Patent Application
20240178247
The present application relates to a hermetic package device and a device module.
Micro Electro Mechanical Systems (MEMS) devices, which are devices in which sensors, actuators, etc. are integrated on a silicon substrate, etc. by microfabrication technology, have been put into practical use. Examples of MEMS devices include an infrared sensor, a gyro sensor, an accelerometer, and the like.
Among infrared sensors, an uncooled infrared sensor converts incoming infrared light into heat, as referred to as a thermal sensor. Therefore, the sensor (image sensing element) has a configuration in which a temperature change of a target object is read out as a change of an electric signal, and has an adiabatic structure that is thermally isolated from a base material in order to increase the detection sensitivity. Specifically, the infrared sensor is disposed in a hermetically sealed vacuum space, that is, inside a vacuum package, to enhance the thermal insulation. In this case, it is known that a material used as a lid of the vacuum package is ZnS or silicon containing low oxygen with high infrared transmittance, or an anti-reflection coating (AR coating) is formed on the material.
On the other hand, as a method of manufacturing a vacuum package, a wafer-level package has been proposed in which a wafer on which MEMS devices are manufactured and a lid wafer facing the device wafer are bonded in a vacuum atmosphere to form a plurality of vacuum packages (Refer to, for example, Patent Document 1).
A device formed using the wafer-level package inevitably has a structure in which bonding pads for electrical connection provided on the device wafer are exposed from the lid wafer, and the part for the bonding in the device wafer protrudes relative to the lid wafer. In such a structure where one side thereof protrudes, there have been problems in which stress concentration occurs in a portion where the sealing part on the protruding side of the device wafer is in contact with the device wafer, causing cracks in the device wafer and malfunction of the device due to circuit breakage, wiring disconnection, etc.
The present application discloses a technology to solve the above problems, and an object thereof is to prevent device wafer cracking and obtain a highly reliable hermetic package device.
A hermetic package device disclosed in the present application includes a device wafer in which a semiconductor circuit and terminals for electrical connection to an outside are provided on a mounting surface, a lid wafer arranged to be opposed to the mounting surface of the device wafer, and a sealing part that surrounds an installation region of the semiconductor circuit in the mounting surface, is interposed between the device wafer and the lid wafer, and forms a hermetically sealed space in a vacuum atmosphere to house the semiconductor circuit between the device wafer and the lid wafer. A second installation region in the mounting surface in which the terminals are provided protrudes relative to the lid wafer, and an outer surface of a portion in the sealing part facing the second installation region is inclined such that a position thereon approaches the second installation region when getting closer from the device wafer toward the lid wafer.
According to the hermetic package device or device module disclosed in the present application, the stress at the portion where the sealing part is in contact with the device wafer can be relieved, so that cracking of the device wafer can be prevented and a highly reliable hermetic package device can be obtained.
Hereinafter, hermetic package devices according to embodiments of the present application are described on the basis of the drawings. Note that, in the following drawings, the same or corresponding parts will be given the same reference number and the description thereof will not be repeated.
First, a basic configuration of the hermetic package device will be is described. In the hermetic package device 100, as shown in
The sealing material layer 60 is a solder material and has low wettability to the surface of the device wafer 1 (mounting surface 1ff) and the surface of the lid wafer 2 (opposed surface 2ff), making it difficult to bond the device wafer 1 and the lid wafer 2 as they are. Therefore, the first under-layer 61 and the second under-layer 62 are formed of a material with good wettability to the solder material and good adhesion to each wafer so as to function as an intermediate layer for bonding each wafer and the sealing material layer 60.
A hermetically sealed space 100s surrounded by the device wafer 1, the lid wafer 2, and the sealing part 6 is maintained in a vacuum atmosphere by the sealing part 6 formed in this way. In order to secure the vacuum volume, the sealing part 6 is formed with a thickness of about 50 to 150 μm, and in the present embodiment, it has a thickness of 100 μm. Although the inside of the hermetically sealed space 100s is in a vacuum atmosphere, it does not mean a complete vacuum, but only a degree of vacuum necessary to maintain the thermal insulation. If the pressure is lower than that of the outside air at least to an extent that it is a factor for the stress occurrence, the need to relieve the stress to be described later arises.
In the region inside the sealing part 6 of the device wafer 1, that is, in the hermetically sealed space 100s, an image sensing element 3 for infrared light, a scanning circuit 4, and a readout circuit 5 each are arranged and maintained in a vacuum atmosphere with excellent thermal insulation, thereby enhancing the reliability as the infrared sensor. Note that the MEMS and a semiconductor element that include the image sensing element 3, the scanning circuit 4, and the readout circuit 5 are collectively referred to as a semiconductor circuit 7. In addition, a plurality of bonding pads 8 (terminals) electrically connected to the image sensing element 3, the scanning circuit 4, and the readout circuit 5 via wiring (not shown) are arranged in a region of the device wafer 1 outside the sealing part 6 and in the part protruding relative to the lid wafer 2.
On the other hand, on the lid wafer 2, a gas adsorbent (not shown) called a getter for maintaining the degree of vacuum is formed at a portion surrounded by the second under-layer 62. In addition, a recess may be formed to increase the vacuum volume.
Further, an anti-reflection coating called an AR coating may be formed on the outer surface of the lid wafer 2 (the surface opposite to the opposed surface 2ff) to improve the infrared transmittance. When the bonding pads 8 of the hermetic package device 100 thus configured are electrically connected to a circuit board (not shown) or the like, with wires or the like, an device module 1000 (
On the basis of the above configuration, a characteristic configuration of the hermetic package device 100 in the present application will be described. In the hermetic package device 100 of the present application, as shown in
Next, in order to verify an effect of the inverted trapezoid, several kinds of test specimens were prepared using the dimension ΔP of the positional shift as a parameter, and results of reliability tests will be explained. The horizontal axis in
Further, the vertical axis shows each of the stresses at the intersection point P1x and the intersection point P2x, which is normalized by the stress at the intersection point P1x when the dimension ΔP of the positional shift is zero. Here, the first under-layer 61 and the second under-layer 62 are so-called nickel strikes having multilayer structures made of titanium (Ti) of 0.1 μm in thickness, copper (Cu) of 0.3 μm, and nickel (Ni) of 1 to 5 μm from the respective wafer sides. Then, assuming that the thickness of the sealing part 6 including these is 100 μm, the value of stress that occurs when a temperature change of −100 degrees C. is generated is used. Note that the thickness of the sealing part 6 of each test specimen was within the range of 90+20 μm.
As shown in
In the case of a test specimen in which the dimension ΔP of the positional shift was 0, that is, an under-layer of the same width (W61=W62) was formed on each of the device wafer 1 and the lid wafer 2, a crack occurred in a portion at the intersection point P1x between the device wafer 1 and the outer surface 6fx, resulting in malfunction of the sensor. In contrast, no malfunction occurred in test specimens whose dimension ΔP of the positional shift was increased from 0 to 50 μm.
However, when the dimension ΔP of the positional shift exceeded 50 μm, a crack occurred in the lid wafer 2. The lid wafer 2 had no semiconductor circuit or wiring, and operated normally as the sensor. However, since there is a concern that a foreign object adheres to the device wafer 1 when the crack occur, the dimension ΔP of the positional shift is suitable to be larger than 0 μm and within a range of 50 μm or less, and can be freely selected within that range.
If the dimension ΔP of the positional shift is kept within the range of 5 to 30 μm, the stress value at both the intersection point P1x and the intersection point P2x can be made lower than that of the intersection point P1x of the case when the malfunction occurs, and the hermetic package device 100 with higher reliability can be obtained. In other words, the preferable range of the set value of the dimension ΔP of the positional shift is from 5 to 30 μm when taking into account the dimensional error in mass production.
The first under-layer 61 of the device wafer 1 and the second under-layer 62 of the lid wafer 2 in each embodiment of the present application each are formed by electrolytic Ni plating. The width W61 and the width W61 by electroplating are achieved using existing photolithography technology, and any desirable width can be selected by the pattern size of a photomask.
For example, if the mounting surface of the device wafer or the opposed surface of the lid wafer is provided with a inclination, it is possible to relieve the stress by blunting the angle with the outer surface of the sealing part without forming the inverted trapezoid. However, in such a case, using a device wafer or a lid wafer prepared by special processing such as forming an inclination in the mounting surface or opposed surface, individual packaging is required, and thus it is unsuitable for mass production.
In contrast, the hermetic package device 100 of the present application can be cut out after packaging collectively without any special processing such as forming the inclination on either the mounting surface 1ff or the opposed surface 2ff. That is, by forming the sealing part 6 with the inverted trapezoidal cross section, the device wafer 1 can be prevented from cracking and the highly reliable hermetic package device 100 can be obtained without impairing mass production efficiency.
In Embodiment 1 described above, an example of relieving the stress by adjusting the range of the dimension of the positional shift was described. In Embodiment 2, an example of relieving the stress by adjusting an inclination of the outer surface of the sealing part will be described.
As for the configuration of the hermetic package device according to Embodiment 2 other than the angle between the device wafer and the outer surface, the same configuration as that of Embodiment 1 can be applied, and the description of the similar part is omitted and
In the hermetic package device 100 according to Embodiment 2, as shown in
The vertical axis shows the stress at each of the intersection point P1x and intersection point P2x, normalized by the stress at the intersection point P1x when the angle θ is 90 degrees. Here, the first under-layer 61 and the second under-layer 62 have multilayer structures of titanium (Ti) of 0.1 μm in thickness, copper (Cu) 0.3 μm and nickel (Ni) 1 to 5 μm from the respective wafer sides, as in Embodiment 1.
As shown in
In the case of a test specimen with an angle θ of 90 degrees, that is, with a rectangular cross section of the sealing part 6, a crack occurred at the portion of the intersection point P1x between the device wafer 1 and the outer surface 6fx, resulting in malfunction of the sensor. In contrast, no malfunction occurred in the test specimens with the angle θ decreased from 90 degrees.
However, when the angle θ was close to 40 degrees, a crack occurred in the lid wafer 2. The lid wafer 2 had no semiconductor circuit or wiring, and operated normally as a sensor. However, since there is a concern that a foreign object adheres to the device wafer 1 when cracks occur, the angle θ is suitable to be in the range of 60 degrees or more and less than 90 degrees, and can be freely selected within that range.
If the angle θ is kept within the range of 70 degrees or more and 85 degrees or less, both the stress values at the portion of intersection point P1x and the intersection point P2x can be made lower than the stress value of the intersection point P1x in the case where the malfunction occurred, and a more reliable hermetic package device 100 can be obtained. In other words, if dimensional errors and other factors at the time of mass production are also taken into consideration, the more favorable range of a set value of the angle θ is 70 degrees or more and 85 degrees or less.
The above results were similar to the case where the thickness of the sealing part 6 was changed or when the center positions of the first under-layer 61 and the second under-layer 62 were shifted. That is, by setting the angle θ of the outer surface 6fx with respect to the mounting surface 1ff within the range described above, it is possible to prevent the device wafer 1 from cracking and achieve the effect of obtaining a highly reliable hermetic package device 100 without impairing mass production efficiency.
The first under-layer 61 of the device wafer 1 and the second under-layer 62 of the lid wafer 2 in Embodiment 2 of the present application are respectively formed by electrolytic Ni plating. The width W61, the width W61, and the positional relationship thereof for defining the angle θ are achieved using existing photolithography technology, and it is possible to set a desirable angle θ by the pattern size of a photomask.
In addition, lead-free solder is used for the sealing material layer 60 in the hermetic package device 100 of the present application, and a desirable thickness of the sealing part 6 (including the thickness of the first under-layer 61 and the second under-layer 62) can be obtained by adjusting the amount of lead-free solder for use. Therefore, by adjusting each of the widths W61, W62 and each of the positions of the first under-layer 61 and the second under-layer 62, and the thickness of the sealing part 6, a desirable angle θ can be obtained.
In Embodiment 1 or Embodiment 2 described above, the example of making the cross-sectional shape of the sealing part symmetrical and inverted trapezoidal has been described, but this is not a limitation. In Embodiment 3, an example will be described in which the inclination is provided only on the outer surface where the stress relief is necessary, and the inner surface is not intentionally inclined or is less inclined than the outer surface.
Note that, except for the setting of a portion to which the inclination of the sealing part of the hermetic package device according to Embodiment 3 is to be provided, the same configuration as that in Embodiment 1 or Embodiment 2 can be applied, and the description of the same part is omitted and
As shown in
Furthermore, in the region where the bonding pads 8 are arranged, the width W61 of the first under-layer 61 of the device wafer 1 can be made larger by inclining the outer surface 6fx larger than the inner surface 6fi within the setting range, as compared with the case where both surfaces are inclined equally. It is effective when there is no room to reduce the width W61 of the first under-layer 61 on the device wafer 1 or when the width W62 of the first under-layer 61 of the lid wafer 2 cannot be enlarged, due to layout constraint of the semiconductor circuit 7.
The width W61 of the first under-layer 61 and the width W62 of the second under-layer 62 affect the hermeticity, and if they are too narrow, it may lead to deterioration of the hermeticity over time. However, for the portions where the device operation is not affected by a crack caused by the stress concentration, a nearly vertical structure is to be adopted in which inclination is not intentionally provided as in the case of a typical sealing part. Or, the inner surface 6fi is to be less inclined than the outer surface 6fx. By doing so, the hermetic package device 100 with high hermeticity and reliable device operation can be obtained without impairing mass production efficiency.
In Embodiment 1 to Embodiment 3 described above, the case where the bonding pads are provided on one side of the hermetic package device was described, but it is not a limitation. A case in which the bonding pads are provided on two or more sides of a hermetic package device will be described in Embodiment 4.
In the hermetic package device according to Embodiment 4, as for the configuration except for the arrangement of the bonding pads and the setting of portions in relation to the arrangement, to which the inclination of the sealing part is to be provided, the same configuration as that of Embodiment 1 to Embodiment 3 can be applied, and the explanation of the similar part is omitted, and
In the hermetic package device 100 according to Embodiment 4, as shown in
The cross-sectional shape of the portions of the sealing part 6 facing the region where the bonding pads 8 are formed is such that, for example, the inner surface 6fi and the outer surface 6fx are uniformly inclined in order for the shape to be inverted trapezoid as in Embodiment 1 or Embodiment 2, as shown in
Even when the bonding pads 8 are provided on multiple sides of the device wafer 1, the same effect as in Embodiment 1 and Embodiment 2 or Embodiment 3 can be achieved by providing the inclination as shown in
In Embodiment 5, a device module will be described in which the hermetic package device described above in Embodiment 1 to Embodiment 4 is mounted on a circuit board together with other electronic components.
As shown in
The device module 1000 according to Embodiment 5 is equipped with the hermetic package device 100 described in any of Embodiment 1 to Embodiment 4 to be robust against vibration and shock. For example, when using the hermetic package device 100 that functions as an infrared sensor, it is possible to obtain a highly reliable infrared sensor that is robust against vibration and shock, and prevents cracking of the device wafer.
Note that, although various exemplary embodiments and examples are described in the present application, various features, aspects, and functions described in one or more embodiments are not limited to the application exemplified in a particular embodiment and can be applicable alone or in their various combinations to each embodiment. Accordingly, countless variations that are not illustrated are envisaged within the scope of the art disclosed herein. For example, the case where at least one component is modified, added or omitted, and the case where at least one component is extracted and combined with a component in another embodiment disclosed are included.
The example of forming the first under-layer 61 and the second under-layer 62 using the electrolytic Ni plating have been described, but the electrolytic plating is not a limitation, and for example, electroless plating, a sputtering method, or a metal organic chemical vapor deposition (MO-CVD) method can be adopted as the forming method. In addition, the method of adjusting the width W61 of the first under-layer 61 and the width W62 of the second under-layer 62 using photolithography has been described. However, the photolithography is not a limitation, and a method of printing, inkjet, or mask sputtering can be employed.
Further, the example of setting the dimension ΔP of the positional shift, or the angle of inclination θ by the width W61 of the first under-layer 61 and the width W62 of the second under-layer 62 has been shown, but it is not a limitation. For example, if the mounting surface 1ff and the opposed surface 2ff themselves have affinity with the material constituting the sealing material layer 60, the cross-sectional shape (dimension ΔP of positional shift, angle θ) of the sealing part 6 may be set by forming a layer made of a non-affinity material outside the regions where the first under-layer 61 and the second under-layer 62 were assumed. Alternatively, the sealing material layer 60 may be selectively adhered to the mounting surface 1ff and the opposed surface 2ff by making the surface roughness of the regions where the first under-layer 61 and the second under-layer 62 were assumed to be formed larger than other portions.
Furthermore, although the example of using lead-free solder for the sealing material layer 60 has been described, the material of the solder is not limited to this, a desirable material can be selected, and the material of the under-layers can be changed accordingly. However, the lead-free solder is preferred to high-temperature solder or AuSn, because of its high environmental impact and a high price. In addition, although the example using the thermosetting adhesive 600 has been described for fixing the hermetic package device 100 and the semiconductor device 300, the material of the adhesive is not limited to this, and a desirable material can be selected. However, since a UV-cured type adhesive shrinks more during curing, the thermosetting type adhesive is more suitable.
As described above, the hermetic package device 100 according to the present application includes the device wafer 1 in which the semiconductor circuit 7 and the terminals (bonding pads 8) for electrical connection to an outside are provided on the mounting surface 1ff, the lid wafer 2 arranged to be opposed to the mounting surface 1ff of the device wafer 1, and the sealing part 6 that surrounds the installation region of the semiconductor circuit 7 in the mounting surface 1ff, is interposed between the device wafer 1 and the lid wafer 2, and forms the hermetically sealed space 100s in a vacuum atmosphere to house the semiconductor circuit 7 between the device wafer 1 and the lid wafer 2. The second installation region in the mounting surface 1ff in which the terminals (bonding pads 8) are provided protrudes relative to the lid wafer 2, and the outer surface 6fx of the portion in the sealing part 6 facing the second installation region is formed to be inclined such that a position thereon approaches the second installation region when getting closer from the device wafer 1 toward the lid wafer 2. Because of the above, it is possible to prevent the device wafer 1 from cracking and obtain a highly reliable hermetic package device 100 without impairing mass production efficiency.
In particular, when the sealing part 6 is formed of the first under-layer 61 patterned on the mounting surface 1ff of the device wafer 1, the second under-layer 62 patterned in the lid wafer 2 on the opposed surface 2ff of the mounting surface 1ff, and the sealing material layer 60 for filling between the first under-layer 61 and the second under-layer 62, and when, in the portion in the sealing part 6 facing the second installation region, the end of the second under-layer 62 on the side near the second installation region (intersection point P2x) has a positional shift toward the second installation region with respect to the end of the first under-layer 61 on the side near the second installation region (intersection point P1x), the above-mentioned inclination can be accurately formed.
In this case, if the dimension ΔP of the positional shift, is within the range of 50 μm or less, cracking of the device wafer 1 can be reliably prevented.
More preferably, if the dimension ΔP of the positional shift is within the range of 5 to 30 μm, cracking of the lid wafer 2 is also prevented and reliability is enhanced.
In addition, if lead-free solder is used for the sealing material layer 60 and nickel is used for the first under-layers 61 and the second under-layers 62, the cross-sectional shape of the sealing part 6 can be set reliably.
Alternatively, if the angle θ formed by the outer surface 6fx with respect to the mounting surface 1ff is within the range of 60 degrees or more and less than 90 degrees, cracking of the device wafer 1 can be reliably prevented.
More preferably, if the angle θ formed by the outer surface 6fx with respect to the mounting surface 1ff is within the range of 70 degrees or more and 85 degrees or less, cracking of the lid wafer 2 is also prevented and the reliability is enhanced.
When the inner surface 6fi of the portion in the sealing part 6 provided with the inclination in the outer surface 6fx is formed to be inclined at an angle gentler than the outer surface 6fx in the opposite direction with respect to the outer surface 6fx, or is upright to the mounting surface 1ff, the sealing width is secured to the extent possible and a highly reliable hermetic package device 100 can be obtained.
When the hermetic package device 100 described above is configured such that the image sensing element 3 for infrared light is used for the semiconductor circuit 7 and an infrared transmission material is used for the lid wafer 2 so as to function as an infrared sensor, a highly reliable infrared sensor can be obtained.
Furthermore, according to the device module 1000 of the present application, a highly reliable device module 1000 can be obtained because the module is configured to include the circuit board 200, the above-described hermetic package device 100 mounted on the circuit board 200, and electronic components (semiconductor device 300, electronic components 400) mounted on the circuit board 200 and electrically connected to the terminals (bonding pads 8).
1: device wafer, 1ff: mounting surface, 2: lid wafer, 2ff: opposed surface, 3: image sensing element, 4: scanning circuit, 5: readout circuit, 6: sealing part, 60: sealing material layer, 61: first under-layer, 62: second under-layer, 6fi: inner surface side, 6fx: outer surface side, 7: semiconductor circuit, 8: bonding pads (terminals), 100: hermetic package device, 100s: hermetically sealed space, 200: circuit board, 200fm: mounting surface, 300: semiconductor device, 400: electronic components, 1000: device module, P1x: intersection point, P2x: intersection point, W61: width, W62: width, ΔP: dimension (of positional shift), θ: angle.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2021/018068 | 5/12/2021 | WO |
