Patent Application
20240036254
This document describes high-capacity optical input/output for data processors.
This section introduces aspects that can help facilitate a better understanding of the disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.
As the input/output (I/O) capacities of electronic processing chips increase, electrical signals may not provide sufficient input/output capacity across the limited size of a practically viable electronic chip package. For example, some data centers include racks of data processing servers (e.g., switch servers) and use optical fibers to transmit optical signals between the data processing servers. Each data processing server receives first optical signals from optical fiber cables, converts the first optical signals to first electrical signals, perform operations (e.g., switching operations) on the first electrical signals to generate second electrical signals, convert the second electrical signals to second optical signals, and outputs the second optical signals through the optical fiber cables.
In a general aspect, a system includes: a first optical input/output module including a plurality of photonic integrated circuits arranged in a two-dimensional pattern including at least three photonic integrated circuits, and at least one data processor that is configured to receive, directly or through an interface circuit, the first electrical signals generated by at least some of the photonic integrated circuits, and to transmit, directly or through the interface circuit, the second electrical signals to at least some of the photonic integrated circuits. Each of at least some of the photonic integrated circuits is configured to receive first optical signals and generate first electrical signals based on the first optical signals, each of at least some of the photonic integrated circuits is configured to receive second electrical signals and generate second optical signals based on the second electrical signals.
Implementations can include one or more of the following features. The first optical input/output module can include a plurality of photonic integrated circuits arranged in a two-dimensional array including at least two rows and at least two columns of photonic integrated circuits.
The first optical input/output module can include a plurality of optical connectors, in which each optical connector is associated with a photonic integrated circuit, and the optical connector is coupled to a first surface of the photonic integrated circuit. The first optical input/output module can include a plurality of sets of first electronic integrated circuits, in which each set of the first electronic integrated circuit is associated with one of the photonic integrated circuits, and each set of the first electronic integrated circuits includes at least two electronic integrated circuits that are coupled to the first surface of the associated photonic integrated circuit.
Each set of first electronic integrated circuits can include two electronic integrated circuits that are positioned on opposite sides of the optical connector along a plane parallel to the first surface of the associated photonic integrated circuit.
Each set of first electronic integrated circuits can include three electronic integrated circuits that surround three sides of the optical connector along a plane parallel to the first surface of the photonic integrated circuit.
Each set of first electronic integrated circuits can include four electronic integrated circuits that surround four sides of the optical connector along a plane parallel to the first surface of the photonic integrated circuit.
Each set of first electronic integrated circuits can include at least one of an electrical drive amplifier or a transimpedance amplifier.
The first optical input/output module can include a substrate, in which the plurality of photonic integrated circuits are mounted on the substrate. The first optical input/output module can include a plurality of sets of second electronic integrated circuits mounted on the substrate, in which each set of second electronic integrated circuits is associated with a photonic integrated circuit and electrically coupled to the photonic integrated circuit through one or more signal conductors and/or traces.
Each set of second electronic integrated circuits can include three electronic integrated circuits that surround three sides of the photonic integrated circuit along a plane parallel to a first surface of the substrate.
Each set of second electronic integrated circuits can include four electronic integrated circuits that surround four sides of the photonic integrated circuit along a plane parallel to a first surface of the substrate.
Each set of second electronic integrated circuits can include a serializers/deserializers module.
Each of at least some of the photonic integrated circuits can include an array of grating couplers, a plurality of optical waveguides coupled to the array of grating couplers, and a plurality of photodetectors coupled to the plurality of optical waveguides.
Each of the at least one data processor can include at least one of a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, an application specific integrated circuit (ASIC), or a data storage device.
The system can include a wafer-scale processing module including a plurality of data processors, in which the first optical input/output module is configured to receive a plurality of first optical signals through at least some of a plurality of optical links, generate a plurality of first electrical signals based on the plurality of first optical signals, and transmit the plurality of first electrical signals to the data processors.
The plurality of data processors can be configured to generate a plurality of second electrical signals that are transmitted to the first optical input/output module, the first optical input/output module can be configured to generate a plurality of second optical signals based on the plurality of second electrical signals, and output the plurality of optical signals through at least some of the plurality of optical links.
The wafer-scale processing module can include a wafer and a two-dimensional arrangement of at least three data processors formed on the wafer.
The two-dimensional arrangement of at least three data processors can include an array of at least two rows and at least two columns of data processors.
The array of data processors can include at least three rows and at least three columns of data processors.
The array of data processors can include at least four rows and at least four columns of data processors.
The first optical input/output module can include at least four photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
The first optical input/output module can include at least eight photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
The first optical input/output module can include at least sixteen photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
The first optical input/output module can include at least thirty-two photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
The first optical input/output module can include at least sixty-four photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
Each of more than half of the photonic integrated circuits in the first optical input/output module can have electronic integrated circuits arranged at four sides of the photonic integrated circuit.
Each of more than 80% of the photonic integrated circuits in the first optical input/output module can have electronic integrated circuits arranged at four sides of the photonic integrated circuit.
The plurality of photonic integrated circuits can be arranged in a staggered array configuration.
The plurality of photonic integrated circuits can include a staggered array of photonic integrated circuits. The staggered array can include a first row, a second row, and a third row. In the first row, the photonic integrated circuits can be positioned at (x, y) coordinates (1, 1), (3, 1), (5, 1), . . . , (n1, 1), n1 being an odd number. In the second row, the photonic integrated circuits can be positioned at (x, y) coordinates (2, 2), (4, 2), (6, 2), . . . , (n2, 2), n2 being an even number. In the third row, the photonic integrated circuits can be positioned at (x, y) coordinates (1, 3), (3, 3), (5, 3), . . . , (n3, 3), n3 being an odd number.
The wafer-scale processing module can have a first edge and a second edge, and the first optical input/output module can be positioned in a vicinity of the first edge. The system can include a second optical input/output module that is positioned in a vicinity of the second edge of the wafer-scale processing module. The second optical input/output module can include a plurality of photonic integrated circuits arranged in a two-dimensional pattern including at least three photonic integrated circuits. Each of at least some of the photonic integrated circuits can be configured to receive third optical signals and generate third electrical signals based on the third optical signals, and each of at least some of the photonic integrated circuits can be configured to receive fourth electrical signals and generate fourth optical signals based on the fourth electrical signals. At least some of the data processors in the wafer-scale processing module can be configured to receive the third electrical signals generated by the second optical input/output module, and to transmit the fourth electrical signals to the second optical input/output module.
The wafer-scale processing module can have a third edge. The system can include a third optical input/output module that is positioned in a vicinity of the third edge of the wafer-scale processing module. The third optical input/output module can include a plurality of photonic integrated circuits arranged in a two-dimensional pattern including at least three photonic integrated circuits, in which each of at least some of the photonic integrated circuits can be configured to receive 5th optical signals and generate 5th electrical signals based on the 5th optical signals, and each of at least some of the photonic integrated circuits can be configured to receive 6th electrical signals and generate 6th optical signals based on the 6th electrical signals. At least some of the data processors in the wafer-scale processing module can be configured to receive the 5th electrical signals generated by the third optical input/output module, and to transmit the 5th electrical signals to the third optical input/output module.
The wafer-scale processing module can have a fourth edge. The system can include a fourth optical input/output module that is positioned in a vicinity of the fourth edge of the wafer-scale processing module. The fourth optical input/output module can include a plurality of photonic integrated circuits arranged in a two-dimensional pattern including at least three photonic integrated circuits, in which each of at least some of the photonic integrated circuits can be configured to receive 7th optical signals and generate 7th electrical signals based on the 7th optical signals, and each of at least some of the photonic integrated circuits can be configured to receive 8th electrical signals and generate 8th optical signals based on the 8th electrical signals. At least some of the data processors in the wafer-scale processing module can be configured to receive the 7th electrical signals generated by the fourth optical input/output module, and to transmit the 8th electrical signals to the fourth optical input/output module.
The first optical input/output module can be configured to support at least 50 Tbps data throughput to the first edge of the wafer-scale processing module.
The second optical input/output module can be configured to support at least 50 Tbps data throughput to the second edge of the wafer-scale processing module.
The third optical input/output module can be configured to support at least 50 Tbps data throughput to the third edge of the wafer-scale processing module.
The fourth optical input/output module can be configured to support at least 50 Tbps data throughput to the fourth edge of the wafer-scale processing module.
The first, second, third, and fourth optical input/output modules can be configured to support an aggregate data throughput of at least 200 Tbps to the wafer-scale processing module.
Each of some of the second electronic integrated circuits can be electrically interconnected to two or more photonic integrated circuits.
Each of some of the second electronic integrated circuits can include a serializers/deserializers module that is configured to condition the electrical signals transmitted to or from two or more photonic integrated circuits.
The first optical input/output module can include two rows of photonic integrated circuits that support an aggregate data throughput of approximately 59.1 Tbps.
The wafer-scale processing module can have a first edge, the first optical input/output module can be positioned in a vicinity of the first edge, and the first optical input/output module can be configured to support an aggregate data throughput per unit edge length of approximately 288 Gbps/mm.
The first optical input/output module can include three rows of photonic integrated circuits that support an aggregate data throughput of approximately 89.6 Tbps.
The wafer-scale processing module can have a first edge, the first optical input/output module can be positioned in a vicinity of the first edge, and the first optical input/output module can be configured to support an aggregate data throughput per unit edge length of approximately 437 Gbps/mm.
The first optical input/output module can include four rows of photonic integrated circuits that support an aggregate data throughput of approximately 118.3 Tbps.
The wafer-scale processing module can have a first edge, the first optical input/output module can be positioned in a vicinity of the first edge, and the first optical input/output module can be configured to support an aggregate data throughput per unit edge length of approximately 576 Gbps/mm.
The first optical input/output module can include five rows of photonic integrated circuits that support an aggregate data throughput of approximately 148.7 Tbps.
The wafer-scale processing module can have a first edge, the first optical input/output module can be positioned in a vicinity of the first edge, and the first optical input/output module can be configured to support an aggregate data throughput per unit edge length of approximately 725 Gbps/mm.
The at least one data processor can include an integrated circuit or a system on a chip (SoC) that includes at least one million transistors.
The wafer-scale processing module can include at least one billion transistors.
The first optical input/output module can include a plurality of co-packaged optical modules, and each co-packaged optical module can include at least one of the photonic integrated circuits.
Each co-packaged optical module can include a first optical connector part that is configured to be removably coupled to a second optical connector part that is attached to a first fiber cable that includes an array of optical fibers.
The fiber cable can include at least 10 cores of optical fibers, and the first optical connector part can be configured to couple at least 10 channels of optical signals to the photonic integrated circuit.
The fiber cable can include at least 100 cores of optical fibers, and the first optical connector part can be configured to couple at least 100 channels of optical signals to the photonic integrated circuit.
The fiber cable can include at least 500 cores of optical fibers, and the first optical connector part can be configured to couple at least 500 channels of optical signals to the photonic integrated circuit.
The fiber cable can include at least 1000 cores of optical fibers, and the first optical connector part can be configured to couple at least 1000 channels of optical signals to the photonic integrated circuit.
The photonic integrated circuit can be configured to generate a plurality of first serial electrical signals based on the received optical signals, in which each first serial electrical signal can be generated based on one of the channels of first optical signals. The co-packaged optical module can include a first serializers/deserializers module including multiple serializer units and deserializer units. The first serializers/deserializers module can be configured to generate a plurality of sets of first parallel electrical signals based on the plurality of first serial electrical signals, and condition the electrical signals, and each set of first parallel electrical signals can be generated based on a corresponding first serial electrical signal. The co-packaged optical module can include a second serializers/deserializers module including multiple serializer units and deserializer units. The second serializers/deserializers module can be configured to generate a plurality of second serial electrical signals based on the plurality of sets of first parallel electrical signals, and each second serial electrical signal can be generated based on a corresponding set of first parallel electrical signals.
The co-packaged optical module can be electrically coupled to a circuit board or a substrate using electrical contacts that include at least one of spring-loaded elements, compression interposers, or land-grid arrays.
The system can include a rackmount server, the housing can include an enclosure for the rackmount server, the rackmount server can have an n rack unit form factor, and n can be an integer in a range from 1 to 8.
In another general aspect, a supercomputer that includes any of the systems described above.
The wafer-scale processing module can include an artificial intelligence processor.
The system can be configured to simulate weather.
The system can be configured to construct and/or support a metaverse that includes one or more virtual environments and enable users to interact with one another in the one or more virtual environments, or interact with objects in the one or more virtual environments.
The system can be configured to construct and/or support a simulated environment for training autonomous vehicles.
In another general aspect, an autonomous vehicle that includes any of the systems or the supercomputer described above.
The autonomous vehicle can include at least one of a car, a truck, a train, a boat, a ship, a submarine, a helicopter, a drone, an airplane, a space rover, or a space ship.
In another general aspect, a robot that includes any of the systems or the supercomputer described above.
The robot can include at least one of an industrial robot, a helper robot, a medical surgery robot, a merchandise delivery robot, a teaching robot, a cleaning robot, a cooking robot, a construction robot, or an entertainment robot.
In another general aspect, a system include a wafer-scale processing module including an array of data processors, and a first optical input/output module including a plurality of photonic integrated circuits arranged in a two-dimensional pattern including at least three photonic integrated circuits. Each of at least some of the photonic integrated circuits can be configured to receive first optical signals and generate first electrical signals based on the first optical signals. Each of at least some of the photonic integrated circuits can be configured to receive second electrical signals and generate second optical signals based on the second electrical signals. At least some of the data processors can be configured to receive the first electrical signals generated by at least some of the photonic integrated circuits, and at least some of the data processors can be configured to transmit the second electrical signals to at least some of the photonic integrated circuits.
Implementations can include one or more of the following features. The first optical input/output module can include an edge interface module that is disposed near an edge of the wafer-scale processor, and can be configured to transmit electrical signals to and receive electrical signals from data processors positioned near the edge of the wafer-scale processing module.
The first optical input/output module can be configured to support at least 50 Tbps data throughput to an edge of the wafer-scale processing module.
The first optical input/output module can be configured to support at least 100 Tbps data throughput to an edge of the wafer-scale processing module.
The wafer-scale processing module can include a semiconductor wafer, and the data processors can be formed on the semiconductor wafer or mounted on the semiconductor wafer. The photonic integrated circuits can be mounted on a substrate. Electrical contacts on the substrate can be electrically coupled to electrical contacts on the semiconductor wafer.
The photonic integrated circuits can be electrically coupled to the data processors through a first set of signal lines on the substrate and a second set of signal lines on the semiconductor wafer. Signal propagation loss for the second set of signal lines on the semiconductor wafer can be higher than the signal propagation loss for the first set of signal lines on the substrate for a given propagation length. A longer signal line in the first set can be coupled to a shorter signal line in the second set, and a shorter signal line in the first set can be coupled to a longer signal line in the second set, to reduce the maximum signal propagation loss for the signals transmitted between the photonic integrated circuits and the data processors.
The first optical input/output module can include a plurality of co-packaged optical (CPO) modules, and each CPO module can include a photonic integrated circuit and an electronic integrated circuit. The electronic integrated circuit can include at least one of (i) an XSR chip, (ii) a driver amplifier, or (iii) a transimpedance amplifier (TIA).
The first optical input/output module can include a substrate and a plurality of co-packaged optical (CPO) modules can be mounted on the substrate. Each CPO module can include a photonic integrated circuit and an electronic integrated circuit. The electronic integrated circuit can include at least one of (i) a driver amplifier, or (ii) a transimpedance amplifier (TIA). The first optical input/output module can include a plurality of XSR-to-XSR converters that are disposed near a first edge of the substrate. The first edge can be positioned near the data processors, and the XSR-to-XSR converters can be configured to regenerate signals transmitted between the CPO modules to the data processors.
The first optical input/output module can include a substrate and a plurality of co-packaged optical (CPO) modules mounted on the substrate. Each CPO module can include a photonic integrated circuit and an electronic integrated circuit. The electronic integrated circuit can include at least one of (i) a driver amplifier, or (ii) a transimpedance amplifier (TIA). The first optical input/output module can include a plurality of XSR-to-LR converters that are disposed near a first edge of the substrate. The first edge can be positioned near the data processors, and the XSR-to-LR converters can be configured to regenerate signals transmitted between the CPO modules and the data processors.
Each of at least a subset of the co-packaged optical (CPO) modules can be surrounded by other CPO modules and does not have any XSR chip between the CPO module and other CPO modules.
The first optical input/output module can include a substrate, in which the photonic integrated circuits are mounted on the substrate. The first optical input/output module can include a plurality of XSR-to-LR converters that are disposed near a first edge of the substrate, in which the first edge can be positioned near the data processors, and the XSR-to-LR converters can be configured to regenerate signals transmitted between the photonic integrated circuits and the data processors.
Each photonic integrated circuit can be driven directly by a corresponding XSR-to-LR converter without a separate driver amplifier or transimpedance amplifier.
In another general aspect, a method includes using a first optical input/output module as a high throughput input to a wafer-scale processing module including an array of data processors, including using the first optical input/output module to support at least 50 Tbps data throughput to a first edge the wafer-scale processing module. The first optical input/output module can include a plurality of photonic integrated circuits arranged in a two-dimensional pattern including at least three photonic integrated circuits. Each of at least some of the photonic integrated circuits can receive first optical signals, generate first electrical signals based on the first optical signals, and transmit the first electrical signals to the wafer-scale processing module. Each of at least some of the photonic integrated circuits can receive second electrical signals from the wafer-scale processing module, generate second optical signals based on the second electrical signals, and output the second optical signals through one or more optical links.
Implementations can include one or more of the following features. The method can include using the first optical input/output module to support at least 100 Tbps data throughput to the first edge of the wafer-scale processing module.
The method can include using a second optical input/output module to support at least 50 Tbps data throughput to a second edge of the wafer-scale processing module.
The method can include using a third optical input/output module to support at least 50 Tbps data throughput to a third edge of the wafer-scale processing module.
The method can include using a fourth optical input/output module to support at least 50 Tbps data throughput to a fourth edge of the wafer-scale processing module. The first, second, third, and fourth optical input/output modules can be configured to support an aggregate data throughput of at least 200 Tbps to the wafer-scale processing module.
In another general aspect, a system includes: a multi-wafer processing module including: a first wafer-scale processing module, and a second wafer-scale processing module. The first wafer-scale processing module includes a first array of data processors and a first optical input/output module, in which the first optical input/output module includes at least three photonic integrated circuits arranged in a two-dimensional pattern. The second wafer-scale processing module includes a second array of data processors and a second optical input/output module, in which the second optical input/output module includes at least three photonic integrated circuits arranged in a two-dimensional pattern. The multi-wafer processing module includes one or more optical fibers that optically connect the first optical input/output module to the second input/output module. The first optical input/output module, the second optical input/output module, and the one or more optical fibers provide one or more optical communication links between the first array of data processors and the second array of data processors.
Implementations can include one or more of the following features. The first wafer-scale processing module and the second wafer-scale processing module can be positioned side-by-side, the first array of data processors and the second array of data processors can face a same direction.
The first wafer-scale processing module can include a first substrate, the first array of data processors can be coupled to the first substrate, the second wafer-scale processing module can include a second substrate, the second array of data processors can be coupled to the second substrate. The first and second wafer-scale processing modules can be vertically stacked such that the first array of data processors face toward the second array of data processors, wherein the first and second arrays of data processors are positioned between the first and second substrates.
The first substrate can include a first semiconductor wafer, and the second substrate can include a second semiconductor wafer.
The system can include a first shared power supply positioned between the first wafer-scale processing module and the second wafer-scale processing module, in which the first shared power supply is configured to provide power to the first array of data processors and the second array of data processors.
The system can include a first shared cooling device positioned between the first wafer-scale processing module and the second wafer-scale processing module, in which the first shared cooling device is configured to remove heat from the first array of data processors and the second array of data processors.
The system can include a third wafer-scale processing module including a third array of data processors and a third optical input/output module, in which the third optical input/output module includes at least three photonic integrated circuits arranged in a two-dimensional pattern. The first, second, and third wafer-scale processing modules can be vertically stacked together.
The system can include a second shared power supply positioned between the second wafer-scale processing module and the third wafer-scale processing module, in which the second shared power supply is configured to provide power to the second array of data processors and the third array of data processors.
The system can include a second shared cooling device positioned between the second wafer-scale processing module and the third wafer-scale processing module, in which the second shared cooling device is configured to remove heat from the second array of data processors and the third array of data processors.
The system can include a fourth wafer-scale processing module including a fourth array of data processors and a fourth optical input/output module, in which the fourth optical input/output module includes at least three photonic integrated circuits arranged in a two-dimensional pattern. The first, second, third, and fourth wafer-scale processing modules can be vertically stacked together.
The system can include a third shared power supply positioned between the third wafer-scale processing module and the fourth wafer-scale processing module, in which the third shared power supply is configured to provide power to the third array of data processors and the fourth array of data processors.
The system can include a third shared cooling device positioned between the third wafer-scale processing module and the fourth wafer-scale processing module, in which the third shared cooling device is configured to remove heat from the third array of data processors and the fourth array of data processors.
The second wafer-scale processing module can include a second substrate, the second array of data processors can be coupled to the second substrate, the third wafer-scale processing module can include a third substrate, the third array of data processors can be coupled to the third substrate, and a back side of the second substrate can face a back side of the third substrate.
The second shared power supply can provide power to the second array of data processors through conductive lines that pass through the second substrate, and the second shared power supply can provide power to the third array of data processors through conductive lines that pass through the third substrate.
The second shared cooling device can remove heat from the second array of data processors through thermally conductive paths that pass through the second substrate, and the second shared cooling device can remove heat from the third array of data processors through thermally conductive paths that pass through the third substrate.
In another general aspect, a system includes: a large scale multi-wafer processing module including: two or more multi-wafer processing modules arranged in a two-dimensional array, in which each multi-wafer processing module includes two or more wafer-scale processing modules vertically stacked together. At least one wafer-scale processing module communicates with another wafer-scale processing modules through optical communication links.
Implementations can include one or more of the following features. Each wafer-scale processing module can include an array of data processors and an optical input/output module, in which a first wafer-scale processing module is optically linked to a second wafer-scale processing module through a first optical input/output module of the first wafer-scale processing module, a second optical input/output module of the second wafer-scale processing module, and an optical fiber cable that connects the first optical input/output module to the second optical input/output module.
In another general aspect, a system includes: a processing module including: at least one data processor coupled directly or indirectly to a first substrate; and a first optical input/output module including at least three photonic integrated circuits coupled directly or indirectly to a second substrate, the at least three photonic integrated circuits arranged in a two-dimensional pattern, the at least three photonic integrated circuits including three photonic integrated circuits arranged in a pattern forming a triangle. Each of the at least three photonic integrated circuits includes at least three vertical couplers arranged in a two-dimensional pattern, the at least three vertical couplers including three vertical couplers arranged in a pattern forming a triangle. The photonic integrated circuits are configured to convert input optical signals received at the vertical couplers to input electrical signals that are transmitted directly or indirectly to the at least one data processor.
Implementations can include one or more of the following features. The at least one data processor can include a plurality of data processors arranged in a two dimensional pattern, and the plurality of data processors can include three data processors arranged in a pattern forming a triangle.
The at least three photonic integrated circuits can include N1 photonic integrated circuits, N1 is an integer that is greater than or equal to 3, each photonic integrated circuit can include at least N2 vertical couplers configured to receive input optical signals from fiber cores, N1 is an integer that is greater than or equal to 3. The first optical input/output module can provide an interface between the at least one data processor and N1 bundles of fiber cores, each bundle of fiber cores can be coupled to the vertical couplers of a corresponding photonic integrated circuit, and each bundle of fiber cores can include at least N2 fiber cores.
The at least three photonic integrated circuits can include at least 10 photonic integrated circuits, and each photonic integrated circuit can include at least 10 vertical couplers configured to receive input optical signals from corresponding fiber cores. The first optical input/output module can provide an interface between the at least one data processor and 10 bundles of fiber cores, and each bundle of fiber cores can include at least 10 fiber cores.
The at least one data processor can include a wafer-scale processor including a plurality of data processors. The processing module can include an edge processing module positioned near an edge of the wafer-scale processor, and the edge processing module can include the first optical input/output module.
The wafer-scale processor can include a plurality of data processors that have a footprint of at least 10 cm×10 cm, and each data processor can include at least one million transistors.
The plurality of data processors can have a footprint of at least 15 cm×15 cm.
The plurality of data processors can have a footprint of at least 20 cm×20 cm.
The edge processing module can be configured to support a communication interface of at least 500 Gbps data throughput between the wafer-scale processor and a plurality of optical fibers.
The edge processing module can be configured to support a communication interface of at least 1 tetra bps data throughput between the wafer-scale processor and a plurality of optical fibers.
The edge processing module can be configured to support a communication interface of at least 1.5 tetra bps data throughput between the wafer-scale processor and a plurality of optical fibers.
In another general aspect, a system includes: a processing module including: a wafer-scale processor including an array of at least 4 rows and 4 columns of data processors, in which each data processor includes at least one million transistors, the wafer-scale processor includes 4 edges, the wafer-scale processor is configured to be capable of a data processing throughput of at least 500 Gbps. The processing module includes four edge processing modules, in which each edge processing module is positioned near a corresponding edge of the wafer scale processor, each edge processing module includes an array of at least 2 rows and at least 8 columns of photonic integrated circuits, each photonic integrated circuit includes at least 2 rows and at least 8 columns of vertical couplers that are configured to receive input optical signals from optical fiber cores or transmit output optical signals to optical fiber cores. The four edge processing modules provide communication interfaces between the wafer-scale processor and the optical fiber cores.
Other aspects include other combinations of the features recited above and other features, expressed as methods, apparatus, systems, program products, and in other ways.
Interconnecting electronic chip packages using optical signals can have the advantage that the optical signals can be delivered with a higher input/output capacity per unit area compared to electrical input/outputs.
Particular embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages. The data processing system has a high power efficiency, a low construction cost, a low operation cost, and high flexibility in reconfiguring optical network connections. The thermal solutions described in this document allow efficient dissipation of heat generated by data processors that process large amounts of data carried by fiber optic cables.
The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the invention will become apparent from the description, the drawings, and the claims.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In case of conflict with patent applications or patent application publications incorporated herein by reference, the present specification, including definitions, will control.
The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to-scale. The dimensions of the various features can be arbitrarily expanded or reduced for clarity.
This document describes a novel thermal design for a system for high bandwidth data processing. The system includes novel input/output interface modules for coupling bundles of optical fibers to data processing integrated circuits (e.g., network switches, central processing units, graphics processor units, tensor processing units, digital signal processors, and/or other application specific integrated circuits (ASICs)) that process the data transmitted through the optical fibers. In some implementations, the data processing integrated circuit is mounted on a circuit board (or substrate or a combination of circuit board(s) and substrate(s)) positioned near the input/output interface module through a relatively short electrical signal path on the circuit board (or substrate or a combination of circuit board(s) and substrate(s)). The input/output interface module can include a first connector that allows a user to conveniently connect or disconnect the input/output interface module to or from the circuit board (or substrate or a combination of circuit board(s) and substrate(s)). The input/output interface module can also include a second connector that allows the user to conveniently connect or disconnect the bundle of optical fibers to or from the input/output interface module. In some implementations, a rack mount system having a front panel is provided in which the circuit board (which supports the input/output interface modules and the data processing integrated circuits) (or substrate or a combination of circuit board(s) and substrate(s)) is vertically mounted in an orientation substantially parallel to, and positioned near, the front panel. In some examples, the circuit board (or substrate or a combination of circuit board(s) and substrate(s)) functions as the front panel or part of the front panel. The second connectors of the input/output interface modules face the front side of the rack mount system to allow the user to conveniently connect or disconnect bundles of optical fibers to or from the system.
When many heat-generating components, such as the data processing integrated circuits and the input/output interface modules, are positioned near the front panel of a rackmount system, using the conventional design of placing cooling fans at the rear of the rackmount system may not be sufficient. As described below, in some implementations, the circuit board(s) and/or substrate(s) can be positioned at a distance from the front panel, and many fiber cables and/or fiber guides can be used to connect components coupled to the circuit board(s) and/or substrate(s) to the connectors at the front panel. The multiple fiber cables can impede air flow and reduce heat dissipation. In some implementations, the vertically oriented circuit board(s) and/or substrate(s) are oriented substantially parallel to the front panel and can impede the front-to-back air flow generated by the fans at the rear of the rackmount system. This document describes a novel thermal design that can overcome some of the problems of the conventional thermal design. The novel thermal design provides one or more inlet fans positioned at the front of the rackmount system in addition to the one or more outlet fans at the rear of the rackmount system. The position(s) and orientation(s) of the inlet fan(s), the position(s) and orientation(s) and configuration(s) of the heat dissipating device(s), and (optionally) the use of duct(s) and/or air louver(s) are configured to maximize heat transfer so as to keep the temperature of the data processing integrated circuits and the input/output interface modules within specified temperature limits.
A feature of the novel thermal design is the use of one or more fans that blow air in a direction substantially parallel to the vertically oriented circuit board(s) and/or substrate(s), which can be substantially parallel to the front panel. In this example, a substantial amount of airflow generated by the inlet fan(s) is directed parallel to the front panel of a rackmount system. This is not intuitive since conventional thermal designs have cooling fans that generate front-to-back airflow near the front panel of the rackmount system (which is substantially orthogonal to the front panel). Another feature of the novel thermal design is the use of one or more fans to blow air towards the input/output interface modules coupled to the front side of the circuit board(s) and/or substrate(s), in addition to one or more fans that blow air towards the data processing integrated circuits coupled to the rear side of the circuit board(s) and/or substrate(s). The inventors realized that in a high data throughput system, the amount of heat generated by the input/output interface modules (e.g., optical modules that include photonic integrated circuits that convert optical signals to electrical signals and vice versa, and electronic integrated circuits that condition the electrical signals transmitted to or from the photonic integrated circuits) can be significant, and the cables (or other structures such as fiber guides) coupled to the input/output interface modules may impede air flow, so it is useful to configure one or more fans (and optionally ducts and/or air louvers) dedicated to increase airflow to the input/output interface modules.
In some implementations, a feature of the high bandwidth data processing system is that, by vertically mounting the circuit board that supports the input/output interface modules and the data processing integrated circuits to be near the front panel, or configuring the circuit board as the front panel or part of the front panel, the optical signals can be routed from the optical fibers through the input/output interface modules to the data processing integrated circuits through relatively short electrical signal paths. This allows the signals transmitted to the data processing integrated circuits to have a high bit rate (e.g., over 50 Gbps) while maintaining low crosstalk, distortion, and noise, hence reducing power consumption and footprint of the data processing system.
In some implementations, a feature of the high bandwidth data processing system is that the cost of maintenance and repair can be lower compared to traditional systems. For example, the input/output interface modules and the fiber optic cables are configured to be detachable, a defective input/output interface module can be replaced without taking apart the data processing system and without having to re-route any optical fiber. Another feature of the high bandwidth data processing system is that, because the user can easily connect or disconnect the bundles of the optical fibers to or from the input/output interface modules through the front panel of the rack mount system, the configurations for routing of high bit rate signals through the optical fibers to the various data processing integrated circuits is flexible and can easily be modified. For example, connecting a bundle of hundreds of strands of optical fibers to the optical connector of the rack mount system can be almost as simple as plugging a universal serial bus (USB) cable into a USB port. A further feature of the high bandwidth data processing system is that the input/output interface module can be made using relatively standard, low cost, and energy efficient components so that the initial hardware costs and subsequent operational costs of the input/output interface modules can be relatively low, compared to conventional systems.
In some implementations, optical interconnects can co-package and/or co-integrate optical transponders with electronic processing chips. It is useful to have transponder solutions that consume relatively low power and that are sufficiently robust against significant temperature variations as may be found within an electronic processing chip package. In some implementations, high speed and/or high bandwidth data processing systems can include massively spatially parallel optical interconnect solutions that multiplex information onto relatively few wavelengths and use a relatively large number of parallel spatial paths for chip-to-chip interconnection. For example, the relatively large number of parallel spatial paths can be arranged in two-dimensional arrays using connector structures such as those disclosed in U.S. Pat. No. 11,287,585, and incorporated herein by reference in its entirety.
Some end-to-end communication paths can pass through an optical power supply module 103 (e.g., see the communication path between the nodes 101_2 and 101_6). For example, the communication path between the nodes 101_2 and 101_6 can be jointly established by the optical fiber links 102_7 and 1028, whereby light from the optical power supply module 103 is multiplexed onto the optical fiber links 102_7 and 102_8.
Some end-to-end communication paths can pass through one or more optical multiplexing units 104 (e.g., see the communication path between the nodes 101_2 and 101_6). For example, the communication path between the nodes 101_2 and 101_6 can be jointly established by the optical fiber links 102_10 and 102_11. Multiplexing unit 104 is also connected, through the link 1029, to receive light from the optical power supply module 103 and, as such, can be operated to multiplex said received light onto the optical fiber links 10210 and 102_11.
Some end-to-end communication paths can pass through one or more optical switching units 105 (e.g., see the communication path between the nodes 101_1 and 101_4). For example, the communication path between the nodes 101_1 and 101_4 can be jointly established by the optical fiber links 102_3 and 102_12, whereby light from the optical fiber links 102_3 and 102_4 is either statically or dynamically directed to the optical fiber link 102_12.
As used herein, the term “network element” refers to any element that generates, modulates, processes, or receives light within the system 100 for the purpose of communication. Example network elements include the node 101, the optical power supply module 103, the optical multiplexing unit 104, and the optical switching unit 105.
Some light distribution paths can pass through one or more network elements. For example, optical power supply module 103 can supply light to the node 101_4 through the optical fiber links 1027, 102_4, and 102_12, letting the light pass through the network elements 101_2 and 105.
Various elements of the communication system 100 can benefit from the use of optical interconnects, which can use photonic integrated circuits comprising optoelectronic devices, co-packaged and/or co-integrated with electronic chips comprising integrated circuits.
As used herein, the term “photonic integrated circuit” (or PIC) should be construed to cover planar lightwave circuits (PLCs), integrated optoelectronic devices, wafer-scale products on substrates, individual photonic chips and dies, and hybrid devices. A substrate can be made of, e.g., one or more ceramic materials, or organic “high density build-up” (HDBU). The ceramic materials can include, e.g., low temperature co-fired ceramics (LTCC). Example material systems that can be used for manufacturing various photonic integrated circuits can include but are not limited to III-V semiconductor materials, silicon photonics, silica-on-silicon products, silica-glass-based planar lightwave circuits, polymer integration platforms, lithium niobate and derivatives, nonlinear optical materials, etc. Both packaged devices (e.g., wired-up and/or encapsulated chips) and unpackaged devices (e.g., dies) can be referred to as planar lightwave circuits.
Photonic integrated circuits are used for various applications in telecommunications, instrumentation, and signal-processing fields. In some implementations, a photonic integrated circuit uses optical waveguides to implement and/or interconnect various circuit components, such as for example, optical switches, couplers, routers, splitters, multiplexers/demultiplexers, filters, modulators, phase shifters, lasers, amplifiers, wavelength converters, optical-to-electrical (O/E) and electrical-to-optical (E/O) signal converters, etc. For example, a waveguide in a photonic integrated circuit can be an on-chip solid light conductor that guides light due to an index-of-refraction contrast between the waveguide's core and cladding. A photonic integrated circuit can include a planar substrate onto which optoelectronic devices are grown by an additive manufacturing process and/or into which optoelectronic devices are etched by a subtractive manufacturing processes, e.g., using a multi-step sequence of photolithographic and chemical processing steps.
In some implementations, an “optoelectronic device” can operate on both light and electrical currents (or voltages) and can include one or more of: (i) an electrically driven light source, such as a laser diode; (ii) an optical amplifier; (iii) an optical-to-electrical converter, such as a photodiode; and (iv) an optoelectronic component that can control the propagation and/or certain properties (e.g., amplitude, phase, polarization) of light, such as an optical modulator or a switch. The corresponding optoelectronic circuit can additionally include one or more optical elements and/or one or more electronic components that enable the use of the circuit's optoelectronic devices in a manner consistent with the circuit's intended function. Some optoelectronic devices can be implemented using one or more photonic integrated circuits.
As used herein, the term “integrated circuit” (IC) should be construed to encompass both a non-packaged die and a packaged die. In a typical integrated circuit-fabrication process, dies (chips) are produced in relatively large batches using wafers of silicon or other suitable material(s). Electrical and optical circuits can be gradually created on a wafer using a multi-step sequence of photolithographic and chemical processing steps. Each wafer is then cut (“diced”) into many pieces (chips, dies), each containing a respective copy of the circuit that is being fabricated. Each individual die can be appropriately packaged prior to being incorporated into a larger circuit or be left non-packaged.
The term “hybrid circuit” can refer to a multi-component circuit constructed of multiple monolithic integrated circuits, and possibly some discrete circuit components, all attached to each other to be mountable on and electrically connectable to a common base, carrier, or substrate. A representative hybrid circuit can include (i) one or more packaged or non-packaged dies, with some or all of the dies including optical, optoelectronic, and/or semiconductor devices, and (ii) one or more optional discrete components, such as connectors, resistors, capacitors, and inductors. Electrical connections between the integrated circuits, dies, and discrete components can be formed, e.g., using patterned conducting (such as metal) layers, ball-grid arrays, solder bumps, wire bonds, etc. Electrical connections can also be removable, e.g., by using land-grid arrays and/or compression interposers. The individual integrated circuits can include any combination of one or more respective substrates, one or more redistribution layers (RDLs), one or more interposers, one or more laminate plates, etc.
In some embodiments, individual chips can be stacked. As used herein, the term “stack” refers to an orderly arrangement of packaged or non-packaged dies in which the main planes of the stacked dies are substantially parallel to each other. A stack can typically be mounted on a carrier in an orientation in which the main planes of the stacked dies are parallel to each other and/or to the main plane of the carrier.
A “main plane” of an object, such as a die, a photonic integrated circuit, a substrate, or an integrated circuit, is a plane parallel to a substantially planar surface thereof that has the largest sizes, e.g., length and width, among all exterior surfaces of the object. This substantially planar surface can be referred to as a main surface. The exterior surfaces of the object that have one relatively large size, e.g., length, and one relatively small size, e.g., height, are typically referred to as the edges of the object.
Referring to
In some embodiments, the integrated optical communication device 210 can be connected to the electronic processor integrated circuit 240 using traces 231 embedded in one or more layers of the package substrate 230. In some embodiments, the processor integrated circuit 240 can include monolithically embedded therein an array of serializers/deserializers (SerDes) 247 electrically coupled to the traces 231. In some embodiments, the processor integrated circuit 240 can include electronic switching circuitry, electronic routing circuitry, network control circuitry, traffic control circuitry, computing circuitry, synchronization circuitry, time stamping circuitry, and data storage circuitry. In some implementations, the processor integrated circuit 240 can be a network switch, a central processing unit, a graphics processor unit, a tensor processing unit, a digital signal processor, or an application specific integrated circuit (ASIC).
Because the electronic processor integrated circuit 240 and the integrated communication device 210 are both mounted on the package substrate 230, the electrical connectors or traces 231 can be made shorter, as compared to mounting the electronic processor integrated circuit 240 and the integrated communication device 210 on separate circuit boards. Shorter electrical connectors or traces 231 can transmit signals that have a higher data rate with lower noise, lower distortion, and/or lower crosstalk.
In some implementations, the electrical connectors or traces can be configured as differential pairs of transmission lines, e.g., in a ground-signal-ground-signal-ground configuration. In some examples, the speed of such signal links can be 10 Gbps or more; 56 Gbps or more; 112 Gbps or more; or 224 Gbps or more.
In some implementations, the integrated optical communication device 210 further includes a first optical connector part 213 having a first surface 213_1 and a second surface 213_2. The connector part 213 is configured to receive a second optical connector part 223 of the fiber-optic connector assembly 220, optically coupled to the connector part 213 through the surfaces 213_1 and 223_2. In some embodiments the connector part 213 can be removably attached to the connector part 223, as indicated by a double-arrow 234, e.g., through a hole 235 in the package substrate 230. In some embodiments the connector part 213 can be permanently attached to the connector part 223. In some embodiments, the connector parts 213 and 223 can be implemented as a single connector element combining the functions of both the connector parts 213 and 223.
In some implementations, the optical connector part 223 is attached to an array of optical fibers 226. In some embodiments, the array of optical fibers 226 can include one or more of: single-mode optical fiber, multi-mode optical fiber, multi-core optical fiber, polarization-maintaining optical fiber, dispersion-compensating optical fiber, hollow-core optical fiber, or photonic crystal fiber. In some embodiments, the array of optical fibers 226 can be a linear (1D) array. In some other embodiments, the array of optical fibers 226 can be a two-dimensional (2D) array. For example, the array of optical fibers 226 can include 2 or more optical fibers, 4 or more optical fibers, 10 or more optical fibers, 100 or more optical fibers, 500 or more optical fibers, or 1000 or more optical fibers. Each optical fiber can include, e.g., 2 or more cores, or 10 or more cores, in which each core provides a distinct light path. Each light path can include a multiplex of, e.g., 2 or more, 4 or more, 8 or more, or 16 or more serial optical signals, e.g., by use of wavelength division multiplexing channels, polarization-multiplexed channels, coherent quadrature-multiplexed channels. The connector parts 213 and 223 are configured to establish light paths through the first main surface 211_1 of the substrate 211. For example, the array of optical fibers 226 can includes n1 optical fibers, each optical fiber can include n2 cores, and the connector parts 213 and 223 can establish n1×n2 light paths through the first main surface 211_1 of the substrate 211. Each light path can include a multiplex of n3 serial optical signals, resulting in a total of n1×n2×n3 serial optical signals passing through the connector parts 213 and 223. In some embodiments, the connector parts 213 and 223 can be implemented, e.g., as disclosed in U.S. Pat. No. 11,287,585.
In some implementations, the integrated optical communication device 210 further includes a photonic integrated circuit 214 having a first main surface 214_1 and a second main surface 214_2. The photonic integrated circuit 214 is optically coupled to the connector part 213 through its first main surface 214_1, e.g., as disclosed in in U.S. Pat. No. 11,287,585. For example, the connector part 213 can be configured to optically couple light to the photonic integrated circuit 214 using optical coupling interfaces, e.g., vertical grating couplers or turning mirrors. In the example above, a total of n1×n2×n3 serial optical signals can be coupled through the connector parts 213 and 223 to the photonic integrated circuit 214. Each serial optical signal is converted to a serial electrical signal by the photonic integrated circuit 214, and each serial electrical signal is transmitted from the photonic integrated circuit 214 to a deserializer unit, or a serializer/deserializer unit, described below.
In some embodiments, the connector part 213 can be mechanically connected (e.g., glued) to the photonic integrated circuit 214. The photonic integrated circuit 214 can contain active and/or passive optical and/or opto-electronic components including optical modulators, optical detectors, optical phase shifters, optical power splitters, optical wavelength splitters, optical polarization splitters, optical filters, optical waveguides, or lasers. In some embodiments, the photonic integrated circuit 214 can further include monolithically integrated active or passive electronic elements such as resistors, capacitors, inductors, heaters, or transistors.
In some implementations, the integrated optical communication device 210 further includes an electronic communication integrated circuit 215 configured to facilitate communication between the array of optical fibers 226 and the electronic processor integrated circuit 240. A first main surface 215_1 of the electronic communication integrated circuit 215 is electrically coupled to the second main surface 214_2 of the photonic integrated circuit 214, e.g., through solder bumps, copper pillars, etc. The first main surface 215_1 of the electronic communication integrated circuit 215 is further electrically connected to the second main surface 211_2 of the substrate 211 through the array of electrical contacts 212_2. In some embodiments, the electronic communication integrated circuit 215 can include electrical pre-amplifiers and/or electrical driver amplifiers electrically coupled, respectively, to photodetectors and modulators within the photonic integrated circuit 214 (see also
For example, the electronic communication integrated circuit 215 includes a first serializers/deserializers module that includes multiple serializer units and multiple deserializer units, and a second serializers/deserializers module that includes multiple serializer units and multiple deserializer units. The first serializers/deserializers module includes the first array of serializers/deserializers 216. The second serializers/deserializers module includes the second array of serializers/deserializers 217.
In some implementations, the first and second serializers/deserializers modules have hardwired functional units so that which units function as serializers and which units function as deserializers are fixed. In some implementations, the functional units can be configurable. For example, the first serializers/deserializers module is capable of operating as serializer units upon receipt of a first control signal, and operating as deserializer units upon receipt of a second control signal. Likewise, the second serializers/deserializers module is capable of operating as serializer units upon receipt of a first control signal, and operating as deserializer units upon receipt of a second control signal.
Signals can be transmitted between the optical fibers 226 and the electronic processor integrated circuit 240. For example, signals can be transmitted from the optical fibers 226 to the photonic integrated circuit 214, to the first array of serializers/deserializers 216, to the second array of serializers/deserializers 217, and to the electronic processor integrated circuit 240. Similarly, signals can be transmitted from the electronic processor integrated circuit 240 to the second array of serializers/deserializers 217, to the first array of serializers/deserializers 216, to the photonic integrated circuit 214, and to the optical fibers 226.
In some implementations, the electronic communication integrated circuit 215 is implemented as a first integrated circuit and a second integrated circuit that are electrically coupled each other. For example, the first integrated circuit includes the array of serializers/deserializers 216, and the second integrated circuit includes the array of serializers/deserializers 217.
In some implementations, the integrated optical communication device 210 is configured to receive optical signals from the array of optical fibers 226, generate electrical signals based on the optical signals, and transmit the electrical signals to the electronic processor integrated circuit 240 for processing. In some examples, the signals can also flow from the electronic processor integrated circuit 240 to the integrated optical communication device 210. For example, the electronic processor integrated circuit 240 can transmit electronic signals to the integrated optical communication device 210, which generates optical signals based on the received electronic signals, and transmits the optical signals to the array of optical fibers 226.
In some implementations, the photodetectors of the photonic integrated circuit 214 convert the optical signals transmitted in the optical fibers 226 to electrical signals. In some examples, the photonic integrated circuit 214 can include transimpedance amplifiers for amplifying the currents generated by the photodetectors, and drivers for driving output circuits (e.g., driving optical modulators). In some examples, the transimpedance amplifiers and drivers are integrated with the electronic communication integrated circuit 215. For example, the optical signal in each optical fiber 226 can be converted to one or more serial electrical signals. For example, one optical fiber can carry multiple signals by use of wavelength division multiplexing. The optical signals (and the serial electrical signals) can have a high data rate, such as 50 Gbps, 100 Gbps, or more. The first serializers/deserializers module 216 converts the serial electrical signals to sets of parallel electrical signals. For example, each serial electrical signal can be converted to a set of N parallel electrical signals, in which N can be, e.g., 2, 4, 8, 16, or more. The first serializers/deserializers module 216 conditions the serial electrical signals upon conversion into sets of parallel electrical signals, in which the signal conditioning can include, e.g., one or more of clock and data recovery, and signal equalization. The first serializers/deserializers module 216 sends the sets of parallel electrical signals to the second serializers/deserializers module 217 through the bus processing unit 218. The second serializers/deserializers module 217 converts the sets of parallel electrical signals to high speed serial electrical signals that are output to the electrical contacts 212_2 and 212_1.
The serializers/deserializers module (e.g., 216, 217) can perform functions such as fixed or adaptive signal pre-distortion on the serialized signal. Also, the parallel-to-serial mapping can use a serialization factor M different from N, e.g., 50 Gbps at the input to the first serializers/deserializers module 216 can become 50×1 Gbps on a parallel bus, and two such parallel buses from two serializers/deserializers modules 216 having a total of 100×1 Gbps can then be mapped to a single 100 Gbps serial signal by the serializers/deserializers module 217. An example of the bus processing unit 218 for performing such mapping is shown in
In some implementations, the package substrate 230 can include connectors on the bottom side that connects the package substrate 230 to another circuit board, such as a motherboard. The connection can use, e.g., fixed (e.g., by use of solder connection) or removable (e.g., by use of one or more snap-on or screw-on mechanisms). In some examples, another substrate can be provided between the electronic processor integrated circuit 240 and the package substrate 230.
Referring to
The system 250 is similar to the data processing system 200 of
Referring to
The connector parts 266 and 268 can be similar to the connector parts 213 and 223, respectively, of
The photonic integrated circuit 264 has a top main surface and bottom main surface. The terms “top” and “bottom” refer to the orientations shown in the figure. It is understood that the devices described in this document can be positioned in any orientation, so for example the “top surface” of a device can be oriented facing downwards or sideways, and the “bottom surface” of the device can be oriented facing upwards or sideways. A difference between the photonic integrated circuit 264 and the photonic integrated circuit 214 (
The integrated optical communication devices 252 (
Referring to
The integrated optical communication device 282 includes a photonic integrated circuit 284, a circuit board 286, a first serializers/deserializers module 216, a second serializers/deserializers module 217, and a control circuit 287. The photonic integrated circuit 284 can include components that perform functions similar to those of the photonic integrated circuit 214 (
The circuit board 286 has a top main surface 290 and a bottom main surface 292. The photonic integrated circuit 284 has a top main surface 294 and bottom main surface 296. The first and second serializers/deserializers modules 216, 217 are mounted on the top main surface 290 of the circuit board 286. The top main surface 294 of the photonic integrated circuit 284 has electrical terminals that are electrically coupled to corresponding electrical terminals on the bottom main surface 292 of the circuit board 286. In this example, the photonic integrated circuit 284 is mounted on a side of the circuit board 286 that is opposite to the side of the circuit board 286 on which the first and second serializers/deserializers modules 216, 217 are mounted. The photonic integrated circuit 284 is electrically coupled to the first serializers/deserializers 216 by electrical connectors 300 that pass through the circuit board 286 in the thickness direction. In some embodiments, the electrical connectors 300 can be implemented as vias.
The connector part 288 has dimensions that are configured such that the fiber-optic connector assembly 270 can be coupled to the connector part 288 without bumping into other components of the integrated optical communication device 282. The connector part 288 can be configured to optically couple light to the photonic integrated circuit 284 using optical coupling interfaces, e.g., vertical grating couplers or turning mirrors, similar to the way that the connector part 213 or 266 optically couples light to the photonic integrated circuit 214 or 264, respectively.
When the integrated optical communication device 282 is coupled to the package substrate 230, the photonic integrated circuit 284 and the control circuit 287 are positioned between the circuit board 286 and the package substrate 230. The integrated optical communication device 282 includes an array of contacts 298 arranged on the bottom main surface 292 of the circuit board 286. The array of contacts 298 is configured such that after the circuit board 286 is coupled to the package substrate 230, the array of contacts 298 maintains a thickness d3 between the circuit board 286 and the package substrate 230, in which the thickness d3 is slightly larger than the thicknesses of the photonic integrated circuit 284 and the control circuit 287.
An array of electrical terminals 312 arranged on the top main surface 294 of the photonic integrated circuit 284 are electrically coupled to an array of electrical terminals 314 arranged on the bottom main surface 292 of the circuit board 286. The array of electrical terminals 312 and the array of electrical terminals 314 have a fine pitch, in which the minimum distance between two adjacent electrical terminals can be as small as, e.g., 10 μm, 40 μm, or 100 μm. An array of electrical terminals 316 arranged on the bottom main surface of the first serializers/deserializers 216 are electrically coupled to an array of electrical terminals 318 arranged on the top main surface 290 of the circuit board 286. An array of electrical terminals 320 arranged on the bottom main surface of the second serializers/deserializers module 217 are electrically coupled an array of electrical terminals 322 arranged on the top main surface 290 of the circuit board 286.
For example, the arrays of electrical terminals 312, 314, 316, 318, 320, and 322 have a fine pitch (or fine pitches). For simplicity of description, in the example of
An array of electrical terminals 324 arranged on the bottom main surface of the circuit board 286 are electrically coupled to the array of contacts 298. The array of electrical terminals 324 can have a coarse pitch. For example, the minimum distance between adjacent electrical terminals is d1, which can be in the range of, e.g., 200 μm to 1 mm. The array of contacts 298 can be configured as a module that maintains a distance that is slightly larger than the thicknesses of the photonic integrated circuit 284 and the control circuit 287 (which is not shown in
An array 330 of optical coupling components 310 is provided to allow optical signals to be provided to the photonic integrated circuit 284 in parallel. The first serializers/deserializers 216 include an array 332 of electrical terminals 316 arranged on the bottom surface of the first serializers/deserializers 216. The second serializers/deserializers module 217 include an array 334 of electrical terminals 320 arranged on the bottom surface of the second serializers/deserializers module 217. The arrays 332 and 334 of electrical terminals 316, 320 have a fine pitch, and the minimum distance between adjacent terminals can be in the range of, e.g., 40 μm to 200 μm. An array 336 of electrical terminals 324 is arranged on the bottom main surface of the circuit board 286. The array 336 of electrical terminals 324 has a coarse pitch, and the minimum distance between adjacent terminals can be in the range of, e.g., 200 μm to 1 mm. For example, the array 336 of electrical terminals 324 can be part of a compression interposer that has a pitch of about 400 μm between terminals.
The electrical contacts of the serializers/deserializers blocks 216_1 to 216_12 and 217_1 to 217_12 have a fine pitch, and the minimum distance between adjacent terminals can be in the range of, e.g., 40 μm to 200 μm. The electrical contacts 212_1 have a coarse pitch, and the minimum distance between adjacent terminals can be in the range of, e.g., 200 μm to 1 mm.
The integrated optical communication device 374 includes a photonic integrated circuit 352, a combination of drivers and transimpedance amplifiers (D/T) 354, a first serializers/deserializers module 216, a second serializers/deserializers module 217, the first optical connector 356, a control module 358, and a substrate 360. The host application specific integrated circuit 240 includes an embedded third serializers/deserializers module 247.
In this example, the photonic integrated circuit 352, the drivers and transimpedance amplifiers 354, the first serializers/deserializers module 216, and the second serializers/deserializers module 217 are mounted on the top side of the substrate 360. In some embodiments, the drivers and transimpedance amplifiers 354, the first serializers/deserializers module 216, and the second serializers/deserializers module 217 can be monolithically integrated into a single electrical chip. The first optical connector 356 is optically coupled to the bottom side of the photonic integrated circuit 352. The control module 358 is electrically coupled to electrical terminals arranged on the bottom side of the substrate 360, whereas the photonic integrated circuit 352 is connected to electrical terminals arranged on the top side of the substrate 360. The control module 358 is electrically coupled to the photonic integrated circuit 352 through electrical connectors 362 that pass through the substrate 360 in the thickness direction. In some embodiments, the substrate 360 can be removably connected to the package substrate 230, e.g., using a compression interposer or a land grid array.
The photonic integrated circuit 352 is electrically coupled to the drivers and transimpedance amplifiers 354 through electrical connectors 364 on or in the substrate 360. The drivers and transimpedance amplifiers 354 are electrically coupled to the first serializers/deserializers module 216 by electrical connectors 366 on or in the substrate 360. The second serializers/deserializers module 216 has electrical terminals 370 on the bottom side that are electrically coupled to electrical terminals 366 arranged on the bottom side of the substrate 360 through electrical connectors 368 that pass through the substrate 360 in the thickness direction. The electrical terminals 370 have a fine pitch, whereas the electrical terminals 366 have a coarse pitch. The electrical terminals 366 are electrically coupled to the third serializers/deserializers module 247 through electrical connectors or traces 372 on or in the package substrate 230.
In some implementations, optical signals are converted by the photonic integrated circuit 352 to electrical signals, which are conditioned by the first serializers/deserializers module 216 (or the second serializers/deserializers module 217), and processed by the host application specific integrated circuit 240. The host application specific integrated circuit 240 generates electrical signals that are converted by the photonic integrated circuit 352 into optical signals.
The photonic integrated circuit 392 receives optical signals from a first optical connector 404, generates serial electrical signals based on the optical signals, sends the serial electrical signals to the first and second serializers/deserializers modules 394 and 398. The first and second serializers/deserializers modules 394 and 398 generate parallel electrical signals based on the received serial electrical signals, and send the parallel electrical signals to the third and fourth serializers/deserializers modules 396 and 400, respectively. The third and fourth serializers/deserializers modules 396 and 400 generate serial electrical signals based on the received parallel electrical signals, and send the serial electrical signals to electrical terminals 406 and 408, respectively, arranged on the bottom side of the substrate 410.
The first optical connector 404 is optically coupled to the bottom side of the photonic integrated circuit 392. In some embodiments, the optical connector 404 can also be placed on the top of the photonic integrated circuit 392 and couple light to the top side of the photonic integrated circuit 392 (not shown in the figure). The first optical connector 404 is optically coupled to a second optical connector, which in turn is optically coupled to a plurality of optical fibers. In the configuration shown in
In some implementations, the integrated optical communication device 402 (or 408) can be modified such that the first optical connector 404 couples optical signals to the top side of the photonic integrated circuit 392 (or 422).
A first serializers/deserializers module 394, a second serializers/deserializers module 396, a third serializers/deserializers module 398, and a fourth serializers/deserializers module 400 are mounted on the top side of the first slab 516. The photonic integrated circuit 524 is electrically coupled to the first and third serializers/deserializers modules 394 and 398 by electrical connectors 522 that pass through the substrate 514 in the thickness direction. For example, the electrical connectors 522 can be implemented as vias. In some examples, drivers and transimpedance amplifiers can be integrated in the photonic integrated circuit 524, or integrated in the serializers/deserializers modules 394 and 398. In some examples, the drivers and transimpedance amplifiers can be implemented in a separate chip (not shown in the figure) positioned between the photonic integrated circuit 524 and the serializers/deserializers modules 394 and 398, similar to the example in
Complementary metal oxide semiconductor (CMOS) transimpedance amplifier and driver blocks 424 are arranged on the right side of the photonic integrated circuit 424, and CMOS transimpedance amplifier and driver blocks 426 are arranged on the left side of the photonic integrated circuit 424. A first serializers/deserializers module 394 and a second serializers/deserializers module 396 are arranged on the right side of the CMOS transimpedance amplifier and driver blocks 424. A third serializers/deserializers module 398 and a fourth serializers/deserializers module 400 are arranged on the left side of the CMOS transimpedance amplifier and driver blocks 426.
In this example, each of the first, second, third, and fourth serializers/deserializers module 394, 396, 398, 400 includes 8 serial differential transmitter blocks and 8 serial differential receiver blocks. The integrated optical communication device 428 has a width of about 3.5 mm and a length of slightly more than about 3.6 mm.
In some implementations, the electrical terminals (e.g., 406 and 408) can be arranged in a configuration as shown in
The middle rectangle 1022 is a cutout that connects the photonic integrated circuit to the optics that leave from the top of the module. The bigger rectangle 1024 represents the photonic integrated circuit. The two gray rectangles 1026a, 1026b represent circuitry in a serializers/deserializers chip 1028a. The two gray rectangles 1026c, 1026d represent circuitry in another serializers/deserializers chip 1028b. The serializers/deserializers chips are positioned on the top of the package, and the photonic integrated circuit is positioned on the bottom of the package. The overlap between the photonic integrated circuit and the serializers/deserializers chips 1028a, 1028b is designed so that vias (not shown in the figure) can directly connect these integrated circuits through the package. In some implementations, the serializers/deserializers chips 1028a, 1028b and/or other electronic integrated circuits can be placed around three or four sides of the optical connector (represented by the rectangle 1022), similar to the examples shown in
In the examples of the data processing systems shown in
In a first example, the data processing system includes a digital application specific integrated circuit 444 mounted on the top side of a substrate 442, and an integrated optical communication device 448 mounted on the bottom side of the first circuit board. In some implementations, the integrated optical communication device 448 includes a photonic integrated circuit 450 and a set of transimpedance amplifiers and drivers 452 that are mounted on the bottom side of a substrate 454 (e.g., a second circuit board). The top side of the photonic integrated circuit 450 is electrically coupled to the bottom side of the substrate 454. A first optical connector part 456 is optically coupled to the bottom side of the photonic integrated circuit 450. The first optical connector part 456 is configured to be optically coupled to a second optical connector part 458 that is optically coupled to a plurality of optical fibers (not shown in the figure). An array of electrical terminals 460 is arranged on the top side of the substrate 454 and configured to enable the integrated optical communication device 448 to be removably coupled to the substrate 442.
The optical signals from the optical fibers are processed by the photonic integrated circuit 450, which generates serial electrical signals based on the optical signals. The serial electrical signals are amplified by the set of transimpedance amplifiers and drivers 452, which drives the output signals that are transmitted to a serializers/deserializers module 446 embedded in the digital application specific integrated circuit 444.
In a second example, an integrated optical communication device 462 can be mounted on the bottom side of the substrate 442 to provide an optical/electrical communications interface between the optical fibers and the digital application specific integrated circuit 444. The integrated optical communication device 462 includes a photonic integrated circuit 464 that is mounted on the bottom side of a substrate 454 (e.g., a second circuit board). The top side of the photonic integrated circuit 464 is electrically coupled to the bottom side of the substrate 454. A first optical connector part 456 is optically coupled to the bottom side of the photonic integrated circuit 450. An array of electrical terminals 460 is arranged on the top side of the substrate 454 and configured to enable the integrated optical communication device 462 to be removably coupled to the substrate 442. The integrated optical communication device 462 is similar to the integrated optical communication device 448, except that either the photonic integrated circuit 464 or the serializers/deserializers module 446 includes the set of transimpedance amplifiers and driver circuitry. In some examples, the serializers/deserializers module 446 is configured to directly accept electrical signals emerging from photonic integrated circuit 464, e.g., by having a high enough receiver input impedance that converts the photocurrent generated within the photonic integrated circuit 464 to a voltage swing suitable for further electrical processing. For example, the serializers/deserializers module 446 is configured to have a low transmitter output impedance, and provide an output voltage swing that allows direct driving of optical modulators embedded within the photonic integrated circuit 464.
In a third example, an integrated optical communication device 466 can be mounted on the bottom side of the substrate 442 to provide an optical/electrical communications interface between the optical fibers and the digital application specific integrated circuit 444. The integrated optical communication device 466 includes a photonic integrated circuit 468 that is mounted on the top side of a substrate 470 (e.g., a second circuit board). The bottom side of the photonic integrated circuit 468 is electrically coupled to the top side of the substrate 470. A first optical connector part 456 is optically coupled to the bottom side of the photonic integrated circuit 468. An array of electrical terminals 460 is arranged on the top side of the substrate 470 and configured to enable the integrated optical communication device 466 to be removably coupled to the substrate 442. In some examples, either the photonic integrated circuit 468 or the serializers/deserializers module 446 includes the set of transimpedance amplifiers and driver circuitry. In some examples, the serializers/deserializers module 446 is configured to directly accept electrical signals emerging from the photonic integrated circuit 464.
In a fourth example, an integrated optical communication device 472 can be mounted on the bottom side of the substrate 442 to provide an optical/electrical communications interface between the optical fibers and the digital application specific integrated circuit 444. The integrated optical communication device 472 includes a photonic integrated circuit 474 and a set of transimpedance amplifiers and drivers 476 that are mounted on the top side of a substrate 470 (e.g., a second circuit board). The bottom side of the photonic integrated circuit 474 is electrically coupled to the top side of the substrate 470. A first optical connector part 456 is optically coupled to the bottom side of the photonic integrated circuit 468. An array of electrical terminals 460 is arranged on the top side of the substrate 470 and configured to enable the integrated optical communication device 466 to be removably coupled to the substrate 442. The integrated optical communication device 472 is similar to the integrated optical communication device 466, except that neither the photonic integrated circuit 464 nor the serializers/deserializers module 446 include a set of transimpedance amplifiers and driver circuitry, and the set of transimpedance amplifiers and drivers 476 is implemented as a separate integrated circuit.
In the examples described above, such as those shown in
For example, the bus processing unit 218 can re-map the lanes of signals and perform coding on the signals, such that the bit rate and/or modulation format of the serial signals output from the transmitters TX5, TX6, TX7, TX8 can be different from the bit rate and/or modulation format of the serial signals received at the receivers RX1, RX2, RX3, RX4. For example, 4 lanes of T Gbps NRZ serial signals received at the receivers RX1, RX2, RX3, RX4 can be re-encoded and routed to transmitters TX5, TX6 to output 2 lanes of 2×T Gbps PAM4 serial signals.
Similarly, serial electrical signals received at the receivers RX5, RX6, RX7, RX8 are converted to parallel electrical signals and routed by the bus processing unit 218 to the transmitters TX1, TX2, TX3, TX4, which convert the parallel electrical signals to serial electrical signals. For example, the electronic processor integrated circuit or host application specific integrated circuit can send serial electrical signals to the receivers RX5, RX6, RX7, RX8, and the transmitters TX1, TX2, TX3, TX4 can transmit serial electrical signals to the photonic integrated circuit.
For example, the bus processing unit 218 can re-map the lanes of signals and perform coding on the signals, such that the bit rate and/or modulation format of the serial signals output from the transmitters TX1, TX2, TX3, TX4 can be different from the bit rate and/or modulation format of the serial signals received at the receivers RX5, RX6, RX7, RX8. For example, 2 lanes of 2×T Gbps PAM4 serial signals received at receivers RX5, RX6 can be re-encoded and routed to the transmitters TX5, TX6, TX7, TX8 to output 4 lanes of T Gbps NRZ serial signals.
Similarly, serial electrical signals received at the receivers RX3, RX4, RX7, RX8 are converted to parallel electrical signals and routed by the bus processing unit 218 to the transmitters TX1, TX2, TX5, TX6, which convert the parallel electrical signals to serial electrical signals. For example, the electronic processor integrated circuit or host application specific integrated circuit can send serial electrical signals to the receivers RX3, RX4, RX7, RX8, and the transmitters TX1, TX2, TX5, TX6 can transmit serial electrical signals to the photonic integrated circuit.
In some implementations, the bus processing unit 218 can re-map the lanes of signals and perform coding on the signals, such that the bit rate and/or modulation format of the serial signals output from the transmitters TX3, TX4, TX7, TX8 can be different from the bit rate and/or modulation format of the serial signals received at the receivers RX1, RX2, RX5, RX6. Similarly, the bus processing unit 218 can re-map the lanes of signals and perform coding on the signals such that the bit rate and/or modulation format of the serial signals output from the transmitters TX1, TX2, TX5, TX6 can be different from the bit rate and/or modulation format of the serial signals received at the receivers RX4, RX4, RX7, RX8.
Multiple serializers/deserializers blocks can be electrically coupled to multiple serializers/deserializers blocks through a bus processing unit that can be, e.g., a parallel bus of electrical lanes, a static or a dynamically reconfigurable cross-connect device, or a re-mapping device (gearbox).
In some other examples, the bus processing unit 538 can allow for redundancy to increase reliability. For example, the first and the second serializers/deserializers blocks 532 and 534 can be jointly configured to serially interface to a total of N lanes of T×N (N−k) Gbps electrical signals, while the third serializers/deserializers block 536 can be configured to serially interface to N lanes of T Gbps electrical signals. The bus processing unit 538 can then be configured to remap the data from only N−k out of the N lanes serially interfacing to the first and the second serializers/deserializers blocks 532 and 534 (carrying an aggregate bit rate of (N−k)×T×N (N−k)=T×N) to the third serializers/deserializers block 536. This way, the bus processing unit 538 allows for k out of N serially interfacing electrical links to the first and the second serializers/deserializers blocks 532 and 534 to fail while still maintaining an aggregate of T×N Gbps of data serially interfacing to the third serializers/deserializers block 536. The number k is a positive integer. In some embodiments, k can be approximately 1% of N. In some other embodiments, k can be approximately 10% of N. In some embodiment, the selection of which N-k of the N serially interfacing electrical links to the first and the second serializers/deserializers blocks 532 and 534 to remap to the third serializers/deserializers block 536 using bus processing unit 538 can be dynamically selected, e.g., based on signal integrity and signal performance information extracted from the serially interfacing signals by the serializers/deserializers blocks 532 and 534. An example of the bus processing unit 538 is shown in
In some examples, using the redundancy technique discussed above, the bus processing unit 538 enables N lanes of T×N (N−k) Gbps serial electrical signals to be remapped into N/M lanes of M×T Gbps serial electrical signals. The bus processing unit 538 enables k out of N serially interfacing electrical links to fail while still maintaining an aggregate of T×N Gbps of data serially interfacing to the third serializers/deserializers block 536.
The connector assembly 220 includes a connector 223 and a fiber array 226. The connector 223 can include multiple individual fiber-optic connectors 423_i (i∈{R1 . . . RM; S1 . . . SK; T1 . . . TN} with K, M, and N being positive integers). In some embodiments, some or all of the individual connectors 423_i can form a single physical entity. In some embodiments some or all of the individual connectors 423_i can be separate physical entities. When operating as part of the network element 101_1 of the system 100, (i) the connectors 423_S1 through 423_SK can be connected to optical power supply 103, e.g., through link 1026, to receive supply light; (ii) the connectors 423_R1 through 423_RM can be connected to the transmitters of the node 101_2, e.g., through the link 102_1, to receive from the node 1012 optical communication signals; and (iii) the connectors 423_T1 through 423_TN can be connected to the receivers of the node 101_2, e.g., through the link 102_1, to transmit to the node 101_2 optical communication signals.
In some implementations, the communication device 210 includes an electronic communication integrated circuit 215, a photonic integrated circuit 214, a connector part 213, and a substrate 211. The connector part 213 can include multiple individual optical connectors 413_i to photonic integrated circuit 214 (i∈{R1 . . . RAM; S1 . . . SK; T1 . . . TN} with K, M, and N being positive integers). In some embodiments, some or all of the individual connectors 413_i can form a single physical entity. In some embodiments some or all of the individual connectors 413_i can be separate physical entities. The optical connectors 413_i are configured to optically couple light to the photonic integrated circuit 214 using optical coupling interfaces 414, e.g., vertical grating couplers, turning mirrors, etc., as disclosed in U.S. Pat. No. 11,287,585.
In operation, light entering the photonic integrated circuit 214 from the link 102_6 through coupling interfaces 414_S1 through 414_SK can be split using an optical splitter 415. The optical splitter 415 can be an optical power splitter, an optical polarization splitter, an optical wavelength demultiplexer, or any combination or cascade thereof, e.g., as disclosed in U.S. Pat. No. 11,153,670 and in U.S. published patent application US2021/0376950, which is incorporated herein by reference in its entirety. In some embodiments, one or more splitting functions of the splitter 415 can be integrated into the optical coupling interfaces 414 and/or into optical connectors 413. For example, in some embodiments, a polarization-diversity vertical grating coupler can be configured to simultaneously act as a polarization splitter 415 and as a part of optical coupling interface 414. In some other embodiments, an optical connector that includes a polarization-diversity arrangement can simultaneously act as an optical connector 413 and as a polarization splitter 415.
In some embodiments, light at one or more outputs of the splitter 415 can be detected using a receiver 416, e.g., to extract synchronization information as disclosed in U.S. Pat. No. 11,153,670. In various embodiments, the receiver 416 can include one or more p-i-n photodiodes, one or more avalanche photodiodes, one or more self-coherent receivers, or one or more analog (heterodyne/homodyne) or digital (intradyne) coherent receivers. In some embodiments, one or more opto-electronic modulators 417 can be used to modulate onto light at one or more outputs of the splitter 415 data for communication to other network elements.
Modulated light at the output of the modulators 417 can be multiplexed in polarization or wavelength using a multiplexer 418 before leaving the photonic integrated circuit 214 through optical coupling interfaces 414_T1 through 414_TN. In some embodiments, the multiplexer 418 is not provided, i.e., the output of each modulator 417 can be directly coupled to a corresponding optical coupling interface 414.
On the receiver side, light entering the photonic integrated circuit 214 through a coupling interfaces 414_R1 through 414_RM from, e.g., the link 101_2, can first be demultiplexed in polarization and/or in wavelength using an optical demultiplexer 419. The outputs of the demultiplexer 419 are then individually detected using receivers 421. In some embodiments, the demultiplexer 419 is not provided, i.e., the output of each coupling interface 414_R1 through 414_RM can be directly coupled to a corresponding receiver 421. In various embodiments, the receiver 421 can include one or more p-i-n photodiodes, one or more avalanche photodiodes, one or more self-coherent receivers, or one or more analog (heterodyne/homodyne) or digital (intradyne) coherent receivers.
The photonic integrated circuit 214 is electrically coupled to the integrated circuit 215. In some implementations, the photonic integrated circuit 214 provides a plurality of serial electrical signals to the first serializers/deserializers module 216, which generates sets of parallel electrical signals based on the serial electrical signals, in which each set of parallel electrical signal is generated based on a corresponding serial electrical signal. The first serializers/deserializers module 216 conditions the serial electrical signals, demultiplexes them into the sets of parallel electrical signals and sends the sets of parallel electrical signals to the second serializers/deserializers module 217 through a bus processing unit 218. In some implementations, the bus processing unit 218 enables switching of signals and performs line coding and/or error-correcting coding functions. An example of the bus processing unit 218 is shown in
The second serializers/deserializers module 217 generates a plurality of serial electrical signals based on the sets of parallel electrical signals, in which each serial electrical signal is generated based on a corresponding set of parallel electrical signal. The second serializers/deserializers module 217 sends the serial electrical signals through electrical connectors that pass through the substrate 211 in the thickness direction to an array of electrical terminals 500 that are arranged on the bottom surface of the substrate 211. For example, the array of electrical terminals 500 configured to enable the integrated communication device 210 to be easily coupled to, or removed from, the package substrate 230.
In some implementations, the electronic processor integrated circuit 240 includes a data processor 502 and an embedded third serializers/deserializers module 504. The third serializers/deserializers module 504 receives the serial electrical signals from the second serializers/deserializers module 217, and generates sets of parallel electrical signals based on the serial electrical signals, in which each set of parallel electrical signal is generated based on a corresponding serial electrical signal. The data processor 502 processes the sets of parallel signals generated by the third serializers/deserializers module 504.
In some implementations, the data processor 502 generates sets of parallel electrical signals, and the third serializers/deserializers module 504 generates serial electrical signals based on the sets of parallel electrical signals, in which each serial electrical signal is generated based on a corresponding set of parallel electrical signal. The serial electrical signals are sent to the second serializers/deserializers module 217, which generates sets of parallel electrical signals based on the serial electrical signals, in which each set of parallel electrical signal is generated based on a corresponding serial electrical signal. The second serializers/deserializers module 217 sends the sets of parallel electrical signals to the first serializers/deserializers module 216 through the bus processing unit 218. The first serializers/deserializers module 216 generates serial electrical signals based on the sets of parallel electrical signals, in which each serial electrical signal is generated based on a corresponding set of parallel electrical signals. The first serializers/deserializers module 216 sends the serial electrical signals to the photonic integrated circuit 214. The opto-electronic modulators 417 modulate optical signals based on the serial electrical signals, and the modulated optical signals are output from the photonic integrated circuit 214 through optical coupling interfaces 414_T1 through 414_TN.
In some embodiments, supply light from the optical power supply 103 includes an optical pulse train, and synchronization information extracted by the receiver 416 can be used by the serializers/deserializers module 216 to align the electrical output signals of the serializers/deserializers module 216 with respective copies of the optical pulse trains at the outputs of the splitter 415 at the modulators 417. For example, the optical pulse train can be used as an optical power supply at the optical modulator. In some such implementations, the first serializers/deserializers module 216 can include interpolators or other electrical phase adjustment elements.
Referring to
At the front panel 544 are pluggable input/output interfaces 556 that allow the data processing chip 554 to communicate with other systems and devices. For example, the input/output interfaces 556 can receive optical signals from outside of the system 540 and convert the optical signals to electrical signals for processing by the data processing chip 554. The input/output interfaces 556 can receive electrical signals from the data processing chip 554 and convert the electrical signals to optical signals that are transmitted to other systems or devices. For example, the input/output interfaces 556 can include one or more of small form-factor pluggable (SFP), SFP+, SFP28, QSFP, QSFP28, or QSFP56 transceivers. The electrical signals from the transceiver outputs are routed to the data processing chip 554 through electrical connectors on or in the printed circuit board 558.
In the examples shown in
In some implementations, the integrated communication device 574 includes a photonic integrated circuit 586 and an electronic communication integrated circuit 588 mounted on a substrate 594. The electronic communication integrated circuit 588 includes a first serializers/deserializers module 590 and a second serializers/deserializers module 592. The printed circuit board 570 can be similar to the package substrate 230 (
In some examples, the integrated communication device 574 includes a photonic integrated circuit without serializers/deserializers modules, and drivers/transimpedance amplifiers (TIA) are provided separately. In some examples, the integrated communication device 574 includes a photonic integrated circuit and drivers/transimpedance amplifiers but without serializers/deserializers modules.
The integrated communication device 574 includes a first optical connector 578 that is configured to receive a second optical connector 580 that is coupled to a bundle of optical fibers 582. The integrated communication device 574 is electrically coupled to the data processing chip 572 through electrical connectors or traces 584 on or in the printed circuit board 570. Because the data processing chip 572 and the integrated communication device 574 are both mounted on the printed circuit board 570, the electrical connectors or traces 584 can be made shorter, compared to the electrical connectors that electrically couple the transceivers 556 to the data processing chip 554 of
In some examples, the bundle of optical fibers 582 can be firmly attached to the photonic integrated circuit 586 without the use of the first and second optical connectors 578, 580.
The printed circuit board 570 can be secured to the side panels 564 and 566, and the bottom and top panels of the housing using, e.g., brackets, screws, clips, and/or other types of fastening mechanisms. The surface of the printed circuit board 570 can be oriented perpendicular to bottom panel of the housing, or at an angle (e.g., between −60° to 60°) relative to the vertical direction (the vertical direction being perpendicular to the bottom panel). The printed circuit board 570 can have multiple layers, in which the outermost layer (i.e., the layer facing the user) has an exterior surface that is configured to be aesthetically pleasing.
The first optical connector 578, the second optical connector 580, and the bundle of optical fibers 582 can be similar to those shown in
Although
In some examples of the data processing system 540 (
In some implementations, the integrated communication device 612 includes a photonic integrated circuit 614 and an electronic communication integrated circuit 588 mounted on a substrate 618. The electronic communication integrated circuit 588 includes a first serializers/deserializers module 590 and a second serializers/deserializers module 592. The integrated communication device 612 includes a first optical connector 578 that is configured to receive a second optical connector 580 that is coupled to a bundle of optical fibers 582. The integrated communication device 612 is electrically coupled to the data processing chip 572 through electrical connectors or traces 616 that pass through the printed circuit board 610 in the thickness direction. Because the data processing chip 572 and the integrated communication device 612 are both mounted on the printed circuit board 610, the electrical connectors or traces 616 can be made shorter, thereby allowing the signals to have a higher data rate with lower noise, lower distortion, and/or lower crosstalk. Mounting the integrated communication device 612 on the outside of the printed circuit board 610 perpendicular to the bottom panel of the housing and accessible from outside the housing allows for more easily accessible connections to the integrated communication device 612 that may be removed and re-connected without, e.g., removing the housing from a rack.
In some examples, the integrated communication device 612 includes a photonic integrated circuit without serializers/deserializers modules, and drivers and transimpedance amplifiers (TIA) are provided separately. In some examples, the integrated communication device 612 includes a photonic integrated circuit and drivers/transimpedance amplifiers but without serializers/deserializers modules. In some examples, the bundle of optical fibers 582 can be firmly attached to the photonic integrated circuit 614 without the use of the first and second optical connectors 578, 580.
In some examples, the data processing chip 572 is mounted on the rear side of the substrate, and the integrated communication device 612 are removably attached to the front side of the substrate, in which the substrate provides high speed connections between the data processing chip 572 and the integrated communication device 612. For example, the substrate can be attached to a front side of a printed circuit board, in which the printed circuit board includes an opening that allows the data processing chip 572 to be mounted on the rear side of the substrate. The printed circuit board can provide from a motherboard electrical power to the substrate (and hence to the data processing chip 572 and the integrated communication device 612, and allow the data processing chip 572 and the integrated communication device 612 to connect to the motherboard using low-speed electrical links.
The printed circuit board 610 can be secured to the side panels 604 and 606, and the bottom and top panels of the housing using, e.g., brackets, screws, clips, and/or other types of fastening mechanisms. The surface of the printed circuit board 610 can be oriented perpendicular to bottom panel of the housing, or at an angle (e.g., between −60° to 60°) relative to the vertical direction (the vertical direction being perpendicular to the bottom panel). The printed circuit board 610 can have multiple layers, in which the portion of the outermost layer (i.e., the layer facing the user) not covered by the integrated communication device 612 has an exterior surface that is configured to be aesthetically pleasing.
The enclosure 632 has side panels 634 and 636, a rear panel 638, a top panel, and a bottom panel. In some examples, the circuit board 642 is perpendicular to the bottom panel. In some examples, the circuit board 642 is oriented at an angle in a range −60° to 60° relative to a vertical direction of the bottom panel. The side of the circuit board 642 facing the user is configured to be aesthetically pleasing.
The optical/electrical communication interface 644 is electrically coupled to the data processing chip 640 by electrical connectors or traces 646 on or in the circuit board 642. The circuit board 642 can be a printed circuit board that has one or more layers. The electrical connectors or traces 646 can be signal lines printed on the one or more layers of the printed circuit board 642 and provide high bandwidth data paths (e.g., one or more Gigabits per second per data path) between the data processing chip 640 and the optical/electrical communication interface 644.
In a first example, the data processing chip 640 receives electrical signals from the optical/electrical communication interface 644 and does not send electrical signals to the optical/electrical communication interface 644. In a second example, the data processing chip 640 receives electrical signals from, and sends electrical signals to, the optical/electrical communication interface 644. In the first example, the optical/electrical communication interface 644 receives optical signals from optical fibers, generates electrical signals based on the optical signals, and sends the electrical signals to the data processing chip 640. In the second example, the optical/electrical communication interface 644 also receives electrical signals from the data processing chip, generates optical signals based on the electrical signals, and sends the optical signals to the optical fibers.
An optical connector 648 is provided to couple optical signals from the optical fibers to the optical/electrical communication interface 644. In this example, the optical connector 648 passes through an opening in the circuit board 642. In some examples, the optical connector 648 is securely fixed to the optical/electrical communication interface 644. In some examples, the optical connector 648 is configured to be removably coupled to the optical/electrical communication interface 644, e.g., by using a pluggable and releasable mechanism, which can include one or more snap-on or screw-on mechanisms. In some other examples, an array of 10 or more fibers is securely or fixedly attached to the optical connector 648.
The optical/electrical communication interface 644 can be similar to, e.g., the integrated communication device 210 (
The enclosure 658 has side panels 660 and 662, a rear panel 664, a top panel, and a bottom panel. In some examples, the circuit board 654 and the front panel 656 are perpendicular to the bottom panel. In some examples, the circuit board 654 and the front panel 656 are oriented at an angle in a range −60° to 60° relative to a vertical direction of the bottom panel. In some examples, the circuit board 654 is substantially parallel to the front panel 656, e.g., the angle between the surface of the circuit board 654 and the surface of the front panel 656 can be in a range of −5° to 5°. In some examples, the circuit board 654 is at an angle relative to the front panel 656, in which the angle is in a range of −45° to 45°.
The optical/electrical communication interface 652 is electrically coupled to the data processing chip 670 by electrical connectors or traces 666 on or in the circuit board 654, similar to those of the system 630. The signal path between the data processing chip 670 and the optical/electrical communication interface 652 can be unidirectional or bidirectional, similar to that of the system 630.
An optical connector 668 is provided to couple optical signals from the optical fibers to the optical/electrical communication interface 652. In this example, the optical connector 668 passes through an opening in the front panel 656 and an opening in the circuit board 654. The optical connector 668 can be securely fixed, or releasably connected, to the optical/electrical communication interface 652, similar to that of the system 630.
The optical/electrical communication interface 652 can be similar to, e.g., the integrated communication device 210 (
In the examples of
The enclosure 684 has side panels 685 and 686, a rear panel 687, a top panel, and a bottom panel. In some examples, the circuit board 683 is perpendicular to the bottom panel. In some examples, the circuit board 683 is oriented at an angle in a range −60° to 60° (or −30° to 30°, or −10° to 10°, or −1° to 1°) relative to a vertical direction of the bottom panel.
Each of the optical/electrical communication interfaces 682 is electrically coupled to the data processing chip 681 by electrical connectors or traces 688 that pass through the circuit board 683 in the thickness direction. For example, the electrical connectors or traces 688 can be configured as vias of the circuit board 683. The signal paths between the data processing chip 681 and each of the optical/electrical communication interfaces 682 can be unidirectional or bidirectional, similar to those of the systems 630 and 650.
For example, the system 680 can be configured such that signals are transmitted unidirectionally between the data processing chip 681 and one of the optical/electrical communication interfaces 682, and bidirectionally between the data processing chip 681 and another one of the optical/electrical communication interfaces 682. For example, the system 680 can be configured such that signals are transmitted unidirectionally from the optical/electrical communication interface 682a to the data processing chip 681, and unidirectionally from the data processing chip to the optical/electrical communication interface 682b and/or optical/electrical communication interface 682c.
Optical connectors 689a, 689b, 689c (collectively referenced as 689) are provided to couple optical signals from the optical fibers to the optical/electrical communication interfaces 682a, 682b, 682c, respectively. The optical connectors 689 can be securely fixed, or releasably connected, to the optical/electrical communication interfaces 682, similar to those of the systems 630 and 650.
The optical/electrical communication interface 682 can be similar to, e.g., the integrated communication device 210 (
In some examples, the optical/electrical communication interfaces 682 are securely fixed (e.g., by soldering) to the circuit board 683. In some examples, the optical/electrical communication interfaces 682 are removably connected to the circuit board 683, e.g., by use of mechanical mechanisms such as one or more snap-on or screw-on mechanisms. An advantage of the system 680 is that in case of a malfunction at one of the optical/electrical communication interfaces 682, the faulty optical/electrical communication interface 682 can be replaced without opening the enclosure 684.
The enclosure 694b has side panels 695b and 696b, a rear panel 697b, a top panel, and a bottom panel. In some examples, the circuit board 693b is perpendicular to the bottom panel. In some examples, the circuit board 693b is oriented at an angle in a range −60° to 60° (or −30° to 30°, or −10° to 10°, or −1° to 1°) relative to a vertical direction of the bottom panel.
Each of the optical/electrical communication interfaces 692 is electrically coupled to the data processing chip 691b by electrical connectors or traces 698b that pass through the circuit board 693b in the thickness direction. For example, the electrical connectors or traces 698b can be configured as vias of the circuit board 693b. In this example, the electrical connectors or traces 698b extend to both sides of the circuit board 693b (e.g., for connecting to optical/electrical communication interfaces 692 located internal to and external of the enclosure 694b). The signal paths between the data processing chip 691b and each of the optical/electrical communication interfaces 692 can be unidirectional or bidirectional, similar to those of the systems 630, 650 and 680.
For example, the system 690b can be configured such that signals are transmitted unidirectionally between the data processing chip 691b and one of the optical/electrical communication interfaces 692, and bidirectionally between the data processing chip 691b and another one of the optical/electrical communication interfaces 692. For example, the system 690b can be configured such that signals are transmitted unidirectionally from the optical/electrical communication interface 692a to the data processing chip 691b, and unidirectionally from the data processing chip 691b to the optical/electrical communication interface 692b and/or optical/electrical communication interface 692c.
Optical connectors 699a, 699b, 699c (collectively referenced as 699) are provided to couple optical signals from the optical fibers to the optical/electrical communication interfaces 692a, 692b, 692c, respectively. The optical connectors 699 can be securely fixed, or releasably connected, to the optical/electrical communication interfaces 692, similar to those of the systems 630, 650, and 680. In this example, optical connector 699b and optical connector 699c can connect to optical fibers at the front of the enclosure 694b and the optical connector 699a can connect to optical fibers at the rear of the enclosure 694b. In the illustrated example, the optical connector 699a connects to an optical fiber at the rear of the enclosure 694b by being connected to a fiber 1000b that connects to a rear panel interface 1001b (e.g., a backplane, etc.) that is mounted to the rear panel 697b. In some examples, the optical connectors 699 can be securely or fixedly attached to communication interfaces 692. In some examples, the optical connectors 699 can be securely or fixedly attached to an array of optical fibers.
The optical/electrical communication interface 692 can be similar to, e.g., the integrated communication device 210 (
In some examples, the optical/electrical communication interfaces 692 are securely fixed (e.g., by soldering) to the circuit board 693b. In some examples, the optical/electrical communication interfaces 692 are removably connected to the circuit board 693b, e.g., by use of mechanical mechanisms such as one or more snap-on or screw-on mechanisms. An advantage of the system 690b is that in case of a malfunction at one of the optical/electrical communication interfaces 692, the faulty optical/electrical communication interface 692 can be replaced without opening the enclosure 694b.
The enclosure 694c has side panels 695c and 696c, a rear panel 697c, a top panel, and a bottom panel. In some examples, the circuit board 693c is perpendicular to the bottom panel. In some examples, the circuit board 693c is oriented at an angle in a range −60° to 60° (or −30° to 30°, or −10° to 10°, or −1° to 1°) relative to a vertical direction of the bottom panel.
Each of the optical/electrical communication interfaces 692 is electrically coupled to the data processing chip 691c by electrical connectors or traces 698c that pass through the circuit board 693c in the thickness direction. For example, the electrical connectors or traces 698c can be configured as vias of the circuit board 693c. In this example, the electrical connectors or traces 698c extend to both sides of the circuit board 693b (e.g., for connecting to optical/electrical communication interfaces 692 located internal to and external of the enclosure 694b. The signal paths between the data processing chip 691c and each of the optical/electrical communication interfaces 692 can be unidirectional or bidirectional, similar to those of the systems 630, 650 and 680.
For example, the system 690c can be configured such that signals are transmitted unidirectionally between the data processing chip 691c and one of the optical/electrical communication interfaces 692, and bidirectionally between the data processing chip 691c and another one of the optical/electrical communication interfaces 692. For example, the system 690c can be configured such that signals are transmitted unidirectionally from the optical/electrical communication interface 692d to the data processing chip 691c, and unidirectionally from the data processing chip 691c to the optical/electrical communication interface 692e and/or optical/electrical communication interface 692f.
Optical connectors 699d, 699e, 699f (collectively referenced as 699) are provided to couple optical signals from the optical fibers to the optical/electrical communication interfaces 692d, 692e, 692f, respectively. The optical connectors 699 can be securely fixed, or releasably connected, to the optical/electrical communication interfaces 692, similar to those of the systems 630, 650, and 680. In the illustrated example, the optical/electrical communication interfaces 692d and optical connector 699d are oriented differently compared to the optical/electrical communication interfaces 692a and optical connector 699a of
The optical/electrical communication interface 692 can be similar to, e.g., the integrated communication device 210 (
In some examples, the optical/electrical communication interfaces 692 are securely fixed (e.g., by soldering) to the circuit board 693c. In some examples, the optical/electrical communication interfaces 692 are removably connected to the circuit board 693c, e.g., by use of mechanical mechanisms such as one or more snap-on or screw-on mechanisms. An advantage of the system 690c is that in case of a malfunction at one of the optical/electrical communication interfaces 692, the faulty optical/electrical communication interface 692 can be replaced without opening the enclosure 694c.
The enclosure 710 has side panels 712 and 714, a rear panel 716, a top panel, and a bottom panel. In some examples, the circuit board 706 and the front panel 708 are oriented at an angle in a range −60° to 60° relative to a vertical direction of the bottom panel. In some examples, the circuit board 706 is substantially parallel to the front panel 708, e.g., the angle between the surface of the circuit board 706 and the surface of the front panel 708 can be in a range of −5° to 5°. In some examples, the circuit board 706 is at an angle relative to the front panel 708, in which the angle is in a range of −45° to 45°.
For example, the angle can refer to a rotation around an axis that is parallel to the larger dimension of the front panel (e.g., the width dimension in a typical 1U, 2U, or 4U rackmount device), or a rotation around an axis that is parallel to the shorter dimension of the front panel (e.g., the height dimension in the 1U, 2U, or 4U rackmount device). The angle can also refer to a rotation around an axis along any other direction. For example, the circuit board 706 is positioned relative to the front panel such that components such as the interconnection modules, including optical modules or photonic integrated circuits, mounted on or attached to the circuit board 706 can be accessed through the front side, either through one or more openings in the front panel, or by opening the front panel to expose the components, without the need to separate the top or side panels from the bottom panel. Such orientation of the circuit board (or a substrate on which a data processing module is mounted) relative to the front panel also applies to the examples shown in
Each of the optical/electrical communication interfaces 704 is electrically coupled to the data processing chip 702 by electrical connectors or traces 718 that pass through the circuit board 706 in the thickness direction, similar to those of the system 680 (
Optical connectors 716a, 716b, 716c (collectively referenced as 716) are provided to couple optical signals from the optical fibers to the optical/electrical communication interfaces 704a, 704b, 704c, respectively. The optical connectors 716 can be securely fixed, or releasably connected, to the optical/electrical communication interfaces 704, similar to those of the systems 630, 650, and 680.
The optical/electrical communication interface 704 can be similar to, e.g., the integrated communication device 210 (
In some examples, the optical/electrical communication interfaces 704 are securely fixed (e.g., by soldering) to the circuit board 706. In some examples, the optical/electrical communication interfaces 704 are removably connected to the circuit board 706, e.g., by use of mechanical mechanisms such as one or more snap-on or screw-on mechanisms. An advantage of the system 700 is that in case of a malfunction at one of the optical/electrical communication interfaces 704, the faulty optical/electrical communication interface 704 can unplugged or decoupled from the circuit board 706 and replaced without opening the enclosure 710.
In some implementations, the optical/electrical communication interfaces 704 do not protrude through openings in the front panel 708. For example, each optical/electrical communication interface 704 can be at a distance behind the front panel 708, and a fiber patchcord or pigtail can connect the optical/electrical communication interface 704 to an optical connector on the front panel 708, similar to the examples shown in
The enclosure 732 has side panels 736 and 738, a rear panel 740, a top panel, and a bottom panel. In some examples, the circuit board 730 is perpendicular to the bottom panel. In some examples, the circuit board 730 is oriented at an angle in a range −60° to 60° relative to a vertical direction of the bottom panel.
The optical/electrical communication interface 724 includes a photonic integrated circuit 726 mounted on a substrate 728 that is electrically coupled to the circuit board 730. The optical//electrical communication interface 724 is electrically coupled to the data processing chip 722 by electrical connectors or traces 742 that pass through the circuit board 730 in the thickness direction. For example, the electrical connectors or traces 742 can be configured as vias of the circuit board 730. The signal paths between the data processing chip 722 and the optical/electrical communication interface 724 can be unidirectional or bidirectional, similar to those of the systems 630, 650, 680, and 700.
An optical connector 744 is provided to couple optical signals from the optical fibers 734 to the optical/electrical communication interface 724. The optical connector 744 can be securely fixed, or removably connected, to the optical/electrical communication interface 744, similar to those of the systems 630, 650, 680, and 700.
In some implementations, the optical/electrical communication interface 724 can be similar to, e.g., the integrated communication device 448, 462, 466, and 472 of
The optical connector 744 includes a first optical connector 746 and a second optical connector 748, in which the second optical connector 748 is optically coupled to the optical fibers 734. The first optical connector 746 can be similar to, e.g., the first optical connector part 213 (
In some examples, the optical/electrical communication interface 724 is securely fixed (e.g., by soldering) to the circuit board 730. In some examples, the optical/electrical communication interface 724 is removably connected to the circuit board 730, e.g., by use of mechanical mechanisms such as one or more snap-on or screw-on mechanisms. An advantage of the system 720 is that in case of a malfunction of the optical/electrical communication interface 724, the faulty optical/electrical communication interface 724 can be replaced without opening the enclosure 732.
The technique of using a fiber patchcord or pigtail to optically couple the photonic integrated circuit to the optical connector attached to the inner side of the front panel can also be applied to the data processing system 700 of
In the examples of
In each of the examples in
The data processing chips 758 can be similar to, e.g., the electronic processor integrated circuit, data processing chip, or host application specific integrated circuit 240 (
Although the figure shows that the optical/electrical communication interfaces 760 are mounted on the side of the circuit board 752 facing the front panel 754, the optical/electrical communication interfaces 760 can also be mounted on the side of the circuit board 752 facing the interior of the enclosure 756. The optical/electrical communication interfaces 760 can be similar to, e.g., the integrated communication devices 210 (
The circuit board 752 is positioned near a front panel 754 of an enclosure 756, and optical signals are coupled to the optical/electrical communication interfaces 760 through optical paths that pass through openings in the front panel 754. This allows users to conveniently removably connect optical fiber cables 762 to the input/output interfaces 760. The position and orientation of the circuit board 752 relative to the enclosure 756 can be similar to, e.g., those of the circuit board 654 (
In some implementations, the data processing system 750 can include multiple types of optical/electrical communication interfaces 760. For example, some of the optical/electrical communication interfaces 760 can be mounted on the same side of the circuit board 752 as the corresponding data processing chip 758, and some of the optical/electrical communication interfaces 760 can be mounted on the opposite side of the circuit board 752 as the corresponding data processing chip 758. Some of the optical/electrical communication interfaces 760 can include first and second serializers/deserializers modules, and the corresponding data processing chips 758 can include third serializers/deserializers modules, similar to the examples in
Other types of connections may be present and associated with circuit board 752 and other boards included in the enclosure 756. For example, two or more circuit boards (e.g., vertically mounted circuit boards) can be connected which may or may not include the circuit board 752. For instances in which circuit board 752 is connected to at least one other circuit board (e.g., vertically mounted in the enclosure 756), one or more connection techniques can be employed. For example, an optical/electrical communication interface (e.g., similar to optical/electrical communication interfaces 760) can be used to connect data processing chips 758 to other circuit boards. Interfaces for such connections can be located on the same side of the circuit board 752 that the processing chips 758 are mounted. In some implementations, interfaces can be located on another portion of the circuit board (e.g., a side that is opposite from the side that the processing chips 758 are mounted). Connections can utilize other portions of the circuit board 752 and/or one or more other circuit boards present in the enclosure 756. For example an interface can be located on an edge of one or more of the boards (e.g., an upper edge of a vertically mounted circuit board) and the interface can connect with one or more other interfaces (e.g., the optical/electrical communication interfaces 760, another edge mounted interface, etc.). Through such connections, two or more circuit boards can connect, receive and send signals, etc.
In the example shown in
In this example, the system 2000 includes vertically mounted line cards 2040, 2042, 2044. In this particular example, line card 2040 includes an electrical connection sockets/connector 2046 that is connected to electrical cable 2036, and line card 2042 includes an electrical connection sockets/connector 2048 that is connected to electrical cable 2032. Line card 2044 includes an electrical connection sockets/connector 2050. Each of the line cards 2040, 2042, 2044 include pluggable optical modules 2052, 2054, 2056 that can implement various interface techniques (e.g., QSFP, QSFP-DD, XFP, SFP, CFP).
In this particular example, the printed circuit board 2002 is approximate to a forward panel 2058 of the system 2000; however, the printed circuit board 2002 can be positioned in other locations within the system 2000. Multiple printed circuit boards can also be included in the system 2000. For example, a second printed circuit board 2060 (e.g., a backplane) is included in the system 2000 and is located approximate to a back panel 2062. By locating the printed circuit board 2060 towards the rear, signals (e.g., data signals) can be sent to and received from other systems (e.g., another switch box) located, for example, in the same switch rack or other location as the system 2000. In this example, a data processing chip 2064 is mounted to the printed circuit board 2060 that can perform various operations (e.g., data processing, prepare data for transmission, etc.). Similar to the printed circuit board 2002 located forward in the system 2000, the printed circuit board 2060 includes an optical/electrical communication interface 2066 that communicates with the optical/electrical communication interface 2008 (located on the same side on printed circuit board 2002 as data processing chip 2004) using optical fibers 2068. The printed circuit board 2060 includes electrical connection sockets/connectors 2070 that uses the electrical connection cable 2034 to send electrical signals to and receive electrical signals from the electrical connection sockets/connectors 2024. The printed circuit board 2060 can also communicate with other components of the system 2000, for example, one or more of the line cards. As illustrated in the figure, electrical connection sockets/connectors 2072 located on the printed circuit board 2060 uses the electrical connection cable 2074 to send electrical signals to and/or receive electrical signals from the electrical connection sockets/connector 2050 of the line card 2044. Similar to the printed circuit board 2002, other portions of the system 2000 can include timing modules. For example, the line cards 2040, 2042, and 2044 can include timing modules (respectively identified with symbol “*”, “**”, and “***”). Similarly, the second circuit board 2060 can include timing modules such as timing modules 2076 and 2078 for regenerating data, re-timing data, maintaining signal integrity, etc.
A feature of some of the systems described in this document is that the main data processing module(s) of a system, such as switch chip(s) in a switch server, and the communication interface modules that support the main data processing module(s), are configured to allow convenient access by users. In the examples shown in
In some implementations, for a single rack of rackmount servers where there is open space at the front, rear, left, and right side of the rack, in each rackmount server, it is possible to place a first main data processing module and the communication interface modules supporting the first main data processing module near the front panel, place a second main data processing module and the communication interface modules supporting the second main data processing module near the left panel, place a third main data processing module and the communication interface modules supporting the third main data processing module near the right panel, and place a fourth main data processing module and the communication interface modules supporting the fourth main data processing module near the rear panel. The thermal solutions, including the placement of fans and heat dissipating devices, and the configuration of airflows around the main data processing modules and the communication interface modules, are adjusted accordingly.
For example, if a data processing server is mounted to the ceiling of a room or a vehicle, the main data processing module and the communication interface modules can be positioned near the bottom panel for easy access. For example, if a data processing server is mounted beneath the floor panel of a room or a vehicle, the main data processing module and the communication interface modules can be positioned near the top panel for easy access. The housing of the data processing system does not have to be in a box shape. For example, the housing can have curved walls, be shaped like a globe, or have an arbitrary three-dimensional shape.
In some implementations, the photonic integrated circuit 772, the first serializers/deserializers module 776, and the second serializers/deserializers module 780 can be mounted on a substrate of an integrated communication device, an optical/electrical communication interface, or an input/output interface module. The first serializers/deserializers module 776 and the second serializers/deserializers module 780 can be implemented in a single chip. In some implementations, the third serializers/deserializers module 784 can be embedded in the data processor 788, or the third serializers/deserializers module 784 can be separate from the data processor 788.
The data processor 788 generates an eighth set of parallel signals 790 that is sent to the third serializers/deserializers module 784, which generates a sixth serial electrical signal 792 based on the eighth set of parallel signals 790. The sixth serial electrical signal 792 is provided to the second serializers/deserializers module 780, which generates a fourth set of parallel signals 794 based on the sixth serial electrical signal 792. The second serializers/deserializers module 780 can condition the serial electrical signal 792 upon conversion into the fourth set of parallel electrical signals 794. The fourth set of parallel signals 794 is provided to the first serializers/deserializers module 780, which generates a second serial electrical signal 796 based on the fourth set of parallel signals 794 that is sent to the photonic integrated circuit 772. The photonic integrated circuit 772 generates a second optical signal 798 based on the second serial electrical signal 796, and sends the second optical signal 798 to an optical fiber. The first and second optical signals 770, 798 can travel on the same optical fiber or on different optical fibers.
A feature of the system 800 is that the electrical signal paths traveled by the first, fifth, sixth, and second serial electrical signals 774, 782, 792, 796 are short (e.g., less than 5 inches), to allow the first, fifth, sixth, and second serial electrical signals 782, 792 to have a high data rate (e.g., up to 50 Gbps).
In some examples, the data processor 812 processes first data carried in the first optical signal received at the first photonic integrated circuit 772, and generates second data that is carried in the fourth optical signal output from the second photonic integrated circuit 814.
The examples in
In some implementations, signals are transmitted unidirectionally from the photonic integrated circuit 772 to the data processor 788 (
It should be appreciated by those of ordinary skill in the art that the various embodiments described herein in the context of coupling light from one or more optical fibers, e.g., 226 (
The example optical systems disclosed herein should only be viewed as some of many possible embodiments that can be used to perform polarization demultiplexing and independent array pattern scaling, array geometry re-arrangement, spot size scaling, and angle-of-incidence adaptation using diffractive, refractive, reflective, and polarization-dependent optical elements, 3D waveguides and 3D printed optical components. Other implementations achieving the same set of functionalities are also covered by the spirit of this disclosure.
For example, the optical fibers can be coupled to the edges of the photonic integrated circuits, e.g., using fiber edge couplers. The signal conditioning (e.g., clock and data recovery, signal equalization, or coding) can be performed on the serial signals, the parallel signals, or both. The signal conditioning can also be performed during the transition from serial to parallel signals.
In some implementations, the data processing systems described above can be used in, e.g., data center switching systems, supercomputers, internet protocol (IP) routers, Ethernet switching systems, graphics processing work stations, and systems that apply artificial intelligence algorithms.
In the examples described above in which the figures show a first serializers/deserializers module (e.g., 216) placed adjacent to a second serializers/deserializers module (e.g., 217), it is understood that a bus processing unit 218 can be positioned between the first and second serializers/deserializers modules and perform, e.g., switching, re-routing, and/or coding functions described above.
In some implementations, the data processing systems described above includes multiple data generators that generate large amounts of data that are sent through optical fibers to the data processors for processing. For example, an autonomous driving vehicle (e.g., car, truck, train, boat, ship, submarine, helicopter, drone, airplane, space rover, or space ship) or a robot (e.g., an industrial robot, a helper robot, a medical surgery robot, a merchandise delivery robot, a teaching robot, a cleaning robot, a cooking robot, a construction robot, an entertainment robot) can include multiple high resolution cameras and other sensors (e.g., LIDARs (Light Detection and Ranging), radars) that generate video and other data that have a high data rate. The cameras and/or sensors can send the video data and/or sensor data to one or more data processing modules through optical fibers. The one or more data processing modules can apply artificial intelligence technology (e.g., using one or more neural networks) to recognize individual objects, collections of objects, scenes, individual sounds, collections of sounds, and/or situations in the environment of the vehicle and quickly determine appropriate actions for controlling the vehicle or robot.
In some implementations, a data center includes multiple systems, in which each system incorporates the techniques disclosed in
The example of
For example, the photon supply 1256 can correspond to the optical power supply 103 of
The implementation shown in
An external optical power supply or photon supply 1266 provides optical power supply signals, which can be continuous-wave light, one or more trains of periodic optical pulses, or one or more trains of non-periodic optical pulses. The power supply light is provided from the photon supply 1266 to the optical interconnect modules 1258 through optical fibers 1744, 1746a, 1746b, 1746c, respectively. For example, the optical power supply 1266 can provide both pulsed light for data modulation and synchronization, as described in U.S. patent Ser. No. 11/153,670. This allows the high-capacity chip 1262 to be synchronized with the lower-capacity chips 1264a, 1264b, and 1264c.
An external optical power supply or photon supply 1274 provides optical power supply signals, which can be continuous-wave light, one or more trains of periodic optical pulses, or one or more trains of non-periodic optical pulses. For example, the optical power supply 1274 can provide both pulsed light for data modulation and synchronization, as described in U.S. patent Ser. No. 11/153,670. This allows the high-capacity chip 1262 to be synchronized with the lower-capacity chips 1264a and 1264b.
Some aspects of the systems 1250, 1260, and 1270 are described in more detail in connection with
The optical module with connector 868 can be inserted into a first grid structure 870, which can function as both (i) a heat spreader/heat sink and (ii) a mechanical holding fixture for the optical modules with connectors 868. The first grid structure 870 includes an array of receptors, and each receptor can receive an optical module with connector 868. When assembled, the first grid structure 870 is connected to the printed circuit board 862. The first grid structure 870 can be firmly held in place relative to the printed circuit board 862 by sandwiching the printed circuit board 862 in between the first grid structure 870 and a second structure 872 (e.g., a second grid structure) located on the opposite side of the printed circuit board 862 and connected to the first grid structure 870 through the printed circuit board 862, e.g., by use of screws. Thermal vias between the first grid structure 870 and the second structure 872 can conduct heat from the front-side of the printed circuit board 862 to the heat sink 866 on the back-side of the printed circuit board 862. Additional heat sinks can also be mounted directly onto the first grid structure 870 to provide cooling in the front.
The printed circuit board 862 includes electrical contacts 876 configured to electrically connect to the removable optical module with connectors 868 after the removable optical module with connectors 868 are inserted into the first grid structure 870. The first grid structure 870 can include an opening 874 at the location in which the host application specific integrated circuit 864 is mounted on the other side of the printed circuit board 862 to allow for components such as voltage regulators, filters, and/or decoupling capacitors to be mounted on the printed circuit board 862 in immediate lateral vicinity to the host application specific integrated circuit 864.
In some examples, the host application specific integrated circuit 864 is mounted on a substrate (e.g., a ceramic or high-density build-up substrate), and the substrate is attached to the circuit board 862, similar to the examples shown in
The optical module 880 can have any of various configurations, including an optical module containing silicon photonics integrated optics, indium phosphide integrated optics, one or more vertical-cavity surface-emitting lasers (VCSEL)s, one or more direct-detection optical receivers, or one or more coherent optical receivers. The optical module 880 can include any of the optical modules, co-packaged optical modules, integrated optical communication devices (e.g., 448, 462, 466, or 472 of
The optical connector part 882 is inserted through an opening 888 of a substrate 890 and optically coupled to a photonic integrated circuit 896 mounted on the underside of the substrate 890. The substrate 890 can be similar to the substrate 514 of
In some implementations, the upper mechanical part 904, at its underside, is brought in thermal contact with the first serializers/deserializers chip 892 and the second serializers/deserializers chip 894. The upper mechanical part 904 is also brought in thermal contact with the lower mechanical part 902. The lower mechanical part 902 includes a removable latch mechanism, e.g., two wings 906 that can be elastically bent inwards (the movement of the wings 906 are represented by a double-arrow 908 in
Referring to
To remove the optical module 880 from the first grid structure 870, the user can pull the optical fiber connector 950 and cause the balls 962 to disengage from the detents 964. The user can then bend the wings 906 inwards so that the tongues 910 disengage from the grooves 920 on the walls of the first grid structure 870.
In some implementations, the co-packaged optical module 982 includes a mechanical connector structure 984 and a smart optical assembly 986. The smart optical assembly 986 includes, e.g., a photonic integrated circuit (e.g., 896 of
In some examples, the fiber connector 983 includes guide pins 998 that are inserted into holes in the smart optical assembly 986 to improve alignment of optical components (e.g., waveguides and/or lenses) in the fiber connector 983 to optical components (e.g., optical couplers and/or waveguides) in the smart optical assembly 986. In some examples, the guide pins 998 can be chamfered shaped, or elliptical shaped that reduces wear.
In some implementations, after the fiber connector 983 is installed in the co-packaged optical module 982, the fiber connector 983 prevents the co-packaged optical module latches 990 from bending inwards, thus preventing the co-packaged optical module 982 from being inserted into, or released from, the co-packaged optical port 1000. To couple the fiber cable 996 to the data processing system, the co-packaged optical module 982 is first inserted into the co-packaged optical port 1000 without the fiber connector 983, then the fiber connector 983 is inserted into the mechanical connector structure 984. To remove the fiber cable 996 from the data processing system, the fiber connector 983 can be removed from the mechanical connector structure 984 while the co-packaged optical module 982 is still coupled to the co-packaged optical port 1000.
In some implementations, the nested connection latches can be designed to allow the co-packaged optical module 982 to be inserted in, or removed from, the co-packaged optical port 1000 when a fiber cable is connected to the co-packaged optical module 982.
The rackmount systems and rackmount devices described in this document can include, and are not limited to, e.g., rackmount computer servers, rackmount network switches, rackmount controllers, and rackmount signal processors.
For example, the at least one data processing chip can include a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application specific integrated circuit (ASIC). The rackmount server can be, and not limited to, e.g., a rackmount computer server, a rackmount switch, a rackmount controller, a rackmount signal processor, a rackmount storage server, a rackmount multi-purpose processing unit, a rackmount graphics processor, a rackmount tensor processor, a rackmount neural network processor, or a rackmount artificial intelligence accelerator. For example, each co-packaged optical module can include a module similar to the integrated optical communication device 448, 462, 466, or 472 of
For example, the co-packaged optical module can include a first optical connector part (e.g., 456 of
In some examples, the fiber cable can include, e.g., 10 or more cores of optical fibers, and the first optical connector part is configured to couple 10 or more channels of optical signals to the photonic integrated circuit. In some examples, the fiber cable 1076 can include 100 or more cores of optical fibers, and the first optical connector part is configured to couple 100 or more channels of optical signals to the photonic integrated circuit. In some examples, the fiber cable can include 500 or more cores of optical fibers, and the first optical connector part is configured to couple 500 or more channels of optical signals to the photonic integrated circuit. In some examples, the fiber cable can include 1000 or more cores of optical fibers, and the first optical connector part is configured to couple 1000 or more channels of optical signals to the photonic integrated circuit.
In some implementations, the photonic integrated circuit can be configured to generate first serial electrical signals based on the received optical signals, in which each first serial electrical signal is generated based on one of the channels of first optical signals. Each co-packaged optical module can include a first serializers/deserializers module that includes serializer units and deserializer units, in which the first serializers/deserializers module is configured to generate sets of first parallel electrical signals based on the first serial electrical signals and condition the electrical signals, and each set of first parallel electrical signals is generated based on a corresponding first serial electrical signal. Each co-packaged optical module can include a second serializers/deserializers module that includes serializer units and deserializer units, in which the second serializers/deserializers module is configured to generate second serial electrical signals based on the sets of first parallel electrical signals, and each second serial electrical signal is generated based on a corresponding set of first parallel electrical signals.
In some examples, the rackmount server can include 4 or more co-packaged optical modules that are configured to be removably coupled to corresponding second optical connector parts that are attached to corresponding fiber cables. For example, the rackmount server can include 16 or more co-packaged optical modules that are configured to be removably coupled to corresponding second optical connector parts that are attached to corresponding fiber cables. In some examples, each fiber cable can include 10 or more cores of optical fibers. In some examples, each fiber cable can include 100 or more cores of optical fibers. In some examples, each fiber cable can include 500 or more cores of optical fibers. In some examples, each fiber cable can include 1000 or more cores of optical fibers. Each optical fiber can transmit one or more channels of optical signals. For example, the at least one data processing chip can include a network switch that is configured to receive data from an input port associated with a first one of the channels of optical signals, and forward the data to an output port associated with a second one of the channels of optical signals.
In some implementations, the co-packaged optical modules are removably coupled to the vertical printed circuit board. For example, the co-packaged optical modules can be electrically coupled to the vertical printed circuit board using electrical contacts that include, e.g., spring-loaded elements, compression interposers, or land-grid arrays.
A feature of the rackmount units described above is the use of co-packaged optical modules or optical/electrical communication interfaces that have higher bandwidth per module or interface, as compared to conventional designs. For example, each co-packaged optical module or optical/electrical communication interface can be coupled to a fiber cable that carries a large number of densely packed optical fiber cores.
Referring to
The vertically mounted processor blade 12300 includes one or more optical interconnect modules or co-packaged optical modules 12310 mounted on the second side 12306 of the substrate 12302. For example, the optical interconnect module 12310 includes an optical port configured to receive optical signals from an external optical fiber cable, and a photonic integrated circuit configured to generate electrical signals based on the received optical signals, and transmit the electrical signals to the electronic processor 12308. The photonic integrated circuit can also be configured to generate optical signals based on electrical signals received from the electronic processor 12308, and transmit the optical signals to the external optical fiber cable. The optical interconnect module or co-packaged optical module 12310 can be similar to, e.g., the integrated optical communication device 262 of
For example, the substrate 12302 can include electrical connectors that extend from the first side 12304 to the second side 12306 of the substrate 12302, in which the electrical connectors pass through the substrate 12302 in a thickness direction. For example, the electrical connectors can include vias of the substrate 12302. The optical interconnect module 12310 is electrically coupled to the electronic processor 12308 by the electrical connectors. For example, the vertically mounted processor blade 12300 can include an optional optical fiber connector 12312 for connection to an optical fiber cable bundle. The optical fiber connector 12312 can be optically coupled to the optical interconnector modules 12310 through optical fiber cables 12314. The optical fiber cables 12314 can be connected to the optical interconnect modules 12310 through a fixed connector (in which the optical fiber cable 12314 is securely fixed to the optical interconnect module 12310) or a removable connector in which the optical fiber cable 12314 can be easily detached from the optical interconnect module 12310, such as with the use of an optical connector part 266 as shown in
For example, the substrate 12302 can be positioned near from front panel of the housing of the server that includes the vertically mounted processor blade 12300, or away from the front panel and located anywhere inside the housing. For example, the substrate 12302 can be parallel to the front panel of the housing, perpendicular to the front panel, or oriented in any angle relative to the front panel. For example, the substrate 12302 can be oriented vertically to facilitate the flow of hot air and improve dissipation of heat generated by the electronic processor 12308 and/or the optical interconnect modules 12310.
For example, the optical interconnect module or co-packaged optical module 12310 can receive optical signals through vertical or edge coupling.
For example, the optical interconnect modules 12310 can receive optical power from an optical power supply. For example, the optical interconnect modules 12310 can include one or more of optical coupling interfaces 414, demultiplexers 419, splitters 415, multiplexers 418, receivers 421, or modulators 417 of
In some implementations, the vertically mounted processor blades 12300 can include blade pairs, in which each blade pair includes a switch blade and a processor blade. The electronic processor of the switch blade includes a switch, and the electronic processor of the processor blade is configured to process data provided by the switch. For example, the electronic processor of the processor blade is configured to send processed data to the switch, which switches the processed data with other data, e.g., data from other processor blades.
In the examples shown in
For example, the electronic processor can be a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application specific integrated circuit (ASIC). For example, the electronic processor can be a memory device or a storage device. In this context, processing of data includes writing data to, or reading data from, the memory or storage device, and optionally performing error correction. The memory device can be, e.g., random access memory (RAM), which can include, e.g., dynamic RAM (DRAM) or static RAM (SRAM). The storage device can include, e.g., solid state memory or drive, which can include, e.g., one or more non-volatile memory (NVM) Express® (NVMe) SSD (solid state drive) modules, or Intel® Optane™ persistent memory.
The co-packaged optical module (or optical interconnect module) 12316 can be similar to, e.g., the integrated optical communication device 262 of
In some implementations, each co-packaged optical module can receive optical signals from a large number of fiber cores, and each co-packaged optical module can be optically coupled to external fiber optic cables through three or more array connectors that occupy an overall area at the front panel that is larger than the overall area occupied by the co-packaged optical module on the printed circuit board.
In the examples shown in
In the examples shown in
Referring to
For example, each integrated circuit 16710 (mounted on the photonic integrated circuit 16704) can include an electrical drive amplifier or a transimpedance amplifier. Each integrated circuits 16712 (mounted on the substrate) can include a SerDes or a DSP chip or a combination of SerDes/DSP chips.
Furthermore, the conductive traces between the electrical integrated circuits 16710 and active components in the photonic integrated circuit 16704 can be made shorter, resulting in better performance, e.g., higher data rate, higher signal-to-noise ratio, and lower power required to transmit the signals, as compared to a configuration in which the electrical signals have to travel longer distances.
There are several ways to package the electrical integrated circuits and the photonic integrated circuit in order to achieve a compact, small-size, and energy efficient co-packaged optical module.
In some implementations, an integrated circuit is configured to surround or partially surround the vertical fiber connector. For example, the integrated circuit can have an L-shape that surrounds two sides of the vertical fiber connector (e.g., two of north, east, south, and west sides). For example, the integrated circuit can have a U-shape that surrounds three sides of the vertical fiber connector (e.g., three of north, east, south, and west sides). For example, the integrated circuit can have an opening in the center region to allow the vertical fiber connector to pass through, in which the integrated circuit completely surrounds the vertical fiber connector. The dimensions of the opening in the integrated circuit are selected to allow the optical fiber connector to pass through to enable an optical fiber to be optically coupled to the photonic integrated circuit. For example, the integrated circuit with an opening in the center region can have a circular or polygonal shape at the outer perimeter. A feature of the integrated circuit mounted on the same surface as the vertical fiber connector is that it takes advantage of the space available on the surface of the photonic integrated circuit that is not occupied by the vertical fiber connector so that the electrical integrated circuit can be placed near or adjacent to the active components (e.g., photodetectors and/or modulators) of the photonic integrated circuit.
In some implementations, an integrated circuit defining an opening can be manufactured by the following process:
Step 1: Use semiconductor lithography to form an integrated circuit on a semiconductor die (or wafer or substrate), in which a first interior region of the semiconductor die does not have integrated circuit component intended to be used for the final integrated circuit (but can have components intended to be used for other products).
Step 2: Use a laser (or any other suitable cutting tool) to cut an opening in the first interior region of the semiconductor die.
Step 3: Place the semiconductor die on a lower mold resin that defines an opening in an interior region. A lead frame or electrical connectors are attached to the lower mold resin.
Step 4: Wire bond electrical contacts on the semiconductor die to the lead frame or electrical connectors attached to the lower mold resin.
Step 5: Attach an upper mold resin to the lower mold resin, and enclose the semiconductor die between the lower and upper mold resins. The upper mold resin defines an opening in an interior region that corresponds to the opening in the lower mold resin. In some examples, the footprint of the semiconductor die is within the footprint of the lower/upper mold resins so that the semiconductor die is completely enclosed inside the lower and upper mold resins. In some examples, the lower and/or upper mold resin can have additional openings, and the opening(s) in the lower and/or upper mold resins can be configured to expose one or more portions of the semiconductor die.
An integrated circuit having an L-shape or a U-shape can be manufactured using a similar process. For example, in step 1, circuitry is formed in an L-shaped or U-shaped footprint. In step 2, the laser or cutting tool cuts the die according to the L-shape or U-shape footprint. In steps 3 and 5, a lower mold resin and an upper mold resin having the desired L-shape or U-shape are used.
Referring to
Semiconductor manufacturing technologies and microprocessor designs improve year after year, enabling the wafer-scale processor to process ever increasing amounts of data. There is a need to improve the mechanism for transmitting the large amounts of data to and from the data processors 17202 in the wafer-scale processor 17200. In some examples, electrical input/output interfaces are positioned at the four edges 17204a, 17204b, 17204c, and 17204d of the wafer-scale processor 17200. In some examples, the electrical input/output interfaces at each edge can provide a bandwidth of several terabytes per second, with an aggregate bandwidth of tens of terabytes per second on all four edges 17204a, 17204b, 17204c, and 17204d. The following describes a technology for using optical interfaces to further increase the input/output bandwidth of the wafer-scale processor 17200.
Referring to
In some examples, the wafer-scale processor can have data processors arranged in a substantially triangular shape and have three edges, and three edge interface modules are provided near the three edges of the wafer-scale processor. In some examples, the wafer-scale processor can have data processors arranged in a shape similar to a pentagon and have five edges, and five edge interface modules are provided near the five edges of the wafer-scale processor. In some examples, the wafer-scale processor can have data processors arranged in a shape similar to a hexagon and have six edges, and six edge interface modules are provided near the six edges of the wafer-scale processor. In some examples, the wafer-scale processor can have data processors arranged in a shape similar to an N1-polygon having N1 edges, N1 being a positive integer greater than 6, and N1 edge interface modules are provided near the N1 edges of the wafer-scale processor. In some examples, the wafer-scale processor can have N1 edges, and M1 edge interface modules are provided near M1 of the N1 edges of the wafer-scale processor, in which M1<N1.
In some examples, the wafer-scale processor has one or more curved edges, and the edge interface modules also have one or more curved edges that match those of the wafer-scale processor. In some examples, the wafer-scale processor has a substantially circular outer edge, and the edge interface module forms a ring that surrounds the wafer-scale processor.
Each edge interface module (e.g., 17302a, 17302b, 17302c, or 17302d) includes a plurality of optical input/output (I/O) interfaces 17304. In some examples, the plurality of optical I/O interfaces 17304 include a two-dimensional arrangement of optical I/O interfaces 17304. In some examples, the two-dimensional arrangement of optical I/O interfaces 17304 includes a two-dimensional array of optical I/O interfaces 17304. In some examples, the two-dimensional array of optical I/O interfaces 17304 includes a plurality of rows and a plurality of columns of optical I/O interfaces 17304. The two-dimensional arrangement does not necessarily have to be a two-dimensional rectilinear arrangement of rows and columns. For example, a two-dimensional arrangement of optical I/O interfaces can include optical I/O interfaces arranged at arbitrary positions on a two-dimensional plane. In some implementations, each optical I/O interface 17304 includes a co-packaged optical module (CPO). For example, the CPO module 17304 can be, or be similar to, any CPO module, integrated optical communication device, or optical module previously described, such as the integrated optical communication device 210 (
For example, each co-packaged optical module includes a photonic integrated circuit that converts optical signals received from one or more optical fibers to electrical signals that are transmitted to one or more data processors 17202, and converts electrical signals received from one or more data processors 17202 to optical signals that are transmitted to one or more optical fibers. In the following, as an example, the optical I/O interface 17304 is described as a co-packaged optical module 17304. It is understood that the optical I/O interface 17304 can include other types of optical interfaces.
In some implementations, the edge interface module 17302 includes a substrate 17308, and the CPO modules 17304 are attached to the substrate 17308 using any of the techniques previously described for attaching a CPO module to a substrate or circuit board. The CPO module can be removably attached to the substrate or circuit board (e.g., by use of compression interposers), or permanently attached to the substrate or circuit board (e.g., by use of solder).
In the following, various examples of the wafer-scale processing systems will be provided. Examples of various parameters of the wafer-scale processing system will be described, such as the rough dimensions of the data processors, the rough dimensions of the edges of the wafer-scale processors, the number of rows of CPO modules included in an edge interface module, the number of CPO modules included in each row, the bandwidth supported by each CPO module, the bandwidth supported by one or more rows of CPO modules, the aggregate bandwidth supported by the edge interface module, the approximate number of bump contacts, the approximate distance between adjacent bump contacts, the approximate distance between adjacent signal lines, etc. It is understood that the values described in this document are merely examples, the invention is not limited to the parameter values described in this document.
In the example of
Referring to
In the example of
For example, the staggered array of photonic integrated circuits includes a first row, a second row, and a third row. In the first row, the photonic integrated circuits are positioned at (x, y) coordinates (1, 1), (3, 1), (5, 1), . . . , (n1, 1), n1 being an odd number. In the second row, the photonic integrated circuits are positioned at (x, y) coordinates (2, 2), (4, 2), (6, 2), . . . , (n2, 2), n2 being an even number. In the third row, the photonic integrated circuits are positioned at (x, y) coordinates (1, 3), (3, 3), (5, 3), . . . , (n3, 3), n3 being an odd number. The staggered array of photonic integrated circuits can include additional rows, and the photonic integrated circuits can be positioned in the additional rows in a similar manner.
Referring to
In some implementations, the bump contacts 17506 form a two-dimensional arrangement of bump contacts 17506. For example, the two-dimensional arrangement of bump contacts 17506 include a two-dimensional array of bump contacts 17506. For example, the two-dimensional array of bump contacts 17506 includes a plurality of rows and a plurality of columns of bump contacts 17506. An inset diagram 17500 shows an enlarged view of a portion 17502 near the edge of the substrate 17308 and the edge of the semiconductor wafer 17203.
In this example, the edge interface module 17302d supports about 150 Tbps bandwidth to the data processors 17202. For example, about 150 Tbps corresponds to about 1500×100 Gbps, which corresponds to about 6000 lanes (1500×2×2, differential, full-duplex). In some embodiments, ground bumps can be used, which can increase the number of lanes and can consequently reduce the line-to-line spacing. Four example layouts for differential signal bumps and ground bumps with ground bump overheads of 50% and 100%, respectively, are shown in
In the example of
When high frequency signals (e.g., having a frequency in the gigahertz range) propagate on metal signal lines formed on the semiconductor substrate 17203, the signal degradation can be significant, e.g., about 0.5 dB per mm at 28 GHz. By keeping the lengths of the signal lines 17504 short, the signal loss can be managed within an acceptable range.
The degradation of signals propagating on metal signal lines formed on the ceramic or high-density build-up substrate 17308 can be lower than the signal degradation on metal signal lines formed on the semiconductor wafer 17203. In some implementations, a longer signal line on the wafer 17203 is paired with a shorter signal line on the substrate 17308, and a shorter signal line on the wafer 17203 is paired with a longer signal line on the substrate 17308. For example, the bump contact 17506a is connected to the data processor 17202 with a relatively longer signal line on the wafer 17203, so the bump contact 17506a is electrically coupled to a CPO module 17304 that is positioned closer to the bump contact 17506a. For example, the bump contact 17506b is connected to the data processor 17202 with a relatively shorter signal line on the wafer 17203, so the bump contact 17506b is electrically coupled to a CPO module 17304 that is positioned farther away from the bump contact 17506a. This design allows the maximum signal loss from the CPO module 17304 to the data processors 17202 to be reduced, as compared to another design that connects the bump contact 17506a to a farthest CPO module 17304.
The CPO modules 17304 can be arranged on the substrate 17308 in a number of ways. Referring to
Referring to
A first set of one or more integrated circuits 17906 are mounted on the top side of the photonic integrated circuit 17902 using, e.g., copper pillars, or solder bumps. The first set of one or more integrated circuits 17906 are positioned adjacent to or near the optical connector 17904. For example, on each photonic integrated circuit 17902, two or more electrical integrated circuits 17906 can be positioned on two or more sides of the optical connector 17904, surrounding or partially surrounding the optical connector 17904. A second set of integrated circuits 17908 are mounted on the substrate 17308 and electrically coupled to the photonic integrated circuit 17902. For example, four integrated circuits 17910a, 17910b, 17910c, 17910d (collectively referenced as 17910) are disposed next to four photonic integrated circuits 17912a, 17912b, 17912c, 17912d (collectively referenced as 17912). For example, the integrated circuit 17910a can process signals transmitted to and/or from the photonic integrated circuit 17912d, the integrated circuit 17910b can process signals transmitted to and/or from the photonic integrated circuit 17912a, the integrated circuit 17910c can process signals transmitted to and/or from the photonic integrated circuit 17912c, and the integrated circuit 17910d can process signals transmitted to and/or from the photonic integrated circuit 17912b.
In some implementations, two or more of the integrated circuits 17910a, 17910b, 17910c, 17910d can be formed as a single integrated circuit that processes signals to/from two or more adjacent photonic integrated circuits 17912.
In some implementations, one or more of the first set of integrated circuits 17906 can include one or more photonic integrated circuits that include both electronic circuitry and optical or optoelectronic components. Similarly, one or more of the second set of integrated circuits 17908 can include one or more photonic integrated circuits that include both electronic circuitry and optical or optoelectronic components. In some embodiments, one or more of photonic integrated circuits 17902 also include integrated electronic circuitry.
Referring to
In some implementations, the data processors 17202 in the wafer-scale processor 17200 all have similar configuration and have similar data processing capabilities. In some implementations, the wafer-scale processor includes multiple groups of data processors in which the data processors in different groups having different processing capabilities and different requirements. For example, a first group of data processors can operate at a higher clock frequency and have a higher power consumption, and a second group of data processors can operate at a lower clock frequency and consumes less power. For example, a first group of data processors can be configured with SerDes having less equalization capabilities (sufficient to only bridge the relatively short processor-to-processor links), while a second group of data processors can be configured with SerDes having stronger equalization capabilities (to be able to bridge the relatively longer processor-to-interface module links). The first group of data processors can be positioned near a first set of one or more edges, and the second group of data processors can be positioned near a second set of one or more edges. For example, the edge interface module or modules 17302 that service the first group of data processors can be configured to support a higher bandwidth, and the edge interface module or modules 17302 that service the second group of data processors can be configured to support a lower bandwidth.
For example, a first group of data processors can be configured to process signals encoded according to a first protocol, and a second group of data processors can be configured to process signals encoded according to a second protocol. The first group of data processors can be positioned near a first set of one or more edges, and the second group of data processors can be positioned near a second set of one or more edges. For example, the edge interface module or modules 17302 that service the first group of data processors can be configured to process signals encoded according to the first protocol, and the edge interface module or modules 17302 that service the second group of data processors can be configured to process signals encoded according to the second protocol.
Referring to
Referring to
Referring to
Referring to
In some implementations, the edge interface module 17804d supports about 140 Tbps bandwidth, in which 5447 radio frequency signal traces (differential, full-duplex) are used to transmit the signals between the CPO modules in the edge interface module 17804d and the data processors 17806. The number of lanes can depend on the number of ground traces and ground bumps, and/or the width of the strip that is used.
Referring to
In some implementations, a longer signal line on the semiconductor wafer 17203 is paired with a shorter signal line on the substrate 17308, and a shorter signal line on the semiconductor wafer 17203 is paired with a longer signal line on the substrate 17308. This reduces the maximum signal propagation loss for the signals transmitted between the CPO modules of the edge interface module 17804d and the data processors 17806.
Referring to
Referring to
Referring to
In some implementations, the photonic integrated circuits (e.g., 17902) can monolithically include driver and TIA electronics, or the driver and TIA electronics can be included in a separate chip. The driver and TIA electronics can directly interface with the data processors (e.g., 17806), referred to as a “direct drive” configuration. For example, the electrical signals output from the driver/TIA electronics associated with the photonic integrated circuits are sent directly to the data processors, and the electrical signals output from the data processors are sent directly to the driver/TIA electronics associated with the photonic integrated circuits.
In some implementations, one or more interface circuits are provided between the photonic integrated circuits and the data processors in order to convert or condition the electrical signals transmitted between the photonic integrated circuits and the data processors. The interface circuits can be, e.g., converters or retimer chips, and can be configured to, e.g., regenerate data, retime data, and/or maintain signal integrity. In some examples, the interface circuits can be positioned on surfaces of the photonic integrated circuits, similar to the integrated circuits 17906 (
In some implementations, the photonic integrated circuits output serial electrical signals, and the interface circuits convert the serial electrical signals to parallel electrical signals that are transmitted to the data processors. In some implementations, the photonic integrated circuits output parallel electrical signals, and the interface circuits convert the parallel electrical signals to serial electrical signals that are transmitted to the data processors. In some implementations, the data processors output serial electrical signals, and the interface circuits convert the serial electrical signals to parallel electrical signals that are transmitted to the photonic integrated circuits. In some implementations, the data processors output parallel electrical signals, and the interface circuits convert the parallel electrical signals to serial electrical signals that are transmitted to the photonic integrated circuits. In some implementations, a combination of the configurations described above are used.
The following describes various configurations of interfaces between a photonic integrated circuit and a data processor. It is understood that a single photonic integrated circuit can communicate with one or more data processors, and a single data processor can communicate with one or more photonic integrated circuits. It is understood that an interface circuit can communicate with one or more photonic integrated circuits and one or more data processors. It is understood that a wafer-scale processor can use any combination of the interface circuit configurations described here. In some implementations, the input/output interface of the photonic integrated circuit includes an XLR (extra long reach) SerDes (serializers/deserializers), an LR (long reach) SerDes, an MR (medium reach) SerDes, an XSR (extra short reach) SerDes, or a BoW (bunch of wire) input/output interface. In some implementations, the input/output interface of the data processor includes an XLR SerDes, an LR SerDes, an MR SerDes, an XSR SerDes, or a BoW input/output interface. An interface circuit in the form of a converter or retimer is provided between the photonic integrated circuit and the data processor. The converter or retimer can be, e.g., an XLR-to-XLR retimer, an LR-to-LR retimer, an MR-to-MR retimer, an SR-to-SR retimer, a BoW-to-BoW retimer, an XLR-to-LR converter, an XLR-to-MR converter, an XLR-to-SR converter, an XLR-to-XSR converter, an LR-to-MR converter, an LR-to-SR converter, an LR-to-XSR converter, an MR-to-SR converter, an MR-to-XSR converter, an SR-to-XSR converter, an XLR-to-BoW converter, an LR-to-BoW converter, an MR-to-BoW converter, or an XSR-to-BoW converter.
In the edge interface module described above, e.g., 17302 of
Referring to
Referring to
In this example, the wafer-scale processor 19202 includes four edges, and four edge interface modules 19204 are provided near the four edges of the wafer-scale processor 19202. Each edge interface module 19204 includes a plurality of optical input/output (I/O) interfaces 19208, which can be similar to the optical input/output interfaces 17304 of
In some implementations, each edge interface module 19204 supports about 150 Tbps bandwidth to the corresponding edge of the wafer-scale data processor 19202. Each edge interface module 19204 can provide up to about 150 Tbps data throughput to the corresponding edge. The four edge interface modules 19204 at the four edges support an aggregate bandwidth of about 600 Tbps to the wafer-scale processor 19202. The four edge interface modules can provide up to about 600 Tbps data throughput to the wafer-scale processor 19202.
Referring to
In this example, the wafer-scale processor 19302 includes four edges, and four edge interface modules 19304 are provided near the four edges of the wafer-scale processor 19302. Each edge interface module 19304 includes a plurality of optical input/output (I/O) interfaces 19308, which can be similar to the optical input/output interfaces 17304 of
In some implementations, each edge interface module 19304 includes 5 edge interface sub-modules 19310 (also referred to as “tiles”), similar to the example shown in
Referring to
In some implementations, an integrated heat dissipating device or cooling device can be provided for the data processors (e.g., 17202 of
Referring to
Referring to
One or more co-packaged optical modules 19812 are positioned between the data processors 19806, and one or more co-packaged optical modules 19814 are positioned between the data processors 19808. The co-packaged optical modules 19812 communicate with the co-packaged optical modules 19814 through one or more optical fibers 19816. The co-packaged optical modules 19812 and 19814, and the one or more optical fibers 19816 provide one or more optical communication links between the wafer-scale processing module 19802 and the wafer-scale processing module 19804. In this example, the shared power supply and/or shared cooling device 19810 include one or more openings to allow the one or more optical fibers 19816 to pass through.
Referring to
The first wafer scale processing module 19902 includes a plurality of co-packaged optical modules, e.g., 19912, 19914, positioned near one or more edges of the wafer scale processing module 19902. The second wafer scale processing module 19904 includes a plurality of co-packaged optical modules, e.g., 19916, 19918, positioned near one or more edges of the wafer scale processing module 19904. One or more of the co-packaged optical modules 19912 of the first wafer scale processing module 19902 and one or more of the co-packaged optical modules 19916 of the second wafer scale processing module 19904 are optically connected through one or more optical fibers 19920. At least some of the co-packaged optical modules 19914 of the first wafer scale processing module 19902 and at least some of the co-packaged optical modules 19918 of the second wafer scale processing module 19904 are connected to optical fibers 19922 that connect to external devices, such as switches, general-purpose processors, and/or storage devices.
Referring to
The first wafer scale processing module 20002 is “flipped over” such that the data processors of the first wafer scale processing module 20002 face the data processors of the second wafer scale processing module 20004. A shared power supply and/or cooling device 20026 is positioned between the data processors of the first wafer scale processing module 20002 and the data processors of the second wafer scale processing module 20004. The third wafer scale processing module 20006 is “flipped over” such that the data processors of the third wafer scale processing module 20006 face the data processors of the fourth wafer scale processing module 20008. A shared power supply and/or cooling device 20028 is positioned between the data processors of the third wafer scale processing module 20006 and the data processors of the fourth wafer scale processing module 20008.
In some implementations, the first and second wafer scale processing modules 20002 and 20004 are optically linked through one or more co-packaged optical modules 20010 on the first wafer scale processing module 20002, one or more co-packaged optical modules 20012 on the second wafer scale processing module 20004, and one or more optical fibers 20014 connected between the one or more co-packaged optical modules 20010 and the one or more co-packaged optical modules 20012, similar to the example shown in
For example, the third and fourth wafer scale processing modules 20006 and 20008 are optically linked through one or more co-packaged optical modules 20016 on the third wafer scale processing module 20006, one or more co-packaged optical modules 20018 on the fourth wafer scale processing module 20008, and one or more optical fibers 20020 connected between the one or more co-packaged optical modules 20016 and the one or more co-packaged optical modules 20018.
In some implementations, the second wafer scale processing module 20004 and the third wafer scale processing module 20006 are positioned back-to-back such that the back side of the carrier wafer or substrate 20022 of the second wafer scale processing module 20004 faces the back side of the carrier wafer or substrate 20024 of the third wafer scale processing module 20006. For example, the second and third wafer scale processing modules 20004 and 20006 are optically linked through one or more co-packaged optical modules 20032 on the second wafer scale processing module 20004, one or more co-packaged optical modules 20034 on the third wafer scale processing module 20006, and one or more optical fibers 20036 connected between the one or more co-packaged optical modules 20032 and the one or more co-packaged optical modules 20034.
A shared power supply and/or cooling device 20030 is positioned between the carrier wafer or substrate 20022 of the second wafer scale processing module 20004 and the carrier wafer or substrate 20024 of the third wafer scale processing module 20006. The shared power supply provides power to the data processors of the second and third wafer scale processing modules 20004, 20006, e.g., through electrical conduction lines that pass through the carrier wafer or substrate 20022 and 20024. The shared cooling device removes heat generated by the data processors of the second and third wafer scale processing modules 20004, 20006, e.g., through thermal conduction paths that pass through the carrier wafer or substrate 20022 and 20024.
In some implementations, the first wafer scale processing module 20002 and the third wafer scale processing module 20006 are optically linked through one or more co-packaged optical modules of the first wafer scale processing module 20002, one or more co-packaged optical modules of the third wafer scale processing module 20006, and one or more optical fibers connected between the one or more co-packaged optical modules of the first wafer scale processing module 20002 and the one or more co-packaged optical modules of the third wafer scale processing module 20006.
In some implementations, the first wafer scale processing module 20002 and the fourth wafer scale processing module 20008 are optically linked through one or more co-packaged optical modules of the first wafer scale processing module 20002, one or more co-packaged optical modules of the fourth wafer scale processing module 20008, and one or more optical fibers connected between the one or more co-packaged optical modules of the first wafer scale processing module 20002 and the one or more co-packaged optical modules of the fourth wafer scale processing module 20008.
In some implementations, the second wafer scale processing module 20004 and the fourth wafer scale processing module 20008 are optically linked through one or more co-packaged optical modules of the second wafer scale processing module 20004, one or more co-packaged optical modules of the fourth wafer scale processing module 20008, and one or more optical fibers connected between the one or more co-packaged optical modules of the second wafer scale processing module 20004 and the one or more co-packaged optical modules of the fourth wafer scale processing module 20008.
In some implementations, some of the co-packaged optical modules 20038 of the first wafer scale processing module 20002 are connected to optical fibers 20040 that connect to external devices, such as switches, general-purpose processors, and/or storage devices. Some of the co-packaged optical modules 20042 of the fourth wafer scale processing module 20008 are connected to optical fibers 20044 that connect to external devices, such as switches, general-purpose processors, and/or storage devices.
In some implementations, some of the co-packaged optical modules of the second wafer scale processing module 20004 are connected to optical fibers that connect to external devices. Some of the co-packaged optical modules of the third wafer scale processing module 20006 are connected to optical fibers that connect to external devices.
In some implementations, the second and/or third wafer scale processing modules 20004, 20006 includes edge interface modules that have co-packaged optical modules mounted to both sides of the carrier wafer or substrate, similar to the example shown in
In the example of
In some implementations, a large scale multi-wafer processing system includes multiple multi-wafer processing modules that are arranged in a two-dimensional array, in which each multi-wafer processing module includes multiple wafer-scale processing modules vertically stacked together. For example, a large scale multi-wafer processing system can include 36 wafer-scale processing modules that are arranged in a 3-by-3 array of multi-wafer processing modules, in which each multi-wafer processing module includes 4 wafer-scale processing modules vertically stacked together. Optical communicate links can be provided between wafer-scale processing modules that are adjacent to each other horizontally, or between wafer-scale processing modules that are adjacent to each other vertically. Optically communication links can also be provided between wafer-scale processing modules that are not adjacent to each other.
In the examples described above, the circuit boards and/or the substrates can be replaced with, or used in combination with, silicon interposers, embedded interposers, and/or glass interposers. For example, the photonic integrated circuits and the electronic integrated circuits of co-packaged optical modules can be mounted on silicon interposers, which in turn can be mounted on other wafers, substrates, or circuit boards.
In this document, when we say that the photonic integrated circuit receives first optical signals and generates first electrical signals based on the first optical signals, and the data processor receives the first electrical signals, it is understood that the data processor can receive the first electrical signals directly (in a direct drive configuration) or through an interface circuit (e.g., an XSR-to-LR or XSR-to-MR converter/retimer, or any other type of converter/retimer described above). The first electrical signals received by the data processor do not necessary have the same format as the first electrical signals generated by the photonic integrated circuit, and the interface circuit performs translation, retiming, or conditioning between the different formats of electrical signals.
While this disclosure includes references to illustrative embodiments, this specification is not intended to be construed in a limiting sense. Various modifications of the described embodiments, as well as other embodiments within the scope of the disclosure, which are apparent to persons skilled in the art to which the disclosure pertains are deemed to lie within the principle and scope of the disclosure, e.g., as expressed in the following claims.
For example, the techniques described above for improving the operations of systems that include rackmount servers can also be applied to systems that include blade servers.
Some embodiments can be implemented as circuit-based processes, including possible implementation on a single integrated circuit.
Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value or range.
It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this disclosure can be made by those skilled in the art without departing from the scope of the disclosure, e.g., as expressed in the following claims.
The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.
Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the disclosure. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.”
Unless otherwise specified herein, the use of the ordinal adjectives “first,” “second,” “third,” etc., to refer to an object of a plurality of like objects merely indicates that different instances of such like objects are being referred to, and is not intended to imply that the like objects so referred-to have to be in a corresponding order or sequence, either temporally, spatially, in ranking, or in any other manner.
Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements.
As used herein in reference to an element and a standard, the term compatible means that the element communicates with other elements in a manner wholly or partially specified by the standard, and would be recognized by other elements as sufficiently capable of communicating with the other elements in the manner specified by the standard. The compatible element does not need to operate internally in a manner specified by the standard.
The described embodiments are to be considered in all respects as only illustrative and not restrictive. In particular, the scope of the disclosure is indicated by the appended claims rather than by the description and figures herein. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
The description and drawings merely illustrate the principles of the disclosure. It will thus be appreciated that those of ordinary skill in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.
The functions of the various elements shown in the figures, including any functional blocks labeled or referred to as “processors” and/or “controllers,” can be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions can be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which can be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and can implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and/or custom, can also be included. Similarly, any switches shown in the figures are conceptual only. Their function can be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.
As used in this application, the term “circuitry” can refer to one or more or all of the following: (a) hardware-only circuit implementations (such as implementations in only analog and/or digital circuitry); (b) combinations of hardware circuits and software, such as (as applicable): (i) a combination of analog and/or digital hardware circuit(s) with software/firmware and (ii) any portions of hardware processor(s) with software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions); and (c) hardware circuit(s) and or processor(s), such as a microprocessor(s) or a portion of a microprocessor(s), that requires software (e.g., firmware) for operation, but the software does not need to be present when it is not needed for operation.” This definition of circuitry applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term circuitry also covers an implementation of merely a hardware circuit or processor (or multiple processors) or portion of a hardware circuit or processor and its (or their) accompanying software and/or firmware. The term circuitry also covers, for example and if applicable to the particular claim element, a baseband integrated circuit or processor integrated circuit for a mobile device or a similar integrated circuit in server, a cellular network device, or other computing or network device.
It should be appreciated by those of ordinary skill in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure.
Although the present invention is defined in the attached claims, it should be understood that the present invention can also be defined in accordance with the following embodiments:
Embodiment 1: A system comprising:
Embodiment 2: The system of embodiment 1 in which the first optical input/output module comprises a plurality of photonic integrated circuits arranged in a two-dimensional array comprising at least two rows and at least two columns of photonic integrated circuits.
Embodiment 3: The system of embodiment 1 or 2 in which the first optical input/output module comprises:
Embodiment 4: The system of embodiment 3 in which each set of first electronic integrated circuits comprises two electronic integrated circuits that are positioned on opposite sides of the optical connector along a plane parallel to the first surface of the associated photonic integrated circuit.
Embodiment 5: The system of embodiment 3 in which each set of first electronic integrated circuits comprises three electronic integrated circuits that surround three sides of the optical connector along a plane parallel to the first surface of the photonic integrated circuit.
Embodiment 6: The system of embodiment 3 in which each set of first electronic integrated circuits comprises four electronic integrated circuits that surround four sides of the optical connector along a plane parallel to the first surface of the photonic integrated circuit.
Embodiment 7: The system of any of embodiments 3 to 6 in which each set of first electronic integrated circuits comprises at least one of an electrical drive amplifier or a transimpedance amplifier.
Embodiment 8: The system of any of embodiments 1 to 7 in which the first optical input/output module comprises:
Embodiment 9: The system of embodiment 8 in which each set of second electronic integrated circuits comprises three electronic integrated circuits that surround three sides of the photonic integrated circuit along a plane parallel to a first surface of the substrate.
Embodiment 10: The system of embodiment 8 in which each set of second electronic integrated circuits comprises four electronic integrated circuits that surround four sides of the photonic integrated circuit along a plane parallel to a first surface of the substrate.
Embodiment 11: The system of any of embodiments 8 to 10 in which each set of second electronic integrated circuits comprises a serializers/deserializers module.
Embodiment 12: The system of any of embodiments 1 to 11 in which each of at least some of the photonic integrated circuits comprises an array of grating couplers, a plurality of optical waveguides coupled to the array of grating couplers, and a plurality of photodetectors coupled to the plurality of optical waveguides.
Embodiment 13: The system of any of embodiments 1 to 12 in which each of the at least one data processor comprises at least one of a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, an application specific integrated circuit (ASIC), or a data storage device.
Embodiment 14: The system of any of embodiments 1 to 13, comprising a wafer-scale processing module comprising a plurality of data processors, in which the first optical input/output module is configured to receive a plurality of first optical signals through at least some of a plurality of optical links, generate a plurality of first electrical signals based on the plurality of first optical signals, and transmit the plurality of first electrical signals to the data processors directly or through the interface circuit.
Embodiment 15: The system of embodiment 14 in which the plurality of data processors are configured to generate a plurality of second electrical signals that are transmitted to the first optical input/output modules directly or through the interface circuit, the first optical input/output module is configured to generate a plurality of second optical signals based on the plurality of second electrical signals, and output the plurality of optical signals through at least some of the plurality of optical links.
Embodiment 16: The system of embodiment 14 or 15 in which the wafer-scale processing module comprises a wafer and a two-dimensional arrangement of at least three data processors formed on the wafer.
Embodiment 17: The system of embodiment 16 in which the two-dimensional arrangement of at least three data processors comprises an array of at least two rows and at least two columns of data processors.
Embodiment 18: The system of embodiment 17 in which the array of data processors comprise at least three rows and at least three columns of data processors.
Embodiment 19: The system of embodiment 18 in which the array of data processors comprise at least four rows and at least four columns of data processors.
Embodiment 20: The system of any of embodiments 14 to 19 in which the first optical input/output module comprises at least four photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
Embodiment 21: The system of embodiment 20 in which the first optical input/output module comprises at least eight photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
Embodiment 22: The system of embodiment 21 in which the first optical input/output module comprises at least sixteen photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
Embodiment 23: The system of embodiment 22 in which the first optical input/output module comprises at least thirty-two photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
Embodiment 24: The system of embodiment 23 in which the first optical input/output module comprises at least sixty-four photonic integrated circuits that are configured to transmit electrical signals to and receive electrical signals from the wafer-scale processing module.
Embodiment 25: The system of any of embodiments 14 to 24 in which each of more than half of the photonic integrated circuits in the first optical input/output module has electronic integrated circuits arranged at four sides of the photonic integrated circuit.
Embodiment 26: The system of embodiment 25 in which each of more than 80% of the photonic integrated circuits in the first optical input/output module has electronic integrated circuits arranged at four sides of the photonic integrated circuit.
Embodiment 27: The system of any of embodiments 1 to 26 in which the plurality of photonic integrated circuits are arranged in a staggered array configuration.
Embodiment 28: The system of embodiment 27 in which the plurality of photonic integrated circuits comprises a staggered array of photonic integrated circuits,
Embodiment 29: The system of any of embodiments 14 to 28 in which the wafer-scale processing module has a first edge and a second edge, the first optical input/output module is positioned in a vicinity of the first edge,
Embodiment 30: The system of embodiment 29 in which the wafer-scale processing module has a third edge,
Embodiment 31: The system of embodiment 30 in which the wafer-scale processing module has a fourth edge,
Embodiment 32: The system of any of embodiments 29 to 31 in which the first optical input/output module is configured to support at least 50 Tbps data throughput to the first edge of the wafer-scale processing module.
Embodiment 33: The system of any of embodiments 29 to 32 in which the second optical input/output module is configured to support at least 50 Tbps data throughput to the second edge of the wafer-scale processing module.
Embodiment 34: The system of any of embodiments 30 to 33 in which the third optical input/output module is configured to support at least 50 Tbps data throughput to the third edge of the wafer-scale processing module.
Embodiment 35: The system of any of embodiments 31 to 34 in which the fourth optical input/output module is configured to support at least 50 Tbps data throughput to the fourth edge of the wafer-scale processing module.
Embodiment 36: The system of embodiment 35 in which the first, second, third, and fourth optical input/output modules are configured to support an aggregate data throughput of at least 200 Tbps to the wafer-scale processing module.
Embodiment 37: The system of any of embodiments 8 to 36 in which each of some of the second electronic integrated circuits is electrically interconnected to two or more photonic integrated circuits.
Embodiment 38: The system of embodiment 37 in which each of some of the second electronic integrated circuits comprises a serializers/deserializers module that is configured to condition the electrical signals transmitted to or from two or more photonic integrated circuits.
Embodiment 39: The system of any of embodiments 14 to 38 in which the first optical input/output module comprises two rows of photonic integrated circuits that support an aggregate data throughput of approximately 59.1 Tbps.
Embodiment 40: The system of embodiment 39 in which the wafer-scale processing module has a first edge, the first optical input/output module is positioned in a vicinity of the first edge, and the first optical input/output module is configured to support an aggregate data throughput per unit edge length of approximately 288 Gbps/mm.
Embodiment 41: The system of any of embodiments 14 to 40 in which the first optical input/output module comprises three rows of photonic integrated circuits that support an aggregate data throughput of approximately 89.6 Tbps.
Embodiment 42: The system of embodiment 41 in which the wafer-scale processing module has a first edge, the first optical input/output module is positioned in a vicinity of the first edge, and the first optical input/output module is configured to support an aggregate data throughput per unit edge length of approximately 437 Gbps/mm.
Embodiment 43: The system of any of embodiments 14 to 42 in which the first optical input/output module comprises four rows of photonic integrated circuits that support an aggregate data throughput of approximately 118.3 Tbps.
Embodiment 44: The system of embodiment 43 in which the wafer-scale processing module has a first edge, the first optical input/output module is positioned in a vicinity of the first edge, and the first optical input/output module is configured to support an aggregate data throughput per unit edge length of approximately 576 Gbps/mm.
Embodiment 45: The system of any of embodiments 14 to 43 in which the first optical input/output module comprises five rows of photonic integrated circuits that support an aggregate data throughput of approximately 148.7 Tbps.
Embodiment 46: The system of embodiment 45 in which the wafer-scale processing module has a first edge, the first optical input/output module is positioned in a vicinity of the first edge, and the first optical input/output module is configured to support an aggregate data throughput per unit edge length of approximately 725 Gbps/mm.
Embodiment 47: The system of any of embodiments 1 to 46 in which the at least one data processor comprises an integrated circuit or a system on a chip (SoC) that includes at least one million transistors.
Embodiment 48: The system of any of embodiments 14 to 47 in which the wafer-scale processing module comprises at least one billion transistors.
Embodiment 49: The system of any of embodiments 1 to 48 in which the first optical input/output module comprises a plurality of co-packaged optical modules, each co-packaged optical module comprises at least one of the photonic integrated circuits.
Embodiment 50: The system of embodiment 49 in which each co-packaged optical module comprises a first optical connector part that is configured to be removably coupled to a second optical connector part that is attached to a first fiber cable that comprises an array of optical fibers.
Embodiment 51: The system of embodiment 50 in which the fiber cable comprises at least 10 cores of optical fibers, and the first optical connector part is configured to couple at least 10 channels of optical signals to the photonic integrated circuit.
Embodiment 52: The system of embodiment 51 in which the fiber cable comprises at least 100 cores of optical fibers, and the first optical connector part is configured to couple at least 100 channels of optical signals to the photonic integrated circuit.
Embodiment 53: The system of embodiment 52 in which the fiber cable comprises at least 500 cores of optical fibers, and the first optical connector part is configured to couple at least 500 channels of optical signals to the photonic integrated circuit.
Embodiment 54: The system of embodiment 53 in which the fiber cable comprises at least 1000 cores of optical fibers, and the first optical connector part is configured to couple at least 1000 channels of optical signals to the photonic integrated circuit.
Embodiment 55: The system of any of embodiments 49 to 54 in which the photonic integrated circuit is configured to generate a plurality of first serial electrical signals based on the received optical signals, in which each first serial electrical signal is generated based on one of the channels of first optical signals;
Embodiment 56: The system of any of embodiments 49 to 54 in which the co-packaged optical module is electrically coupled to a circuit board or a substrate using electrical contacts that comprise at least one of spring-loaded elements, compression interposers, or land-grid arrays.
Embodiment 57: The system of any of embodiments 1 to 56 in which the system comprises a rackmount server, the housing comprises an enclosure for the rackmount server, and the rackmount server has an n rack unit form factor, and n is an integer in a range from 1 to 8.
Embodiment 58: The system of any of embodiments 1 to 57 in which the interface circuit comprises at least one of a converter or retimer, and the converter or retimer comprises at least one of an XLR-to-XLR retimer, an LR-to-LR retimer, an MR-to-MR retimer, an SR-to-SR retimer, a BoW-to-BoW retimer, an XLR-to-LR converter, an XLR-to-MR converter, an XLR-to-SR converter, an XLR-to-XSR converter, an LR-to-MR converter, an LR-to-SR converter, an LR-to-XSR converter, an MR-to-SR converter, an MR-to-XSR converter, an SR-to-XSR converter, an XLR-to-BoW converter, an LR-to-BoW converter, an MR-to-BoW converter, or an XSR-to-BoW converter.
Embodiment 59: A supercomputer that comprises the system of any of embodiments 1 to 58.
Embodiment 60: The system of any of embodiments 14 to 58 in which the wafer-scale processing module comprises an artificial intelligence processor.
Embodiment 61: The system of any of embodiments 14 to 58 in which the system is configured to simulate weather.
Embodiment 62: The system of any of embodiments 14 to 58 in which the system is configured to construct and/or support a metaverse that includes one or more virtual environments and enable users to interact with one another in the one or more virtual environments, or interact with objects in the one or more virtual environments.
Embodiment 63: The system of any of embodiments 14 to 58 in which the system is configured to construct and/or support a simulated environment for training autonomous vehicles.
Embodiment 64: An autonomous vehicle that comprises the system of any of embodiments 1 to 58 and 60, or the supercomputer of embodiment 59.
Embodiment 65: The autonomous vehicle of embodiment 64 in which the vehicle comprises at least one of a car, a truck, a train, a boat, a ship, a submarine, a helicopter, a drone, an airplane, a space rover, or a space ship.
Embodiment 66: A robot that comprises the system of any of embodiments 1 to 58 and 60, or the supercomputer of embodiment 59.
Embodiment 67: The robot of embodiment 66 in which the robot comprises at least one of an industrial robot, a helper robot, a medical surgery robot, a merchandise delivery robot, a teaching robot, a cleaning robot, a cooking robot, a construction robot, or an entertainment robot.
Embodiment 68: A system comprising:
Embodiment 69: The system of embodiment 68 in which the first optical input/output module comprises an edge interface module that is disposed near an edge of the wafer-scale processor, and is configured to transmit electrical signals to and receive electrical signals from data processors positioned near the edge of the wafer-scale processing module.
Embodiment 70: The system of embodiment 68 or 69 in which the first optical input/output module is configured to support at least 50 Tbps data throughput to an edge of the wafer-scale processing module.
Embodiment 71: The system of embodiment 70 in which the first optical input/output module is configured to support at least 100 Tbps data throughput to an edge of the wafer-scale processing module.
Embodiment 72: The system of any of embodiments 68 to 71 in which the wafer-scale processing module comprises a semiconductor wafer, and the data processors are formed on the semiconductor wafer or mounted on the semiconductor wafer, wherein the photonic integrated circuits are mounted on a substrate, wherein electrical contacts on the substrate are electrically coupled to electrical contacts on the semiconductor wafer.
Embodiment 73: The system of any of embodiments 68 to 71 in which the wafer-scale processing module comprises a semiconductor wafer, and the data processors are formed on the semiconductor wafer or mounted on the semiconductor wafer,
Embodiment 74: The system of embodiment 72 or 73 in which the photonic integrated circuits are electrically coupled to the data processors through a first set of signal lines on the substrate and a second set of signal lines on the semiconductor wafer,
Embodiment 75: The system of any of embodiments 68 to 74 in which the first optical input/output module comprises a plurality of co-packaged optical (CPO) modules, each CPO module includes a photonic integrated circuit and an electronic integrated circuit, the electronic integrated circuit includes at least one of (i) an XSR chip, (ii) a driver amplifier, or (iii) a transimpedance amplifier (TIA).
Embodiment 76: The system of any of embodiments 68 to 74 in which the first optical input/output module comprises:
Embodiment 77: The system of any of embodiments 68 to 74 in which the first optical input/output module comprises:
Embodiment 78: The system of embodiment 77 in which each of at least a subset of the co-packaged optical (CPO) modules is surrounded by other CPO modules and does not have any XSR chip between the CPO module and other CPO modules.
Embodiment 79: The system of any of embodiments 68 to 74 in which the first optical input/output module comprises:
Embodiment 80: The system of embodiment 79 in which each photonic integrated circuit is driven directly by a corresponding XSR-to-LR or XSR-to-MR converter without a separate driver amplifier or transimpedance amplifier.
Embodiment 81: The system of any of embodiments 68 to 80 in which the interface circuit comprises at least one of a converter or retimer, and the converter or retimer comprises at least one of an XLR-to-XLR retimer, an LR-to-LR retimer, an MR-to-MR retimer, an SR-to-SR retimer, a BoW-to-BoW retimer, an XLR-to-LR converter, an XLR-to-MR converter, an XLR-to-SR converter, an XLR-to-XSR converter, an LR-to-MR converter, an LR-to-SR converter, an LR-to-XSR converter, an MR-to-SR converter, an MR-to-XSR converter, an SR-to-XSR converter, an XLR-to-BoW converter, an LR-to-BoW converter, an MR-to-BoW converter, or an XSR-to-BoW converter.
Embodiment 82: A method comprising:
Embodiment 83: The method of embodiment 82, comprising using the first optical input/output module to support at least 100 Tbps data throughput to the first edge of the wafer-scale processing module.
Embodiment 84: The method of embodiment 82, comprising using a second optical input/output module to support at least 50 Tbps data throughput to a second edge of the wafer-scale processing module.
Embodiment 85: The method of embodiment 84, comprising using a third optical input/output module to support at least 50 Tbps data throughput to a third edge of the wafer-scale processing module.
Embodiment 86: The method of embodiment 85, comprising using a fourth optical input/output module to support at least 50 Tbps data throughput to a fourth edge of the wafer-scale processing module, in which the first, second, third, and fourth optical input/output modules are configured to support an aggregate data throughput of at least 200 Tbps to the wafer-scale processing module.
Embodiment 87: A system comprising:
Embodiment 88: The system of embodiment 87 in which the first wafer-scale processing module and the second wafer-scale processing module are positioned side-by-side, the first array of data processors and the second array of data processors face a same direction.
Embodiment 89: The system of embodiment 88 in which the first wafer-scale processing module comprises a first substrate, the first array of data processors are coupled to
Embodiment 90: The system of embodiment 89 in which the first substrate comprises a first semiconductor wafer, and the second substrate comprises a second semiconductor wafer.
Embodiment 91: The system of embodiment 89 or 90, comprising a first shared power supply positioned between the first wafer-scale processing module and the second wafer-scale processing module, in which the first shared power supply is configured to provide power to the first array of data processors and the second array of data processors.
Embodiment 92: The system of any of embodiments 89 to 91, comprising a first shared cooling device positioned between the first wafer-scale processing module and the second wafer-scale processing module, in which the first shared cooling device is configured to remove heat from the first array of data processors and the second array of data processors.
Embodiment 93: The system of any of embodiments 89 to 92, comprising a third wafer-scale processing module comprising a third array of data processors and a third optical input/output module, in which the third optical input/output module comprises at least three photonic integrated circuits arranged in a two-dimensional pattern,
Embodiment 94: The system of embodiment 93, comprising a second shared power supply positioned between the second wafer-scale processing module and the third wafer-scale processing module, in which the second shared power supply is configured to provide power to the second array of data processors and the third array of data processors.
Embodiment 95: The system of embodiment 93 or 94, comprising a second shared cooling device positioned between the second wafer-scale processing module and the third wafer-scale processing module, in which the second shared cooling device is configured to remove heat from the second array of data processors and the third array of data processors.
Embodiment 96: The system of any of embodiments 93 to 95, comprising a fourth wafer-scale processing module comprising a fourth array of data processors and a fourth optical input/output module, in which the fourth optical input/output module comprises at least three photonic integrated circuits arranged in a two-dimensional pattern, wherein the first, second, third, and fourth wafer-scale processing modules are vertically stacked together.
Embodiment 97: The system of embodiment 96, comprising a third shared power supply positioned between the third wafer-scale processing module and the fourth wafer-scale processing module, in which the third shared power supply is configured to provide power to the third array of data processors and the fourth array of data processors.
Embodiment 98: The system of embodiment 96 or 97, comprising a third shared cooling device positioned between the third wafer-scale processing module and the fourth wafer-scale processing module, in which the third shared cooling device is configured to remove heat from the third array of data processors and the fourth array of data processors.
Embodiment 99: The system of any of embodiments 96 to 98 in which the second wafer-scale processing module comprises a second substrate, the second array of data processors are coupled to the second substrate, the third wafer-scale processing module comprises a third substrate, the third array of data processors are coupled to the third substrate, and a back side of the second substrate faces a back side of the third substrate.
Embodiment 100: The system of embodiment 99 in which the second shared power supply provides power to the second array of data processors through conductive lines that pass through the second substrate, and the second shared power supply provides power to the third array of data processors through conductive lines that pass through the third substrate.
Embodiment 101: The system of embodiment 99 or 100 in which the second shared cooling device removes heat from the second array of data processors through thermally conductive paths that pass through the second substrate, and the second shared cooling device removes heat from the third array of data processors through thermally conductive paths that pass through the third substrate.
Embodiment 102: A system comprising:
Embodiment 103: The system of embodiment 102 in which each wafer-scale processing module comprises an array of data processors and an optical input/output module, in which a first wafer-scale processing module is optically linked to a second wafer-scale processing module through a first optical input/output module of the first wafer-scale processing module, a second optical input/output module of the second wafer-scale processing module, and an optical fiber cable that connects the first optical input/output module to the second optical input/output module.
Embodiment 104: A system comprising:
Embodiment 105: The system of embodiment 104 in which the at least one data processor comprise a plurality of data processors arranged in a two dimensional pattern, the plurality of data processors comprising three data processors arranged in a pattern forming a triangle.
Embodiment 106: The system of embodiment 104 or 105 in which the at least three photonic integrated circuits comprise N1 photonic integrated circuits, N1 is an integer that is greater than or equal to 3, each photonic integrated circuit comprises at least N2 vertical couplers configured to receive input optical signals from fiber cores, N1 is an integer that is greater than or equal to 3,
Embodiment 107: The system of any of embodiments 104 to 106 in which the at least three photonic integrated circuits comprise at least 10 photonic integrated circuits, and each photonic integrated circuit comprises at least 10 vertical couplers configured to receive input optical signals from corresponding fiber cores,
Embodiment 108: The system of any of embodiments 104 to 107 in which the at least one data processor comprises a wafer-scale processor comprising a plurality of data processors,
Embodiment 109: The system of any of embodiments 104 to 108 in which the wafer-scale processor comprises a plurality of data processors that have a footprint of at least 10 cm×10 cm, each data processor comprises at least one million transistors.
Embodiment 110: The system of embodiment 109 in which the plurality of data processors have a footprint of at least 15 cm×15 cm.
Embodiment 111: The system of embodiment 110 in which the plurality of data processors have a footprint of at least 20 cm×20 cm.
Embodiment 112: The system of any of embodiments 109 to 111 in which the edge processing module is configured to support a communication interface of at least 500 Gbps data throughput between the wafer-scale processor and a plurality of optical fibers.
Embodiment 113: The system of embodiment 112 in which the edge processing module is configured to support a communication interface of at least 1 tetra bps data throughput between the wafer-scale processor and a plurality of optical fibers.
Embodiment 114: The system of embodiment 113 in which the edge processing module is configured to support a communication interface of at least 1.5 tetra bps data throughput between the wafer-scale processor and a plurality of optical fibers.
Embodiment 115: A system comprising:
This application claims priority to U.S. Provisional Application 63/324,429, filed on Mar. 28, 2022. The entire disclosure of the above application is hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63324429 | Mar 2022 | US |
