Claims
- 1. A highly integrated semiconductor memory, comprising:
- an n-channel-EPROM cell in the form of a pillar having side walls and a base;
- an n.sup.+ -doped source region extending along said base of said pillar, and an n.sup.+ -doped drain region disposed on said pillar;
- said pillar having lateral dimensions chosen such that said pillar, in a potential-free state of the n-channel-EPROM cell, is fully depleted of free charge carriers;
- an n.sup.+ -doped floating gate disposed on said side walls of said pillar and enclosing said pillar;
- a control gate formed of p.sup.+ -doped semiconductor material, said control gate enclosing said pillar and said floating gate and being partly disposed on said side walls of said pillar; and
- an intermediate insulator layer between said control gate and said pillar.
- 2. The semiconductor memory according to claim 1, wherein said n-channel-EPROM cell is a silicon-type EPROM cell.
Priority Claims (1)
Number |
Date |
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Kind |
196 00 307 |
Jan 1996 |
DEX |
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CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation of copending international application PCT/DE96/02386, filed on Dec. 11, 1996, which designated the United States.
US Referenced Citations (9)
Foreign Referenced Citations (4)
Number |
Date |
Country |
0 681 333 A1 |
Nov 1995 |
EPX |
195 26 011 C1 |
Nov 1996 |
DEX |
4-155870 |
May 1992 |
JPX |
7-235649 |
Sep 1995 |
JPX |
Non-Patent Literature Citations (2)
Entry |
"Performance of the 3-D Pencil Flash EPROM Cell and Memory Array" (Pein et al.), IEEE Transactions on Electron Devices, vol. 42, No. 11, Nov. 1995, pp. 1982-1991. |
"A 3-D Sidewall Flash EPROM Cell and Memory Array" (Pein et al.), IEEE Electron Device Letters, vol. 14, No. 8, Aug. 1993, pp. 415-417. |
Continuations (1)
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Number |
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Parent |
PCTDE9602386 |
Dec 1996 |
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