HIGH-LEVEL SYNTHESIS FOR EFFICIENT VERIFICATION

Abstract

Verification friendly models for SAT-based formal verification are generated from a given high-level design wherein during construction the following guidelines are enforced: 1) No re-use of functional units and registers; 2) Minimize the use of muxes and sharing; 3) Reduce the number of control steps; 4) Avoid pipelines; 5) Chose functional units from “verification friendly” library; 6) Re-use operations; 7) Perform property-preserving slicing; 8) Support “assume” and “assert” in the language specification; and 8) Use external memory modules instead of register arrays.

Description

BRIEF DESCRIPTION OF THE DRAWING

A more complete understanding of the present invention may be realized by reference to the accompanying drawings in which:

FIG. 1( a)-1(f) show the steps associated with the High-Level synthesis of 1(a) a Program written in the C programming language; (b) a data flow graph for that program; 1(c) its allocation; 1(d) its scheduling; 1(e) its binding; and 1(f) controller generation;

FIG. 2 is schematic diagram showing current methodology of High-Level Synthesis with verification;

FIG. 3 is a schematic diagram showing High-Level Synthesis for Verification according to the present invention; and

FIG. 4 is a schematic diagram depicting the relationship of a verification model according to the present invention as compared with prior-art verification models and their relationships to an original design and an implementation model.

Claims

1. A method of generating a model exhibiting features that promote formal verification, said method comprising the steps of: generating the model utilizing High-Level Synthesis (HLS) tools; andverifying the generated model using formal verification methodology;SAID METHOD CHARACTERIZED IN THATcriteria used by the HLS are selected such that they enhance the subsequent verification by a verification method selected from the group consisting of SAT-based and SMT-based formal verification.

2. The method of claim 1 further CHARACTERIZED IN THAT the generated model exhibits no re-use of functional units and registers.

3. The method of claim 1 further CHARACTERIZED IN THAT the generated model exhibits minimal the use of muxes and sharing.

4. The method of claim 3 further CHARACTERIZED IN THAT the generated model exhibits a reduced number of control steps.

5. The method of claim 1 further CHARACTERIZED IN THAT the generated model exhibits limited pipeline usage.

6. The method of claim 1 further CHARACTERIZED IN THAT the generated model uses external memory modules instead of register arrays.

7. The method of claim 1 further CHARACTERIZED IN THAT the generated model has reduced reachable control states at each depth.

8. The method of claim 1 further CHARACTERIZED IN THAT the generated model uses functional units selected from a library of functional units that exhibit one or more of the following characteristics: 1) no re-use of functional units and registers; 2) Minimal use of muxes and sharing; 3) reduced number of control steps; 4) no pipelines; 5) employ property-preserving slicing; 6) support for assume and assert in the language specification; and 7) use external memory modules instead of register arrays.