The present invention relates to structures and methods designed to increase the capacity of high performance memory systems.
The present invention is applicable to most types of memories such as dynamic random access memory (DRAM), static random access memory (SRAM), nonvolatile memories, etc. Among the wide varieties of possible applications, the most well known applications are the main memory in computers. We will focus on computer main memory using double data rate version 2 (DDR2) dynamic random access memories (DRAM) as examples to demonstrate the basic principles of the present invention. The scope of the present invention is certainly not limited to particular types of memory or particular types of applications used in our examples.
A “memory system” defined in this patent application is board level circuits supporting memory operation of memory chips. A “memory module” is defined as a sub-circuit of a memory system. A “system level signal” is defined as an electrical signal used to communicate with circuits external to a memory system. A “chip level signal” is defined as an electrical signal used to communicate with memory chips.
It is well known that the performance of a computer is strongly dependent on both the performance as well as the capacity of its main memory. Ideally, a computer wants to have high performance system memory at as large capacity as possible. In reality, high performance and high capacity have conflicting requirements that can become limiting factors. We will discuss key factors on those limitations using typical personal computer memory systems as examples.
The most common memory chip used for computer system memory is DRAM. Table 1 lists typical chip level interface signals for a current art 1 G (230) bit DDR2 synchronized DRAM integrated circuit chip.
DRAM chips are typically mounted on small printed circuit board (PCB) called Single-In-line Memory Module (SIMM) or Dual-In-line Memory Module (DIMM); a DIMM is equivalent to two SIMM modules placed into one PCB utilizing both sides of the circuit board. The SIMM or DIMM memory modules provide the flexibility to expand the capacity of computer main memory. The memory controller in chipset typically has the flexibility to support 8 SIMM or 4 DIMM modules. A personal computer typically starts with one installed DIMM or SIMM module while providing additional empty sockets. A user who wants to improve the performance of computer can insert additional modules into the expandable sockets. To support such expandable memory systems, personal computers typically support a system level memory interface with signals listed in Table 2. Beside DQS and DQS#, DDR2 DRAM may have another set of data strobe RDQS and RDQS#; sometimes only one data strobe DQS is used without using DQS#. We will consider those data strobe signals (DQS, DQS#, RDQS, RDQS#) as part of data signals. The scope of the present invention should not be limited on particular types of data strobes.
If we draw all these signals in our figures, the resulting figures will be very busy, making it less clear in demonstrating the key points of the present invention. Therefore, in our figures the interface signals are simplified into two groups, namely data signals and control signals. Data signals (DB) are signals directly related to data transfers while following the same signal transfer protocols, including the data bus (DQ), data strobe (DQS and #DQS), and input data mask (DM) signals. Control signals (CTL) are signals used to determine operation states of the memory chips, including the addresses, bank addresses, clocks signals (CK, CK#, CKE), chip select signal (CS#), and command inputs (RAS#, CAS#, WE#). We will not show DC or slow signals such as power lines, reference voltage signals, EEPROM signals, and on-die-termination signals because those connections are not related to the key factors of the present invention. To facilitate clear understanding of the present invention, there is no need to show those details that are well known to people skilled in the art; we will focus on the key elements related to the present invention—the data and control signals of memory chips. For simplicity, the optional parity/ECC data signals are also not included in our discussion because a person with ordinary skill in the art would understand how to apply the present invention on the parity/ECC signals upon disclosure of our examples. The simplified representations of memory interface signals used in our discussions are listed in Table 3.
The above representations are used to simplify our figures in order clearly disclose the key features of the present invention; the scope of the present invention should not be limited in particular ways of signal representations. For example, one may want to include ODT0-ODT8 signals in CTL.
Using the simplified representations in Table 3, the architectures of typical prior art memory systems can be illustrated by
A common prior art method to increase the capacity of a memory system is to use DIMM modules instead of SIMM modules.
If we want to have larger capacity than a DIMM module, we need to add more memory modules to the system.
The capacity of the memory system in
One prior art solution to solve the loading problem is to use phase locked loop (PLL) to generate local clock signals, and use buffers to generate local control signals. Such methods reduce the loading on control signals, but the loading problems in data signals are not solved. One of the most popular examples for this approach is the Register DIMM (RDIMM) approach. An RDIMM uses PLL to generate local clock and use a “register chip” that comprises latches to buffer control signals; the price to pay for RDIMM approach is one additional clock latency, and the RDIMM approach does not solve loading problems in data signals.
Another prior art solution for the loading problem is the JEDEC standard “Fully Buffered DIMM” (FBDIMM) approach. An FBDIMM uses an integrated circuit (IC) chip called “Advanced Memory Buffer (AMB)” to control all the interface signals to all memory chips on the module. The loadings on memory chip data and control signals are therefore completely isolated from other memory modules.
To increase the capacity of an FBDIMM system, multiple FBDIMM modules (FM1-FM8) are connected in daisy-chained bus architecture as illustrated in
It is therefore highly desirable to provide other solutions that can increase total capacity of memory systems without the drawbacks of existing solutions such as FBDIMM approaches.
This application is a continuation-in-part application of previous patent application with a Ser. No. 11/874,914 (914 application) with the same title and filed by the applicant of this invention on Oct. 19, 2007. While the 914 application had covered key features of this application, further detailed examples were provided in FIGS. 6(a-e). In addition, example methods to reduce package loadings for the present invention are illustrated in
The primary objective of this invention is, therefore, to provide high capacity memory systems without increasing the loading of data signals. The other primary objective of this invention is to achieve the above objective with minimum overhead in performance and in cost. Another objective is to achieve the above objectives while using interfaces that are compatible with conventional memory systems. These and other objectives are achieved by using multiplexing to isolate loadings on data signals. The resulting memory systems are capable of achieving high capacity with basically the same performance and power of a single conventional memory. The interface signals also can be compatible with conventional memory systems.
While the novel features of the invention are set forth with particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawing.
a-c) are simplified schematic block diagrams for prior art conventional memory systems;
a-c) are simplified schematic block diagrams for prior art FBDIMM systems;
a) is a simplified schematic block diagram for one example of the Multiplexed Memory Buffer (MMB) module of the present invention;
b) is a simplified symbolic diagram for the bidirectional multiplexer in
c) is a simplified schematic block diagram for one example of the MMB memory system of the present invention;
a) is a simplified schematic block diagram for one example of the Multiplexed Bus Memory Buffer (MBMB) module of the present invention;
b) is a simplified symbolic diagram for the bidirectional multiplexer in
c) is a simplified schematic block diagram for MBMB one example of the memory system of the present invention;
a) is an example for the simplified schematic diagram of the circuits connected to one data signal in an MMB system;
b) is an example for simplified schematic diagram of the circuits connected to one data signal in an MBMB system;
c-e) are examples for the branch switches used by the present invention; and
a-c) are examples for the methods to reduce package loadings.
a) is a simplified schematic block diagram for one example of the Multiplexed Memory Buffer (MMB) module of the present invention. In this example, the MMB memory module (MMB1) comprises 8 memory chips (M11, M21, M31, M41, M51, M61, M71, M81). Comparing to the prior art memory module in
Since data signals of memory chips are typically bi-direction signals (with possible exceptions such as input data masks), the multiplexers (MUX8) in MMB modules actually need to have both multiplexing and de-multiplexing functions. We will call such circuitry as “bidirectional multiplexer” in our discussions. A person with ordinary skill in circuit design would be able to design bidirectional multiplexers in wide varieties of configurations.
c) is the simplified schematic block diagram for an MMB memory system that has the same capacity as the prior art memory system in
It is well known that a properly controlled bidirectional multiplexer is able to isolate the loadings on unselected branches. The bidirectional multiplexer itself introduces additional loading, but such loading can be designed to be insignificant relative to overall loading. The bidirectional multiplexer also introduced additional delay, but such additional delay can be designed to be insignificant relative to overall delay. The selection logic signal (SM) of the bidirectional multiplexer (MUX8) is determined from system level control signals (CTL) by the MMB Select logic circuitry. The MMB Select logic circuitry can isolate the loading seen by the system level control signals (CTL), but it also introduces additional delays. However, the buffer delay can be designed to be insignificant. In many cases, we may not need to buffer the control signals. The logic function of the MMB Select logic circuitry is similar to DRAM data bus control logic circuits that are well known to the industry. An MMB is certainly by far less complex than a prior art AMB. Upon disclosure of the present invention, a person with ordinary skill in the art will certainly be able to design the MMB in wide varieties of ways so that there is no need to discuss in further details.
The MMB memory systems have many advantages comparing to prior art systems. It has identical functions and identical interface signals (DB1-DB8, CTL) as the prior art system in
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. Upon disclosure of the present invention, those skilled in the art will be able to develop wide varieties of circuits to implement the elements of the present invention. For example, there are many ways in designing the bidirectional multiplexer and supporting selection logic circuits. For another example, the chip select signals connected to memory chips in the same MMB group can be defined in many different ways. If each memory chip in the same MMB group has separated chip select signal, then the function of an MMB system is equivalent to the function of many conventional modules. If all the memory chips in the same MMB group are connected to the same chip select signal, then the function of a MMB group is equivalent to a memory chip of the combined capacity of all memory chips in the group. We certainly can use combinations of the above two chip selection methods. For another example, we can modify the data signal connection methods to define a variation of the MMB architecture called “Multiplexed Bus Memory Buffer” (MBMB) architecture as illustrated by
For the MMB example in
c) is the simplified schematic block diagram for an MBMB memory system that has the same capacity as the prior art memory system in
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. For example, each entry of MBMB multiplexer certainly can support more than 2 memory chips by trading higher loading to achieve lower costs. Different number of memory chips can be connected to different entries of multiplexers. The number of branch entries of each bidirectional multiplexer can be any number larger or equal to 2, not limited to 4 or 8 entries. We certainly can connect more modules to the MMB or MBMB systems. It is also possible to link MMB or MBMB modules with FBDIMM architectures to achieve very large capacity.
The above discussions showed system/module level architectures. In the following discussions, we will focus on one data signal in the memory systems.
a) is a schematic diagram illustrating the circuits connected to one system level data signal (DQ) in an MMB system of the present invention that has the same memory chips (MM1-MM8) as the prior art example shown in
b) is a schematic diagram illustrating the circuits connected to one system level data signal (DQ) in an MBMB system of the present invention that has the same memory chips (MM1-MM8) as the prior art example shown in
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. For example, the bidirectional multiplexer can be placed into an IC chip or separated into multiple chips. The memory chips supporting the same system level data signal can be placed into the same printed circuit board or placed at different printed circuit boards. It is even possible to place branch switches inside of memory chips. If all the branch switches of the same bidirectional multiplexer are placed into the same IC chip, typically we can achieve lower loading. If each branch is placed in a different IC chip at different printed circuit board, the overall loading maybe higher while it is easier to make the resulting PCB fully compatible with prior art modules. Upon disclosure of the present invention, a person with ordinary skill in the art would be able to design many different types of circuits to support implementations of the present invention. For example,
As discussed previously, the data signal loadings of an MMB system are about the same as that of a single prior art SIMM or DIMM plus overhead. Reducing loading overhead is therefore a major consideration in implementing the present invention. One of the major sources of such overhead is IC package loadings.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. There are wide varieties of COB technologies under development. The scope of the present invention should not be limited on particular implementations.
The present invention is a board level architecture developed to increase the total capacity of memory systems while isolating the loading of data signals by multiplexing. Comparing to prior art memory modules, the loadings of an MMB system of the present invention are equivalent to a prior art SIMM module. The variation of MMB system called MBMB system allows multiple memory chips to share the same entry of a bidirectional multiplexer in a bused connection. When each entry of a bidirectional multiplexer is shared by two memory chips, the equivalent loadings are about the same as a prior art DIMM module. Using MMB or MBMB architectures, we can achieve memory capacity much higher than prior art memory systems without significant degradation in system performance. The memory systems of the present invention can be fully compatible with prior art memory systems. The costs of MMB or MBMB systems are by far lower than the costs of prior art FBDIMM systems.
Prior art memory systems typically fit one memory module into one printed circuit board. That is not necessary the case for memory modules of the present invention. We often fit multiple modules into a single printed circuit board. A memory module of the present invention also can be placed in multiple printed circuit boards (for example, one branch entry in one PCB). It is also possible to fit the whole memory system into a single printed circuit board. The memory systems of the present invention can have identical system level interface as prior art systems. It is therefore possible to design printed circuit boards of the present invention that can use existing DIMM sockets with no or minimal modifications. The printed circuit boards of the present invention sometimes do not use all the interface signals on a conventional DIMM socket, and sometimes we may need more signals such as chip select signals and clock enable signals in other sockets. We may need to use additional board level connectors or small modifications in board interface to design circuit boards of the present invention that fit into prior art DIMM sockets.
A “memory system” is defined as board level circuits supporting memory operations. A “memory module” is defined as sub circuits of a memory system. A “system level signal” is defined as an electrical signal used to communicate with circuits external to a memory system. A “chip level signal” is defined as an electrical signal used to communicate with memory chips. The “Loading” on a signal is the non-ideal factors that can slow down performances such as leakage currents, parasitic capacitances, inductances, resistances, or termination resistors. A “bidirectional multiplexer” defined in the present invention is a circuitry that provides multiplexing as well as de-multiplexing functions for bidirectional signal communication; A “bidirectional multiplexer” has one “root entry” and a plurality of “branch entries”; During normal operation conditions, one or no branch entry of a bidirectional multiplexer is selected to communicate with the “root entry” while the loadings of unselected branch entries are isolated from the root entry; However “bidirectional multiplexer” allows exceptions, such as transitional operations or special mode operations, to have conditions when multiple branch entries are selected simultaneously. “Isolate loadings from a signal” means significantly reduce the effective loading caused by the signal. Different branch entries of a bidirectional multiplexer used by the present invention can be placed in the same chip, separated into different chips, placed on the same printed circuit board, or placed in different printed circuit boards. The scopes of the present invention should not be limited on detailed implementations of the branch entries of the bidirectional multiplexer. An “IC chip” is defined as packaged integrated circuit or integrated circuit bare die that is ready to be placed on printed circuit board. A “memory chip” is defined as packaged IC memories or bare die memory integrated circuit that is ready to be placed on printed circuit board. COB technologies are technologies that form connections between printed circuit boards to bare IC dice without package. FCOB technologies are variations of COB technologies that form connections between printed circuit boards to bare IC dice without using bounding wires.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all modifications and changes as fall within the true spirit and scope of the invention.
This application is a continuation-in-part application of previous patent application with a Ser. No. 11/874,914 with the same title and filed by the applicant of this invention on Oct. 19, 2007.
Number | Date | Country | |
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Parent | 11874914 | Oct 2007 | US |
Child | 11933556 | US |