1. Field of the Invention
The present invention is related to a sense amplifier, and more particularly, to a high speed and low offset current-latch type sense amplifier for SRAM application.
2. Description of the Prior Art
Sense amplifiers are used to detect differences between two voltages and common applications include reading the contents of memory cells in memory arrays. Sense amplifiers may adopt single-ended or differential schemes. A single-ended sense amplifier determines the state of a memory cell by comparing the potential of a single sense input with an internal current source or voltage source. A differential sense amplifier determines the state of a memory cell by comparing the relative voltages of two sense inputs and provides an output signal representative of a data value stored within the memory cell.
A typical sense amplifier includes a plurality of transistors whose characteristics may vary due to process, voltage, and temperature (PVT) variations. Such performance mismatch has great impact on the sensing ability of the sense amplifier. Therefore, there is a need for a high speed sense amplifier capable of compensating die-to-die PVT variations.
The present invention provides a single-ended sense amplifier including an input node arranged to receive an input signal and a reference signal; an output node arranged to output an output signal which reflects the input signal; a sensing circuit coupled between the input node and the output node; and an equalizing circuit connected between the input node and the output node. The sensing circuit is configured to detect a potential of the input node and generate an output signal according to the potential of the input node. The equalizing circuit is configured to bring the sensing circuit to a metastable state from which the sensing circuit switches to a high-level state or a low-level state in response to the potential of the input node crossing a threshold voltage.
The present invention also provides a differential sense amplifier including a first input node arranged to receive a first input signal; a second input node arranged to receive a second input signal; a first output node arranged to output a first output signal; a second output node arranged to output a second output signal; a sensing circuit coupled to the first input node, the second input node, the first output node and the second output node; and an equalizing circuit connected between the first output node and the second output node. The sensing circuit is configured to detect a potential of the first input node and a potential of the second input node and generate the first output signal and the second output signal according to a potential difference between the first input node and the second input node in an inverting state, wherein a potential difference between the first output signal and the second output signal reflects the potential difference between the first input signal and the second input signal. The equalizing circuit is configured to bring the sensing circuit to a metastable state from which the sensing circuit switches to the inverting state in response to the potential difference between the first input node and the second input node crossing a predetermined value.
The present invention also provides a sense amplifier including a first input node arranged to receive a first input signal; a first output node arranged to output a first output signal; a sensing circuit configured to supply the first output signal according to the first input signal; and an equalizing circuit configured to bring the sensing circuit to a metastable state from which the sensing circuit switches to an inverting state in response to a potential of the first input node crossing a first value.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In the sense amplifier 100 of the present invention, the sensing circuit 110 may include an inverting logic gate which is constructed with metal-oxide-semiconductor (MOS) transistors, bipolar junction transistors (BJT) or other devices with similar functions in a resistor-transistor logic (RTL), a transistor-transistor logic (TTL) or other configurations. In the embodiment illustrated in
The equalizing circuit 120, coupled between the input node IN0 and the output node OUT0, is configured to bring the sensing circuit 110 to a metastable state from which the sensing circuit 110 may promptly switches to a high-level state or a low-level state in response to the input signal SIN. In the embodiment illustrated in
The value of the input signal SIN depends on whether the memory cell is in the high or low conductivity state. After the reading of the memory cell starts, the voltages present on the input node IN0 begins to change in a way that depends on the pull strength of the input current SIN and the reference current SREF. If the memory cell is in the high conductivity state, the input signal SIN pulls more than the reference signal SREF, thereby increasing the potential VIN of the input node IN0. After VIN becomes sufficiently large to turn on the transistor TN0, the sensing circuit 110 promptly switches from the metastable state to the low-level state and generates the low-level output signal VOUT representing the memory cell in the high conductivity state. If the memory cell is in the low conductivity state, the reference signal SREF pulls more than the input signal SIN, thereby decreasing the potential VIN of the input node IN0. After VIN becomes sufficiently small to turn on the transistor TP0, the sensing circuit 110 promptly switches from the metastable state to the high-level state generates the high-level output signal VOUT representing the memory cell in the low conductivity state.
As previously stated, the characteristics of the devices in the sensing circuit 110 may vary due to die-to-die PVT variations. In other words, the transistors TP0 and TN0 may have different performances when switching between logic 0 and logic 1. The equalizing circuit 120 in the present invention may bring the sensing circuit 110 to the metastable state in which the input node IN0 and the output node OUT0 are both set to VM. The value of VM is between logic 0 and logic 1, and is associated with the overall characteristic of the sensing circuit 110. Therefore, each transistor may switch to logic 0 or logic 1 faster and die-to-die PVT variations may be compensated, thereby providing high speed and low offset read operation.
In the present invention, the sensing circuit 210 may include inverting logic gates which are constructed with MOS transistors, BJTs or other devices with similar functions in a four-transistor (4T), six-transistor (6T) or other configurations. In the embodiment illustrated in
The equalizing circuit 220, coupled between the output nodes OUT1 and OUT2, is configured to bring the sensing circuit 210 to the metastable state from which the sensing circuit 210 may promptly switches to an inverting state in response to in response to the potential difference between the input node IN1 and the input node IN2 crossing a predetermined value. In the embodiment illustrated in
Before the read operation, the input nodes IN1˜IN2 are set to a precharge level by a precharge circuit (not shown) and the output nodes OUT1˜OUT2 are set to VM by the equalizing circuit 220. After the reading of the memory cell starts, the voltages present on the input nodes IN1˜IN2 begin to decrease at different rates, creating a potential difference that depends on whether the memory cell is in the high or low conductivity state. The voltage difference between the input nodes IN1˜IN2 is amplified by the sensing circuit 210 and an amplified voltage difference appears between the output nodes OUT1˜OUT2. If the memory cell is in the high conductivity state, the voltage present on the input node IN1 drops more quickly than that on the input node IN2. If the memory cell is in the low conductivity state, the voltage present on the input node IN1 drops more slowly than that on the input node IN2. When the potential difference between the input nodes IN1 and IN2 becomes sufficiently large, the sensing circuit 210 promptly switches from the metastable state to the inverting state in which the voltage difference established between the output nodes OUT1˜OUT2 reflects the voltage difference between the input nodes IN1˜IN2.
As previously stated, the characteristics of the devices in the sensing circuit 210 may vary due to die-to-die PVT variations. In other words, the transistors TP1˜TP2 and TN1˜TN4 may have different performances when switching between logic 0 and logic 1. The equalizing circuit 220 in the present invention may bring the sensing circuit 210 to the metastable state in which the gates of the transistors TP1˜TP2 and TN1˜TN2 are set to VM. The value of VM is between logic 0 and logic 1, and is associated with the overall characteristic of the sensing circuit 210. Therefore, each transistor may switch to logic 0 or logic 1 faster and die-to-die PVT variations may be compensated, thereby providing high speed and low offset read operation.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.