Claims
- 1. A method of processing a packet, the method comprising the steps of:
receiving the packet; identifying a packet header portion of the data packet; transferring the packet header to a register file accessible to a processor; and processing the packet header without invoking at least one of a load instruction and a store instruction by the processor.
- 2. The method of claim 1, wherein the transferring step is performed without invoking at least one of a load instruction and a store instruction.
- 3. The method of claim 1 further comprising the steps of:
splitting the packet into the packet header portion and a packet body portion; transferring the packet header to the register file using a direct register access; and transferring the packet body to an output buffer.
- 4. The method of claim 3 further comprising the steps of:
selecting an output port for transmission of the packet; integrating the processed packet header with the packet body in the output buffer; and forwarding the integrated packet from the output buffer to the selected output port for transmission therefrom.
- 5. The method of claim 1 further comprising the steps of:
providing a plurality of identical processors executing a common instruction set, each processor storing the instruction set locally to the processor; selecting a processor from among the plurality to process the packet header; and causing the selected processor to process the packet header.
- 6. The method of claim 5, wherein the step of selecting the processor is performed by a state machine responsive to the receipt of the packet at an input port.
- 7. The method of claim 5, wherein the step of causing the selected processor to process the packet header is performed by at least one state machine configured to write the packet header to at least one fixed location in the register file accessible to the selected processor.
- 8. The method of claim 5, further comprising the step of downloading a common instruction set to an instruction memory in each of the plurality of processors.
- 9. A method of processing a packet header of a packet received over a communications network, the method comprising the steps of:
transferring the packet header to at least one fixed location in a register file; providing a processor associated with the register file, the processor repetitively executing an instruction in an infinite loop, the instruction being stored at a first known location in an instruction memory associated with the processor; causing the processor to execute instructions beginning at a second known location in the instruction memory responsive to the transfer of the packet header; processing the packet header in the at least one fixed location in the register file in accordance with the instructions beginning at the second known location in the instruction memory; and resetting the processor to repetitively execute the instruction stored at the first known location in the instruction memory upon completing the processing of the packet header.
- 10. The method of claim 9, wherein the processing step comprises processing the packet header without invoking at least one of a load instruction and a store instruction.
- 11. The method of claim 9, further comprising the steps of
receiving the packet at an input port coupled to the communications network; selecting the processor from a plurality of candidate processors associated with the input port; splitting the packet into the packet header and a packet body; and transferring the packet header to the at least one fixed location in the register file associated with the selected processor by executing a DRA command issued by a state machine coupled to the register file.
- 12. The method of claim 11, further comprising the step of downloading a common instruction set to an instruction memory in each of the plurality of candidate processors.
- 13. A packet-processing system for processing a packet received over a communications network, the system comprising:
an input port configured to receive the packet over the communications network; a processor associated with the input port; a register file accessible to the processor; and an ingress element coupled to the input port, processor, and register file, the ingress element being configured to transfer at least one portion of the packet to the register file by invoking a DRA command, wherein the processor processes the at least one portion of the packet in the register file in response to the DRA command and without invoking at least one of a load instruction and a store instruction.
- 14. The packet-processing system of claim 13, wherein the ingress element is configured to select the processor from a plurality of candidate processors associated with the input port.
- 15. The packet-processing system of claim 14, further comprising a plurality of instruction memories, each of the plurality of instruction memories being associated with a corresponding one of the plurality of candidate processors, wherein the plurality of instruction memories contain an identical instruction set.
- 16. The packet-processing system of claim 13, wherein the at least one portion of the packet corresponds to a header of the packet.
- 17. The packet-processing system of claim 16, wherein the ingress element comprises a state machine configured to write the packet header to a fixed location in the register file.
- 18. A packet-processing system for processing a packet header of a packet received over a communications network, the system comprising:
an input port coupled to the communications network; an ingress element coupled to the input port and configured to receive and parse the packet to obtain the packet header; a register file coupled to the ingress element and configured to store the packet header received from the ingress element at an at least one fixed location; an instruction memory configured to return instructions from at least a first and second address; and a processor coupled to the ingress element, register file, and instruction memory, the processor repetitively executing instructions stored at the first of the instruction memory, wherein the processor executes instructions beginning at the second address of the instruction memory to process the packet header in the register file in response to a signal from the ingress element.
- 19. An information-processing system comprising:
a processor having an internal register file space and a unit for manipulating data; an ingress element for delivering unprocessed data to the internal register file space; and an egress element for removing processed data from the internal register file space, wherein operation of the processor is confined to manipulating data within the internal register file space.
- 20. The system of claim 19 further comprising at least one state machine governing operation of the ingress and egress elements and responsive to instructions within the internal register file space, the state machine causing data to be moved into and out of the internal register file space using direct accesses thereto in accordance with the instructions.
- 21. The system of claim 20 further comprising a network interface receiving data from a communications network, the interface providing received data to the ingress element.
- 22. A method of information processing, the method comprising the steps of:
providing a processor having an internal register file space and a unit for manipulating data; and delivering unprocessed data to the internal register file space and removing processed data from the internal register file space using direct accesses to the internal register file space, operation of the processor being confined to manipulating data within the internal register file space.
- 23. The method of claim 22 further comprising the steps of:
providing at least one state machine governing delivery of data to and removal of data from the internal register file space using direct accesses thereto; and causing the processor to signal the state machine by writing a value into a control register, the state machine being responsive to the value and carrying out the direct accesses in accordance with a state machine logic.
- 24. The method of claim 22 wherein the unprocessed data originates with a communications network having a line data rate, the processor processing data at a rate equal to the line rate.
- 25. The method of claim 24 wherein the unprocessed data is in the form of packets.
- 26. A method of processing a packet stream comprising a temporal sequence of packets, the method comprising the steps of:
providing a plurality of identical processors executing a common instruction set, each processor storing the instruction set locally to the processor; receiving the packets; for each packet, (i) identifying a packet header portion of the data packet, (ii) selecting a processor from among the plurality to process the packet header based on processor availability, and (iii) causing the selected processor to process the packet header using the locally stored instructions; and assembling the processed packets to reconstruct the packet stream in accordance with the temporal sequence.
- 27. The method of claim 26 wherein the plurality of processors is physically located on a plurality of integrated circuits.
- 28. A system for processing a packet stream comprising a temporal sequence of packets, the system comprising:
a plurality of identical processors executing a common instruction set, each processor comprising a local instruction memory containing the instruction set; an input port for receiving the packets; an ingress logic unit coupled to the input port and to the processors, the ingress logic unit being configured, for each packet, to (i) identify a packet header portion of the data packet and (ii) select a processor from among the plurality to process the packet header based on processor availability, the selected processor responding to the ingress logic unit by processing the packet header using the locally stored instructions; and an egress logic unit for assembling the processed packets to reconstruct the packet stream in accordance with the temporal sequence.
- 29. The system of claim 28 wherein the plurality of processors is physically located on a plurality of integrated circuits.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This claims priority to and the benefit of U.S. provisional patent application number 60/186,782, filed Mar. 3, 2000, the entirety of which is incorporated herein by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60186782 |
Mar 2000 |
US |