Claims
- 1. A memory system capable of selectively operating in chip-kill mode and non-chip-kill mode, comprising:a memory controller, a plurality of memory devices, a channel including a data bus connecting the memory controller and the plurality of memory devices; the memory system comprising circuitry to determine whether the memory system is operating in non-chip-kill mode or in chip-kill mode; the memory controller comprising circuitry to generate a Read command to the plurality of memory devices via the channel; in response to the Read command, upon a determination that the memory system is operating in non-chip-kill mode, at least one of the plurality of memory devices returns a first data block to the memory controller via the data bus during a first time period; and, in response to the Read command, upon a determination that the memory system is operating in chip-kill mode, each one of the plurality of memory devices returns a second data block, smaller than the first data block, to the memory controller via the data bus during a second time period within the first time period.
- 2. The memory system of claim 1, wherein the first data block forms a data packet returned to the memory controller during the first time period; andwherein a combination of second data blocks returned to the memory controller by the plurality of memory devices during the first time period forms the data packet.
- 3. The memory system of claim 2, wherein the first time period comprises a number of clock cycles and the second time period comprises a half clock cycle.
- 4. The memory system of claim 3, wherein the first data block comprises at least sixteen bytes of data and the second data block comprises at least two bytes of data.
- 5. The memory system of claim 2, wherein the data bus comprises a first set of data lines and a second set of data lines, andwhen the memory system is operating in non-chip-kill mode, the at least one memory device returns to the memory controller one byte of data on the first set of data lines and another byte of data on the second set of data lines during each second period of time in the first period of time; and when the memory system is operating in chip-kill mode, each one of the plurality of memory devices returns to the memory controller one byte of data on the first set of data lines and another byte of data on the second set of data lines during a selected half clock cycle in the first period of time.
- 6. The memory system of claim 2, wherein at least one of the second data blocks comprises syndrome data, and wherein the memory controller further comprises an error correcting code (ECC) generator responsive to the syndrome data to detect at least one data error in the data packet.
- 7. The memory system of claim 6, wherein each second data block contains syndrome data, and wherein the ECC generator is responsive to the syndrome data from the second data blocks to detect at least one data error in the data packet, the ECC generator further comprising circuitry to determine at least one of the plurality of memory devices providing a second data block containing the detected at least one data error.
- 8. The memory system of claim 7, wherein the memory system further comprises:a spare memory device; and circuitry to replace the at least one of the plurality of memory devices providing a second data block containing the detected at least one error with the spare memory device.
- 9. A method of selectively providing a non-chip-kill mode and a chip-kill mode of operation in a memory system comprising a memory controller, memory devices, and a channel comprising a control/address bus connecting the memory controller and the memory devices, and a data bus connecting the memory controller and the memory devices, the method comprising:upon determining that the memory system is operating in non-chip-kill mode, generating a Read command in the memory controller, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning to the memory controller a first data block from at least one of the memory devices during a first time period; and upon determining that the memory system is operating in chip-kill mode, generating a Read command in the memory controller, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning a second data block from each one of a plurality of the memory devices during the first time period.
- 10. The method of claim 9, further comprising:when operating in non-chip-kill mode, receiving the first data block at the memory controller as a data packet during the first time period; and, when operating in chip-kill mode, receiving at the memory controller a second data block from each one of the plurality of memory devices during the first time period, and combining the received second data blocks into the data packet.
- 11. The method of claim 10, wherein the memory controller sequentially receives a second data block from each one of the plurality of memory device during a second time period in the first time period.
- 12. The method of claim 11, wherein the first time period is equal to a number of clock cycles in the memory system and the second time period equals a half clock cycle.
- 13. The method claim of claim 11, wherein the memory system further comprises an error correcting code (ECC) generator, and wherein at least one of the second data blocks returned from the plurality of memory devices comprises syndrome data, the method further comprising:evaluating the syndrome data in the ECC generator to detect at least one error, if present, in the data packet.
- 14. The method of claim 11, wherein the memory system further comprises an error correcting code (ECC) generator, and wherein each second data block comprises syndrome data, the method further comprising:evaluating the syndrome data in the ECC generator to determining whether a data error exists; and, upon determining that a data error exists, correcting the data error.
- 15. The method of claim 11, wherein the memory system further comprises an error correcting code (ECC) generator and a spare memory device, and wherein at least one of the second data blocks comprises syndrome data, the method further comprising:evaluating the syndrome data in the ECC generator to determining whether at least one data error exists, and which second data block contained the at one data error; and, replacing the memory device providing the second data block containing the at least one data error with the spare memory device in the event that the at least one data error comprises at least two data errors.
- 16. A memory system capable of selectively operating in non-chip-kill and chip-kill modes, comprising a memory controller, a plurality of memory devices, and a channel connecting the memory controller and the plurality of memory devices; each memory device comprising:a memory core having an array of memory locations arranged in columns and rows; a column decoder addressing the columns, and a row decoder addressing the rows, the column and row decoders cooperating to select memory locations in the memory core; a plurality of input/output (I/O) amplifiers, each I/O amplifier being associated with a column; a CAS timing generator providing an I/O amplifier enable signal to the plurality of I/O amplifiers to selectively control data transfer flow from the memory core to the channel; the memory system further comprising: a chip kill control circuit and a chip kill decoder; wherein the chip kill control circuit receives at least a portion of a command packet from the memory controller via the channel, and in response thereto provides a chip kill decoder control signal to the chip kill decoder; wherein the chip kill decoder, upon receiving the chip kill decoder control signal and upon receiving a chip kill enable signal indicating that the memory system is operating in chip-kill mode, communicates a control signal to the CAS timing generator, whereupon the CAS timing generator defines the I/O amplifier enable signal in response to the control signal.
- 17. The memory system of claim 16, wherein the chip kill control circuit also provides a chip kill enable signal to the chip kill decoder.
- 18. The memory system of claim 16, wherein the chip kill control circuit comprises logic implementing a transmission cycle control map, any one selection from the transmission cycle control map defining the chip kill decoder control signal.
- 19. The memory system of claim 18, wherein the chip kill control circuit also receives a device identification (ID) signal, such that the device ID signal and the portion of the command packet are used to address a selection from the transmission cycle control map.
- 20. The memory system of claim 19, wherein the plurality of memory devices activates in response to a first portion of the first device ID field, and a second portion of the first device ID field is used to perform sub-page referencing within the plurality of memory devices.
- 21. The memory system of claim 16, wherein the memory controller communicates a ROW packet and a COL packet to the plurality of memory devices via the channel as part of a data transfer operation, the ROW packet comprising a first device identification (ID) field, and the COL packet comprising a second device identification (ID) field;wherein the chip kill control circuit receives at least a portion of the second device ID field, and uses the portion of the second device ID field to generate a chip kill decoder control signal.
- 22. A memory system capable of selectively operating in chip-kill mode and non-chip-kill mode, comprising:a memory controller, memory devices, and a channel comprising an address/control bus connecting the memory controller and the memory devices, and a data bus comprising a plurality of data lines connecting the memory controller and the memory devices; the memory system comprising circuitry to determine whether the memory system is operating in non-chip-kill mode or in chip-kill mode; the memory controller further comprising circuitry to generate a Read command and transmit the Read command to at least a plurality of the memory devices via the address/control bus; in response to the Read command, upon a determination that the memory system is operating in non-chip-kill mode, at least one of the plurality of memory devices returns a first data block to the memory controller via the data bus during a first period of time; and, in response to the Read command, upon a determination that the memory system is operating in chip-kill mode, each one of the plurality of memory devices simultaneously returns a second data block to the memory controller via at least one dedicated data bus line during the first period of time.
- 23. The memory system of claim 22, wherein the first data block comprises a data packet returned to the memory controller during the first time period; andwherein a combination of the second data blocks returned by the plurality of memory devices during the first time period comprises the data packet.
- 24. The memory system of claim 23, wherein at least one of the second data blocks comprises syndrome data, and the memory system further comprises an error correcting code (ECC) generator responsive to the syndrome data to perform an error detection algorithm on at least a portion of the data packet.
- 25. The memory system of claim 24, wherein each one of the second data blocks comprises syndrome data, and the memory system further comprises an error correcting code (ECC) generator, and a spare memory device;wherein the ECC generator performs an error detection algorithm using syndrome data from each second data block to determine if at least one data error is present in each second data block; upon determining that a second data block includes one data error, correcting the one data; and, upon determining that a second data block includes more than one data error, replacing the memory device providing the second data block containing the more than one error with the spare memory device.
- 26. A method of selectively providing a non-chip-kill mode and a chip-kill mode of operation in a memory system comprising a memory controller, memory devices, and a channel comprising a control/address bus connecting the memory controller and the memory devices, and a data bus comprising a plurality of data bus lines connecting the memory controller and the memory devices, the method comprising:upon determining that the memory system is operating in non-chip-kill mode, generating a Read command, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning to the memory controller a first data block from at least one of the memory devices via the data bus during a first time period; and upon determining that the memory system is operating in chip-kill mode, generating a Read command in the memory controller, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning a second data block from each one of a plurality of the memory devices via at least one dedicated data bus line during the first time period.
- 27. The method of claim 26, further comprising:when operating in non-chip-kill mode, receiving the first data block at the memory controller as a data packet during the first time period; and, when operating in chip-kill mode, receiving at the memory controller a second data block from each one of the plurality of memory devices during the first time period, and combining the received second data blocks into the data packet.
- 28. The method of claim 27, wherein the first time period is equal to a number of clock cycles in the memory system and the second time period equals a half clock cycle.
- 29. The method claim of claim 27, wherein the memory system further comprises an error correcting code (ECC) generator, and wherein at least one of the second data blocks returned from the memory devices comprises syndrome data, the method further comprising:evaluating the syndrome data in the ECC generator to detect at least one error, if present, in the data packet.
- 30. The method of claim 27, wherein the memory system further comprises an error correcting code (ECC) generator, and wherein each one of the second data blocks comprises syndrome data, the method further comprising:evaluating the syndrome data in each second data block in the ECC generator; determining whether each second data block contains a data error; and, upon determining that a second data block contains an error, correcting the error.
- 31. The method of claim 27, wherein the memory system further comprises an error correcting code (ECC) generator and a spare memory device, and wherein at least one of the second data blocks comprises syndrome data, the method further comprising:evaluating the syndrome data to determine whether at least one error is present in the data packet; upon detecting the at least one data error, determining which second data block contains the at least one data error; upon determining that the at least one data error comprises one data error, correcting the data error; and, upon determining that the at least one data error comprises more than one data error, replacing the memory device providing the second data block containing the more than one error with the spare memory device.
- 32. A memory system capable of selectively operating in chip-kill mode and non-chip-kill mode, comprising:a memory controller, memory devices, and a channel comprising an address/control bus connecting the memory controller and the memory devices, and a data bus comprising a plurality of data lines connecting the memory controller and the memory devices; the memory system comprising circuitry to determine whether the memory system is operating in non-chip-kill mode or in chip-kill mode; the memory controller further comprising circuitry to generate a Read command and transmit the Read command to the memory devices via the address/control bus; in response to the Read command, upon a determination that the memory system is operating in non-chip-kill mode, at least one of the memory devices returns a first data block to the memory controller via the data bus during a first period of time; and, in response to the Read command, upon a determination that the memory system is operating in chip-kill mode, each one of a plurality of the memory devices simultaneously returns a second data block to the memory controller via at least a selected one data bus line during each second time period in the first period of time.
- 33. The memory system of claim 32, wherein the first period of time comprises a sequence of second time periods, and wherein the at least selected one data bus line changes with each second time period in the sequence of second time periods.
- 34. The memory system of claim 33, wherein the first data block comprises a data packet returned to the memory controller during the first time period; andwherein a combination of the second data blocks returned by the plurality of memory devices during the sequence of second time periods comprises the data packet.
- 35. The memory system of claim 32, wherein at least one of the second data blocks comprises syndrome data, and the memory system further comprises an error correcting code (ECC) generator responsive to the syndrome data to perform an error detection algorithm on the data packet.
- 36. A method of selectively providing a non-chip-kill mode and a chip-kill mode of operation in a memory system comprising a memory controller, memory devices, and a channel comprising a control/address bus connecting the memory controller and the memory devices, and a data bus comprising a plurality of data bus lines connecting the memory controller and the memory devices, the method comprising:upon determining that the memory system is operating in non-chip-kill mode, generating a Read command, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command returning to the memory controller a first data block from at least one of the memory devices via the data bus during a first time period, wherein the first time period comprises a plurality of second time periods; upon determining that the memory system is operating in chip-kill mode, generating a Read command, transmitting the Read command to the memory devices via the control/address bus, and in response to the Read command, each one of a plurality of the memory devices returns a second data block to the memory controller via a selected data bus line every second time period during the first time period.
- 37. The memory system of claim 36, wherein the selected one data bus line changes each second time period.
- 38. A memory system capable of selectively operating in non-chip-kill mode and chip-kill mode, comprising:a memory controller, memory devices, and a channel comprising a control/address bus connecting the memory controller and the memory devices, and a data bus connecting the memory controller and the memory devices; wherein the memory controller generates a Read command and transmits the Read command to the memory devices via the control/address bus, the Read command comprising at least a ROW packet and a COL packet, such that; while operating in non-chip-kill mode the ROW packet activates one of the memory devices, and the COL packet causes a first data block to be read from the activated memory device during a first time period; and, while operating in chip-kill mode the ROW packet activates a plurality of the memory devices, and the COL packet causes a second data block to be read from each one of the activated plurality of memory devices during the first time period.
- 39. The memory system of claim 38, wherein the first time period comprises a plurality of second time periods, such that in response to the COL packet one of the activated plurality of memory devices has a second block of data read therefrom during each second time period.
- 40. The memory system of claim 38, wherein the first data block comprises a data packet, and wherein a combination of the second data blocks read from the activated plurality of memory devices during the first time period comprises the data packet.
- 41. The memory system of claim 38, wherein the ROW packet comprises a first device identification (ID) field, such thatwhile the memory system is operating in non-chip-kill mode, the first device ID field provides a unique activation code for the one memory device, and while the memory system is operating in chip-kill mode, a first portion of the first device ID field provides an common activation code for the plurality of memory devices.
- 42. The memory system of claim 41, wherein each one of the memory devices is arranged in a plurality of sub-pages, and wherein a second portion of the first device ID field performs sub-page referencing for the activated plurality of memory devices while the memory system is operating in chip-kill mode.
- 43. The memory system of claim 41, wherein a second portion of the first device ID field comprises error correction data for the ROW packet.
- 44. The memory system of claim 43, wherein the error correction data comprises one or more parity check bits for the ROW packet.
- 45. The memory system of claim 41, wherein the COL packet comprises a second device ID field, such thatwhile the memory system is operating in non-chip-kill mode, data is read from the one activated memory device in accordance with the second device ID field; and, while the memory system is operating in chip-kill mode, data is read from the plurality of activated memory devices in accordance with a first portion of the second device ID field.
- 46. The memory system of claim 45, further comprising a chip kill control circuit associated with each memory device, such thatwhile the memory system is operating in chip kill mode, a second portion of the second device ID field is applied to a chip kill control circuit decoder associated with each one of the activated plurality of memory devices; wherein the chip kill control circuit generates a control signal defining from which one of the plurality of activated memory devices a second data block will be read for each second time period in the first time period.
- 47. The memory system of claim 46, wherein the control/address bus and the data bus each comprise multiple wires;wherein a logic 0 within the memory system is defined by a terminal voltage on any one of the multiple wires; and, wherein the memory controller and each one of the memory devices assert a logic 1 within the memory system by sinking current from any one of the multiple wires using an open-drain NMOS transistor structure.
- 48. The memory system of claim 47, wherein during each second time period in which an activated memory device does not have a second block of data read therefrom in accordance with the control signal, that activated memory device outputs all logic 0's onto the data bus.
- 49. The memory system of claim 45, wherein the chip kill control circuit comprises logic defining a transmission cycle map, any one selection from the transmission cycle map defining the control signal.
- 50. The memory system of claim 49, wherein a transmission cycle map selection is made in accordance with the second portion of the second device ID field and in accordance with a device activation code common to the plurality of activated memory devices.
- 51. The memory system of claim 45, wherein each one of the plurality of activated memory devices internally generates a byte read mask in response to the control signal.
Parent Case Info
This application claims benefit of Provisional No. 60/145,222 filed Jul. 23, 1998.
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