Claims
- 1. A high speed readout circuit for reading out data of a memory unit, comprising:
- an amplifier unit having an input terminal and an output terminal for sensing variations from a preset voltage on a sense line so as to read out stored data; and
- an operating point setting unit for setting an operating point of said amplifier by short-circuiting the input and output terminals of said amplifier unit and for precharging said sense line to said operating point in response to a first signal, said operating point setting unit including capacitor means for setting the voltage on said sense line to a value having a predetermined slight deviation from said operating point in response to a second signal.
- 2. A high speed readout circuit according to claim 1 wherein said amplifier unit includes an inverter circuit.
- 3. A high speed readout circuit according to claim 2 wherein said inverter circuit includes two metal oxide semiconductor transistors connected in series.
- 4. A high speed readout circuit according to claim 1 wherein said operating point setting unit includes a metal-oxide semiconductor transistor coupled to said input and output terminals of said amplifier unit.
- 5. A high speed readout circuit according to claim 4 wherein said capacitor means includes the capacitance of said metal oxide semiconductor transistor of said operating point setting unit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
63-270792 |
Oct 1988 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/426,545 filed Oct. 26, 1989 now abandoned.
US Referenced Citations (5)
Foreign Referenced Citations (1)
Number |
Date |
Country |
59-24493 |
Feb 1984 |
JPX |
Continuations (1)
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Number |
Date |
Country |
Parent |
426545 |
Oct 1989 |
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