Claims
- 1. A semiconductor device comprising:
- a semiconductor substrate of a first conductivity type;
- a first well of a second conductivity type opposite to said first conductivity type, said first well being formed in an annular first surface region of said substrate;
- a second well of said first conductivity type formed in a second surface region of said substrate surrounded by said first surface region, said second well having a side surface coupled to a side surface of said first well and a bottom surface substantially flush with at least a part of a bottom surface of said first well;
- a third well of said second conductivity type formed within said substrate, said third well being coupled directly to said bottom surface of said second well and coupled directly to said at least a part of said bottom surface of said first well, said third well having an impurity concentration higher than an impurity concentration of said first well; and
- a MOSFET having a source formed in said first well, a drain formed in said second well, said source and drain being of said first conductivity type.
- 2. A semiconductor device as defined in claim 1 wherein said MOSFET of said first conductivity type has a rated voltage of 35 volts or higher.
- 3. A semiconductor device as defined in claim 2 further comprising a fourth well of said first conductivity and a fifth well of said second conductivity type both formed in a third and a fourth surface regions of said substrate, respectively, for receiving sources and drains of a CMOSFET.
- 4. A semiconductor device as defined in claim 3 wherein said fourth well has a side surface coupled to another side surface of said first well.
- 5. A semiconductor device as defined in claim 3 wherein said fourth well has a side surface apart from said first well.
- 6. A semiconductor device as defined in claim 1 wherein said MOSFET has a gate, overlying a junction between said first well and said second well, for controlling current flowing between said source and drain.
- 7. A semiconductor device as defined in claim 6 further comprising a field oxide film having a portion overlying a part of said second well and underlying a part of said gate.
- 8. A semiconductor device as defined in claim 1 wherein said first conductivity type is a p-conductivity type.
- 9. A semiconductor device as defined in claim 1 wherein said second conductivity type is an n-conductivity type.
- 10. A semiconductor device as defined in claim 1, wherein said first well is an annular surface region in said substrate.
- 11. A semiconductor device as defined in claim 10, wherein said second well is surrounded by said first well.
Priority Claims (1)
Number |
Date |
Country |
Kind |
7-040185 |
Feb 1995 |
JPX |
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Parent Case Info
This is a divisional of application Ser. No. 08/607,424 filed Feb. 28, 1996 pending.
US Referenced Citations (4)
Foreign Referenced Citations (2)
Number |
Date |
Country |
61-174666 |
Aug 1986 |
JPX |
1-64251 |
Mar 1989 |
JPX |
Non-Patent Literature Citations (2)
Entry |
S. Ghandhi, VLSI Fabrication Principles, Silicon and Gallium Arsenide, pp. 346-348 (1983). |
S. Wolf, Silicon Processing for the VLSI Era, pp. 383-386 (1990). |
Divisions (1)
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Number |
Date |
Country |
Parent |
607424 |
Feb 1996 |
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