Patent Application
20060092695
1. Field of the Invention
This invention relates to hybrid electromechanical and semiconductor memory arrays and, in particular, to hybrid electromechanical and semiconductor memory arrays providing single cycle read and write accesses.
2. History of the Prior Art
Memory structures are an essential building block for electronics devices and systems. Important characteristics of these structures are data retention, density, cost, power, and speed. There are a number of different types of memory structures which display differing characteristics making them suitable for different applications.
For example, read only memory (ROM) is relatively low cost but cannot be written. Programmable read only memory (PROM), electrically programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM) have read cycles that are fast relative to ROM and can be written; however, each has relatively long erase times and can be written reliably only over a only few iterative read/write cycles. Dynamic random access memory (DRAM) may be written and read rapidly but stores charge on capacitors which must be electrically refreshed by separate circuitry every few milliseconds to retain the memory contents. Static random access memory (SRAM) does not need to be refreshed and is fast relative to DRAM but is also more expensive. Both SRAM and DRAM are volatile in the sense that they do not retain stored data when power to the computer is removed.
Recently, the authors of “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing,” Science, vol. 289, pp. 94-97, Jul. 7, 2000, proposed memory devices which use nanoscopic wires, such as single-walled carbon nanotubes, to form crossbar junctions to serve as memory cells. The article describes individual single-walled nanotube wires suspended over other wires to define memory cells. Electrical signals are written to one or both wires to generate electrostatic fields which cause the wires to physically attract one another. Wires which have not been attracted form an open circuit junction, while attracted wires touch and form a rectified junction. Each physical state (i.e., attracted or open) corresponds to an electrical state. When electric power is removed from the junction, the wires retain their physical (and thus electrical) state thereby forming a non-volatile memory cell. The carbon nanotube memory cell device described in the article is referred to hereinafter as an electromechanical device or MEMS.
U.S. Pat. No. 6,574,130, entitled “Hybrid Circuit Having Nanotube Electromechanical Memory,” Segal et al, furnishes additional details including modifications for manufacturability of such memory devices including various forms of the nanoscopic elements themselves such as web-like meshes.
As the patent discloses, it is possible to construct a hybrid semiconductor and electromechanical technology memory cell as part of a memory array device with circuit connections to address decode logic, input/output data logic, and control logic to enable read, write/erase accesses. Typically these accesses are synchronized to a periodic signal (clock). Various connection schemes and associated signaling are possible with these hybrid technology memory cells and arrays. Such hybrid memory cells and arrays may be used to form the more complicated circuits and systems (e.g., field programmable memory arrays) which find use in advanced electronic systems such as computers.
Even though these new nanotube devices provide dense, non-volatile memory structures which may be written and read relatively rapidly, it is desirable to enhance the operations of nanotube memory structures. It is especially desirable to provide hybrid memory cell arrays embodying a connection and signaling scheme to allow single cycle accesses for both read and write operations.
The present invention is realized by a memory array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory cells to be of a single cycle.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views. It is to be understood that, in some instances, various aspects of the invention may be shown exaggerated or enlarged to facilitate an understanding of the invention, and in other instances, some aspects of the invention considered to be conventional may not be shown so as to avoid obfuscating more important aspects or features of the invention.
The cell 100 includes both storage circuitry and access circuitry. N type metal oxide semiconductor (NMOS) device 101 and P type metal oxide semiconductor (PMOS) device 105 are connected together and to supply terminals as a first inverter gate device. Specifically, the gate terminals of the two metal oxide semiconductor (MOS-NMOS/PMOS) devices are tied together (node 108), and the drain terminals are tied together (node 107). The source terminal of the PMOS device 105 is connected to a positive supply, and the source terminal of the NMOS device 101 is connected to a negative supply (ground in this case). The shared gate node 108 may be viewed as the input node of the first inverter, and the shared drain node 107 may be viewed as the output node of the first inverter. Similarly, NMOS device 102 and PMOS device 106 are connected to form a second inverter gate device receiving input at node 107 and furnishing output at node 108.
The input of the first inverter is connected to the output of the second inverter, and the output of the first inverter is connected to the input of the second inverter, thus forming a feedback latch structure. This latch structure provides the storage circuitry component of the memory cell 100.
Access to the storage circuitry component of the memory cell 100 is provided by a pair of NMOS devices 103 and 104 and associated conductors. The NMOS device 103 connects the output node 107 of the first inverter (and the input of the second inverter) to a first bit line 109 (BL) and to a word line 111 (WL). More specifically, the source and drain terminals of device 103 connect bit line 109 to the output of the first inverter; and the gate terminal of device 103 connects to word line 111. Similarly, a NMOS device 104 is connected to the output of the second inverter 108 (also the input of the first inverter), a second bit line 110 (BLB), and the word line 111.
The SRAM storage circuitry is capable of storing a value until a new value is presented but loses any stored value if power is removed. To illustrate, a high or positive value of the power supply on a node may be referred to as a logic level of “ONE,” and a low or negative value of the power supply on a node may be referred to as a logic level “ZERO.” If a logic level ONE is presented to the node 107 while a logic level ZERO is presented simultaneously to the node 108, and then those levels are removed, the storage cell 100 assumes a condition which may be considered to represent a logic state of ONE. Since the input of the first inverter is at logic level ZERO, the device 105 is enabled driving its output to logic level ONE; similarly, the second inverter drives its output to logic level ZERO. Therefore, even after initial logic levels presented to the storage circuitry are removed, the storage circuitry stores (or maintains) the logic state ONE. If, on the other hand, a logic level ZERO is presented to the node 107 and a logic level ONE is simultaneously presented to the node 108 and these levels are subsequently removed, the storage cell maintains a logic state ZERO.
The access circuitry allow the storage circuitry to be written or read. Writing the storage cell occurs when bit lines 109 and 110 are presented with opposite logic levels and the word line node 111 is presented with a logic level ONE. As described, to write a logic state of ONE into the storage circuitry, the bit line 109 is presented with a logic level ONE, the bit line 110 is presented with a logic level ZERO, while the word line 111 is presented with a logic level ONE. One the other hand, to write a logic state of ZERO into the storage circuitry, opposite values are presented on bit line 109 and bit line 110 while the word line 111 is furnished a logic value ONE.
In order to read the state of the cell 100, the bit lines 109 and 110 are both actively driven to logic level ONE and subsequently held weakly or let float at that logic level while word line 111 receives a logic level ONE. If the storage circuitry has a logic state of ONE, the bit line 109 remains at a logic level of ONE and the bit line 110 is driven down towards logic level ZERO through NMOS devices 104 and 102. However, if the storage circuitry has a logic state of ZERO, the bit line 109 is driven towards logic level ZERO through NMOS devices 103 and 101 while the bit line 110 remains at logic level ONE. Since the capacitance and associated charge on bit lines 109 and 110 are typically large while the NMOS and PMOS device sizes are typically made as small as possible, it may take a relatively long time for the particular bit line being driven to reach logic level ZERO. In order to improve the speed of the read operation, special circuitry (such as sense amplifier circuitry) may be employed as part of the output data control circuitry to detect small differences between the bit line voltages instead of the full voltages that typically represent logic levels ZERO or ONE.
The memory cell 100 represents an example of a prior art arrangement providing single cycle access to a memory cell.
The new type of memory storage device circuit disclosed in U.S. Pat. No. 6,574,130 can be used to construct a memory array that can be randomly accessed like an SRAM memory array yet is also nonvolatile or maintains state through power cycling.
In order to close the device 300, a potential difference or voltage is applied between the terminal 301 and a terminal to the attractor plate 302 and thus between the suspended layer 303 and the plate 302. The applied voltage is sufficiently high that field lines generated attract the suspended layer 303 towards the attractor plate 302 and the two eventually make electrical contact. Even after the voltage and corresponding field cease to exist, the layer 303 continues indefinitely to make contact with the attractor plate 302 due to atomic attraction forces (Van der Waals forces) and thus may be utilized to represent in a nonvolatile fashion the memory state of ZERO.
In order to open the switch 300 and produce a memory state of ONE, a potential difference or voltage is applied between the layer 303 and the release plate 304. The applied voltage is sufficiently high to generate field lines that attract the layer 303 back toward the release plate 304 to the suspended position illustrated in
The switch circuit schematic illustrated in
In this embodiment of the present invention, the X address decoder and buffers 517 receive input on the X address bus 511 and the clock signal lines 513 and furnish output on a first word line 506 (WL1) and a second word line 507 (WL2) to a first memory cell 501 and a second memory cell 519 for the purpose of accessing the memory cells during read or write operations. Although not shown here in order to maintain clarity, the X address decoder and buffers 517 may furnish additional signals (and include the necessary circuitry for accomplishing that purpose) not pertinent to the present invention but employed by those skilled in the art.
The Y address decoder and input/output data buffers 504 receive address signals on the Y address bus 512, clock signals on the clock signal lines 513, write data for a write operation on the input data lines 514, and read/write control signals on the read/write control lines 516. The Y address decoder 504 furnishes outputs on the column signal lines 505 (SL) and 518 (RL) to the first and second memory cells 501 and 519 for accessing the memory cells. The Y address decoder and input/output data buffers 504 furnishes output data on the lines 515 received as a result of a read operation on the lines 505 and 518. Although not shown here in order to maintain clarity, the Y address decoder 504 may input additional signals (and include the necessary circuitry for accomplishing that purpose) not pertinent to the present invention but employed by those skilled in the art.
The address signals on the X and Y address buses 511 and 512 when decoded uniquely identify at least one memory cell, for example, memory cell 501. The X address decoder 517 uses the decoded signals to present an appropriate voltage level on the first word line 506 to select memory cell 501 while holding the voltage level on the second word line 507 at an inactive or disabled level. The Y address decoder 504 presents appropriate voltage levels on the column signal lines 505 and 518 to cause the memory cell 501 to be read or written.
The memory cell 501 includes hybrid technology storage device 300 and access circuitry. 502 and 503 which may be NMOS semiconductor devices. The IN terminal 509 of the storage device 300 is connected to ground. The SN terminal at a node 508 is connected to the column line 505 through the source/drain of the NMOS access device 503. The RN terminal at a node 510 is connected to the column line 518 (RL) through the source/drain of the NMOS access device 502. The first word line 506 connects to the gate terminal of NMOS access device 502 and the gate terminal of the NMOS access device 503. When logic state ONE is presented on the first word line 506, a first electrical connection is enabled between the memory cell internal node 508 and the column signal line 505, and a second electrical connection is enabled between the memory cell internal node 510 and the column signal line 518. When logic state ZERO is presented on the word line 506, the first electrical connection and the second electrical connection between the memory cell internal nodes and the column signal lines are disabled.
Although, this example of
The triggering relationship between the clock edge 613 and the first rising edge of the word line 506 and the triggering relationship between second rising clock edge 614 and the first falling edge of the word line 506 are clearly illustrated. Subsequent word line accesses triggered during clock cycles t2, t3, and t4 are also illustrated as is the “no access” interval during cycle t5 on the word line. A voltage level Vw1 for the word line 506 represents an appropriate voltage level for the active state needed to guarantee the successful access of the memory cell 501. Although not shown, it should be understood that at times it may be desirable to use multiple word line voltage levels for the different access operations.
While writing a logic state ONE during clock period t1, an active logic state on the word line 506 electrically connects the internal node 508 to the column signal line 505 and the internal node 510 to the column signal line 518. The column signal line 505 is held inactive (at logic state ZERO or ground), while the column signal line 518 is driven to the active state (logic state ONE) in response to the trigger provided by the falling clock edge 613. An active state voltage level Vwrite1 on the line 518 is shown as an appropriate write voltage level to guarantee that the logic state ONE is successfully written. Since the voltage between the moveable layer joined to the terminal 509 and the internal node 508 is zero and the bias between the moveable layer and the internal node 510 is Vwrite1, the electrostatic forces maintain the storage switch device 501 in the open condition so that no electrical contact is made between the moveable layer and the node 508. This condition is assumed to denote a logic state ONE, a state which is held indefinitely in this embodiment even though power to the memory array is temporarily removed so long as the memory cell 501 is not re-written to a different state. Consequently, read, no access, and power-off operations may be performed with no loss of data after writing. Although non-volatility is a characteristic of this embodiment of the invention, it should be understood that it is not a requirement. At the end of the write operation and cycle t1, the word line 506 and the control signal line 505 are returned to their inactive voltage levels.
During clock cycle t2, the logic state ONE that was previously stored in the memory cell during clock cycle t1 is read from the memory cell 501. In clock cycle t2, the word line 506 is driven active as in cycle t1. In this embodiment, voltage levels for read and write accesses are shown as Vw1 while active; however these levels may be different as a result of design choice in alternate embodiments. Control signal line 518 is held inactive, while control signal line 505 is driven to the read voltage Vread in response to the trigger caused the second rising clock edge 614. The Vread potential is such that it allows a read operation while not allowing a write or accidental disturb. The second falling clock edge 615 triggers the removal of voltage providing hard drive to the control signal line 505 so that the line is no longer driven (or is weakly held) as well as triggering the word line 506 to go active. Since the memory cell 501 is in the open condition storing a logic state ONE, electrically connecting the internal node 508 to the control signal line 505 as a result of activating the word line 506 causes the Vread voltage level on the control signal line 505 to remain unchanged during the remainder of the clock cycle t2. This situation is interpreted by the Y address decoder and input/output data buffers 504 as a logic state ONE. At the end of the operation and cycle t2, the word line 506 and the control signal line 505 are returned to their inactive voltage levels.
During clock period t3, a logic state ZERO is written to the memory cell 501. To accomplish this, an active logic state is provided on the word line 506 to electrically connect the internal node 508 to the column signal line 505 and the internal node 510 to the column signal line 518. The column signal line 518 is held inactive, while the column signal line 505 is driven to the active write state (logic state ONE) in response to the trigger provided by clock edge 618. A voltage level Vwrite0 is illustrated as an appropriate level to guarantee that the write logic state ZERO operation is successful. Since the voltage between the moveable layer connected to terminal 509 and the internal node 510 is zero and the voltage between the moveable layer and the internal node 508 is Vwrite0, the electrostatic forces cause the storage switch device to close so that electrical contact between the layer 509 and the node 508 is made. This state may be taken to denote a logic state ZERO which in this embodiment is held indefinitely, even when power to the memory array is temporarily removed so long as the memory cell 501 is not re-written with a different value. Thus, read, no access, and power off operations may be performed with no loss of data after writing. At the end of the write operation and cycle t3, the word line 506 and the control signal line 505 are returned to their inactive voltage levels.
It should be noted that in this embodiment the voltage level Vread employed to read the storage device is less than the voltage level Vwrite0 used to write the device, but alternate electromechanical storage devices may be possible with different level requirements (e.g., Vread may less than or equal to Vwrite0). In fact, it should be noted that in the explanations regarding the embodiment, unique voltage levels are utilized for many of the operations; but one skilled in the art may decide that for simplicity similar voltages levels on some of the signals are desirable.
During clock cycle t4, the logic state ZERO previously stored during clock cycle t3 is read from memory cell 501. To accomplish this, the word line 506 is driven active as in cycles t1, t2, and t3. Control signal line 518 is held inactive, while control signal line 505 is driven to the read voltage level Vread in response to the trigger provided by the fourth rising clock edge 619. The fourth falling clock edge 620 then triggers the removal of the level driving the control signal line 505 so that the line is no longer driven hard (or floats). The clock edge 620 also triggers the word line 506 going active. Since the memory cell 501 is closed storing a logic state ZERO in which the node 508 is electrically connected to ground, electrically connecting the internal node 508 to the control signal line 505 as a result of the word line 506 going active causes the voltage level Vread on the control signal line 505 to be discharged through the NMOS access device 503 and the storage cell 300. This situation is interpreted by the Y address decoder input/output data buffers 504 as a logic state ZERO. At the end of the operation during cycle t4, the word line 506 and the control signal line 505 are returned to their inactive voltage levels.
During clock cycle t5, no access operation is performed. As may be seen, the word line 506, the control signal line 505, and the control signal line 518 are all held at their inactive states so that neither a read nor a write operation is performed on memory cell 501.
Although not discussed in detail, it will be appreciated by those skilled in the art that an erase operation may be accomplished in a manner identical to a write ONE operation since that operation returns a cell to an open condition. Thus, in order to erase a group of cells, all cells of that group are written to a logic ONE state (or a logic ZERO state if a different convention is used).
Understanding the operating characteristics of the memory array of the present invention illustrates various advantages which the array has over memory arrays of the prior art. In addition to providing non-volatile storage and small size, the present invention may significantly increase speed of operation of a memory array. For example, reading the cell described in
Reading the state of the memory cell of the present invention, on the other hand, requires only that a single one of the bit lines be driven to the read voltage, then the hard drive removed and the line sensed to detect the state without the delay of the prior art circuitry. This may significantly increase memory speed and does not demand the extra sensing circuitry of the prior art.
Although the present invention has been described in terms of a preferred embodiment, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow.
