Claims
- 1. An image processing apparatus, comprising:
- process means for image processing;
- computer control means having a memory storing therein a program for controlling said process means, for producing various control signals for the image processing on the basis of said program;
- means for generating clock pulses employed to execute the program of said computer control means; and
- means for dividing said clock pulses;
- wherein said computer control means receives the clock pulses divided by said dividing means in order to count said divided clock pulses, and controls a process sequence in accordance with the count.
- 2. An apparatus according to claim 1, wherein said computer control means determines an operational timing of said process means in accordance with the count.
- 3. An apparatus according to claim 1, further comprising input control means for controlling the input of said clock pulses divided into said computer control means.
- 4. An apparatus according to claim 3, wherein said input control means operates responsive to a predetermined signal from said computer control means.
- 5. An apparatus according to claim 4, wherein said input control means is a gate circuit.
- 6. An image processing apparatus comprising:
- process means for image processing;
- computer control means having a memory storing therein a program having instructions for controlling said process means, for producing control signals; and
- means for generating clock pulses employed to execute the program of said computer control means,
- wherein said computer control means processes one instruction in the program on the basis of predetermined clock pulses of said clock pulse generating means and includes timer means which produces a timer signal on the basis of counted pulses derived by frequency-dividing said clock pulses of said clock pulse generating means and said counted pulses having a frequency lower than that of the said clock pulses.
- 7. An apparatus according to claim 6, wherein said timer means counts the low frequency pulses by the program in said memory.
- 8. An apparatus according to claim 7, wherein said control signals are for controlling the image processing.
Priority Claims (3)
Number |
Date |
Country |
Kind |
52-64528 |
May 1977 |
JPX |
|
52-64529 |
May 1977 |
JPX |
|
52-64530 |
May 1977 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 07/512,537 filed Apr. 18, 1990, which was a continuation of application Ser. No. 07/291,365 filed Dec. 30, 1988, now abandoned, which was a continuation of application Ser. No. 07/193,145 filed May 5, 1988, now abandoned, which was a continuation of application Ser. No. 07/058,327 filed June 4, 1987, now abandoned, which was a division of application Ser. No. 06/771,302 filed Aug. 30, 1985, now U.S. Pat. No. 4,671,647, which was a division of Ser. No. 06/425,706 filed Sept. 28, 1982, now U.S. Pat. No. 4,557,587, which was a division of application Ser. No. 06/156,645 filed June 5, 1980, now U.S. Pat. No. 4,456,366, which was a continuation of application Ser. No. 05/910,831 filed May 30, 1978, now abandoned.
US Referenced Citations (5)
Non-Patent Literature Citations (1)
Entry |
Hubbard et al., IBM Technical Disclosure Bulletin, vol. 19, No. 3 (Aug. 1976) pp. 1818-1820. |
Divisions (4)
|
Number |
Date |
Country |
Parent |
512537 |
Apr 1990 |
|
Parent |
771302 |
Aug 1985 |
|
Parent |
425706 |
Sep 1982 |
|
Parent |
156645 |
Jun 1980 |
|
Continuations (4)
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Number |
Date |
Country |
Parent |
291365 |
Dec 1988 |
|
Parent |
193145 |
May 1988 |
|
Parent |
58327 |
Jun 1987 |
|
Parent |
910831 |
May 1978 |
|