1. Field of the Invention
The invention relates to an image processing apparatus, and in particular, to an image processing apparatus adapted in a field emission display (FED).
2. Description of the Related Art
Conventionally, a display is horizontally deposited, and the status is referred to as a horizontal mode featuring a longer horizontal edge and a shorter vertical edge. Some images such as a portrait may be cropped by a horizontally deposited display because its height exceeds the vertical boundary while the width is zoomed to fit the horizontal boundary. Nevertheless, the total portrait can be properly fit in a vertically deposited display without undesirable crops. A vertically deposited display, is gaining usage as it is particularly adaptable for portrait images.
Before an image signal is displayed on an image display system, an image file stored in a Synchronous Dynamic Random Access Memory (SDRAM) device is first processed by an image processing apparatus to generate a processed image file which is stored in the same SDRAM device. The sequence of image processing is shown as
When the image display system operates in vertical mode, the image processing apparatus may encounter difficulties while displaying the image signal. In a typical SDRAM device, data access for one same row is very efficient. Conversely, when consecutive rows are vertically accessed, the performance may significantly degrade. When the display is vertically deposited, the image processing apparatus must issue consecutive vertical data accesses to the SDRAM device. In this case, longer time is required to process the image file due to its physical inefficiency, and the display effect is deemed unsatisfactory as requirements for quality and performance are getting challenging nowadays. Therefore, it is desirable to propose an enhanced approach so that the processing time can be reduced while efficiency is increased.
The invention proposes an image processing apparatus and an image display system capable of reducing image processing time.
An exemplary embodiment of an image processing apparatus is provided, comprising a storage module, a processing module and an output module. The storage module stores an image file. The processing module performs a coordinate conversion on the image file based on a predetermined manner to generate a converted file, and stores the converted file in the storage module. The output module reads the converted file from the storage module and processes it to output an image signal.
Another embodiment is an image display system is also provided. The image display system comprises a conversion module, a storage module, a processing module, an output module and a display module. The conversion module converts a frame image into an image file. The storage module stores the image file. The processing module performs a coordinate conversion on the image file based on a predetermined manner to generate a converted file, and stores the converted file in the storage module. The output module reads the converted file from the storage module and processes it to output an image signal. The display module displays the image signal.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
As an example in
In one embodiment, the storage module 32 is an SDRAM device, and the storage unit 342 may be a Static Random Access Memory (SRAM) device.
The processing module 56 may divide the image file DIMG into a plurality of subsets, and perform the coordinate conversion sequentially on each of the subsets. Each of the subsets may comprise N columns, and the predetermined manner is a range from the first column to the Nth column of the subsets. The number and sizes of the subsets may be variable dependent on applications, whereby the performance of the storage module can be optimized for difference circumstances.
Additionally, the processing module 56 may further comprise a storage unit 562 for buffering a plurality of subsets read from the storage module 54, and the coordinate conversion is performed on the buffered subsets based on the predetermined manner. The storage unit 562 may be an SRAM device.
In the embodiments disclosed, performances of the image processing apparatus and image display system are increased by optimizing accesses to the storage module. Coordinates of the image file is converted by dividing into the image file a plurality of subsets and sequentially processing the conversion on each subset. Efficiency is thereby increased while time consumption is reduced.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Date | Country | Kind |
---|---|---|---|
096216654 | Oct 2007 | TW | national |