BRIEF DESCRIPTION OF DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 shows on the left a 4:3 resolution image and on the right a 16:9 panel displaying the image;
FIGS. 2A and 2B illustrate writing and reading of line buffers 10 and 12 during two consecutive line periods;
FIG. 3 illustrates an image display system according to embodiments of the invention;
FIG. 4 shows on the left a 4:3 resolution image with 1440 (dot) data items per line and on the right a 16:9 display with 960 dots per line;
FIG. 5 is a timing diagram for signals according to embodiments of the invention;
FIGS. 6A to 6G show at different clocks a buffer with only 360 memory units while 720 processed data items require storage;
FIG. 7 is another timing diagram for signals according to embodiments of the invention; and
FIG. 8 shows a display applicable with the invention.
DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 3 illustrates an image display system 100 according to embodiments of the invention, comprising a display 102, a buffer 106, a processing unit 104 and a display driver.
Display 102 comprises dots arrayed in rows and lines with each line therein comprising several dots.
Buffer 106 comprises a plurality of memory units, each capable of storing one data item to drive one dot on the display 102.
Processing unit 104 receives a video signal corresponding to, for example, image 110 in FIG. 3. Image 110 consists of original data items of original dots arrayed in lines and rows. The original data items are transmitted line by line to processing unit 104. To perform format transformation, picture resizing, or other image functions, processing unit 104 processes original data items in a line to generate processed data items. Based on required image function, the amount of processed data items in a line may or may not exceed that of original data items in a line. If display 102 has a line resolution higher than image 110, the processed data items may be generated by merging or sampling the original data items. The processed data items may be sequentially written to buffer 106.
Display driver 108 sequentially reads the processed data items stored in memory units of buffer 106 to drive corresponding dots in a corresponding line on display 102.
Buffer 106 in image display system 100 can be smaller than a conventional line buffer, such that the embodiments can deploy fewer memory units than the total number of processed data items in a line. Furthermore, the number of processed data items in a line can be twice or four times the number of memory units.
Hereinafter, a 4:3 resolution image with 1440 (dot) data items per line and a 16:9 display with 960 dots per line as illustrated in FIG. 4 are used as an illustrative, but not limitative, example to explain the timing of memory writing and reading. The central portion of the display with a width of 720 dots displays a zoomed 4:3 resolution image and the two frame borders beside the central portion show a constant color of black.
FIG. 5 is a timing diagram for signals according to embodiments of the invention. The signals shown in FIG. 5 are, from top to bottom, horizontal synchronization signal HSYNC, video signal Videos clock signal Clock1, output driving signal, and clock signal Clock2. Clock signals Clock1 and Clock2 are the same signal but have different marks thereon only for technical explanatory purposes. Horizontal synchronization signal HSYNC and video signal Video are generated according to a 4:3 resolution image and input into image display system 100. Horizontal synchronization signal HSYNC switches from low (a disserted condition) to high (an asserted condition), meaning that video signal Video is going to carry original data items for one line of a 4:3 resolution image. Thus, video signal Video, during the 1440 clocks of period TVO, sequentially sends 1440 original data items 128 to image display system 100.
As discussed, the line resolution difference between a 4:3 resolution image and a 16:9 display makes it impossible to drive display 102 directly using original data items 128. Original data items 128 must be processed to perform a zoom function and generate processed data items. Each line in the 4:3 resolution image has 1440 original data items while each line in the 16:9 display has 720 dots corresponding to the 1440 original data items, causing a dot ratio of 1440:720(=2:1). In other words, a processed data item for driving a dot in the 16:9 display is the combination result of two corresponding original data items from the 4:3 resolution image. The combination result may be selected from one of the two corresponding original data items, the average of the two corresponding original data items, or any result after similar manipulation. After processing, the 720 processed data items correspond to the 1440 original data items.
The S symbols in FIG. 5 show writing actions in which 720 processed data items are sequentially written to buffer 106 in the period TVO of 1440 clocks. As buffer 106 is written to once when receiving every two original data, one of every two clocks in clock signal Clock1 after time ts is marked with slashes to represent an effectively writing clock. It can be found in FIG. 5 that the writing rate of the processed data is one half of a processed data item per clock.
Display driver 108 sequentially reads the processed data items stored in buffer 106 to generate a driving signal for driving corresponding dots on display 102. To display a 4:3 resolution image on a 16:9 display, the driving signal includes not only the 720 processed data items 130, but also two sets of black data items for driving the dots inside two frame borders. Each set of the black data items has 120 black (dot) data items.
In FIG. 5, the end points of reading the 720 processed data items from buffer 106 and writing the 720 processed data items to buffer 106 are substantially the same. This arrangement results in the minimum size of buffer 106 being dramatically reduced.
The clocks with slashes in clock signal Clock2 represent effectively reading clocks, clocks when buffer 106 is read. As shown in FIG. 5, during period TVP starting from time tF, display driver 108 spends 720 clocks to read 720 processed data items in buffer 106. Therefore, the reading rate of the processed data items from buffer 106 is one per clock.
It can be derived from FIG. 5 that the size of buffer 106 need not be the same as that for storing all the processed data items. In fact, the size of buffer 106 need only be large enough to store all the processed data items generated during the time period from tS to tF. After time tF, since the reading rate exceeds the writing rate, newly generated processed data items can be stored in memory units that have been read. Namely, in a line period, memory units in a buffer can be repetitively written to or read. In the embodiment, there are 720 clocks between time tS and time tF, such that 360 processed data items will be generated therebetween. Therefore, buffer 106 only requires a minimum of 360 memory units, each storing one processed data item. The total number of the processed data items is 720, about twice the number of memory units, 360.
Even though FIG. 5 shows that writing and reading of buffer 106 end at exactly the same time, this condition is only illustrative. As is understood in the art, a processed data item must first be written to memory, and then it can be read. Therefore, the ending of writing a memory unit in buffer 106 must be at least one clock ahead of that of reading the memory unit. In the embodiments of the invention, if the ending of writing is 10 or fewer clocks ahead of that of reading, or there are fewer than 10 processed data items remain unread after the ending of writing, the writing and the reading end at substantially the same time.
FIGS. 6A to 6G show at different clocks a buffer 106 with only 360 memory units while there are totally 720 processed data items. Pointers R and W in FIGS. 6A-6G point at currently read and written memory units, respectively.
FIG. 6A shows that memory units M1-M359 have been written such that the 360th processed data item is currently written to memory unit M360. In the meantime, the 1st processed data item in memory unit M1 is read out. FIG. 6A also shows that reading the processed data items starts about the time when half of the processed data items have been written to the memory units.
The time of FIG. 6B is one clock behind that of FIG. 6A. Because the writing rate is one half of one processed data item per clock, there is no pointer W in FIG. 6B, implying there is no writing in this clock. Analogously, as the reading rate is one processed data item per clock, pointer R in FIG. 6B proceeds to point at memory unit M2, reading out the 2nd processed data item.
The time of FIG. 6C is one clock behind that of FIG. 6B. Pointer W reappears in FIG. 6C, pointing at memory unit M1. Since memory unit M1 has been read two clocks before and is currently idle, it can be recycled to store a newly generated processed data item, the 361st processed data item. As the reading rate is one processed data item per clock, pointer R in FIG. 6C further proceeds to point at memory unit M3 and read out the 3rd processed data item.
The time of FIG. 6D is one clock behind that of FIG. 6C, and is one clock ahead of that of FIG. 6E. It is comprehensible from FIGS. 6A to 6D that pointer R proceeds to a following memory unit every clock and pointer W does every two clocks.
Every time when pointer R/W points at the last memory unit, memory M360, pointer R/W restarts and points at the first memory unit, memory unit M1, in the next effectively reading/writing clock.
As shown in FIG. 6F, during the last effectively writing clock, the last processed data item, the 720th processed data item, is written to memory unit M360 while the 719th processed data item currently stored in memory unit M359 is read, as shown in FIG. 6F.
The time of FIG. 6G is one clock behind that of FIG. 6F, showing, during the last effectively reading clock, no pointer W, but pointer R pointing at memory unit M360 to read the 720th processed data item. FIGS. 6F and 6G also illustrate that the writing and the reading of buffer 106 end at substantially the same time since the endings thereof are only one clock apart.
As shown by FIGS. 5 and 6A-6G, buffer 106 needs only 360 memory units to store 720 processed data items.
The embodiment shown in FIGS. 5 and 6A-6G reads at twice a writing rate. The invention is also applicable when a reading rate is higher than, but not an integer-multiple of, the writing rate.
Similar to FIG. 5, FIG. 7 shows a timing diagram for signals according to embodiments of the invention. Unlike FIG. 5, two of every three clocks during period TVP starting from time TF are marked as effectively reading clocks. In other words, the reading rate is ⅔ processed data item per clock while the writing rate is ½ processed data item per clock. As there are 720 process data items required to read, period TVP lasts 1080(=720*3/2) clocks. It can be derived from FIG. 7 that 360(=1440−1080) clocks are between time tS and time tF, generating only 180(=360/2) processed data items each requiring an individual memory unit for storing. If solely following the time diagram in FIG. 7 where reading the processed data 130 starts about the time when a quarter of the processed data items have been written to memory units, the size of the buffer can be 180, a quarter of the number of the total processed data items, 720. To prevent the conflict when reading and writing are performed to the same memory unit, the ending of reading in FIG. 7 can be deferred until n clocks behind the ending of writing in FIG. 7, such that the buffer is required to have at least (180+n/2) memory units. As defined, if the ending of writing is 10 or less clocks ahead of that of reading, or there are less than 10 processed data items unread after the ending of writing, the writing and the reading end at substantially the same time.
In the disclosed embodiments, writing and reading end at substantially the same time, such that the buffer size can be a half or quarter of the number of the total processed data items.
As shown in FIGS. 5 and 7, the minimum size of a buffer is determined by the number of the processed data items generated during the time period from tS to tF. The narrower the time period from tS to tF, the smaller the size of the buffer. As shown in FIGS. 5 and 7, the locations of time tS and time tE are unchangeable because they are determined by input video signal Video. Reading rate can be slowed to lengthen period TVP, making tF closer to tS. However, if, in a line period, the time period outside period TVP is defined as period TBLANK, lengthening period TVP is equivalent to shortening period TBLANK. For a LCD display, period TBLANK must be sufficiently long such that dots in frame borders can be driven to show black and some driving preparations, such as pre-charging or VCOM inversion, can be made. Therefore, period TBLANK cannot be too short.
FIGS. 5 and 7 show embodiments wherein only one processed data item is read during one effectively reading clock. The invention is not limited thereto, but more than one processed data items can be read at a time during one effectively reading clock. FIG. 8 shows a display 300 applicable to the invention. Display 300 has scan lines S1-S5 and data lines D1-D10. One scan line crosses one data line to control a corresponding dot at about the cross area. Data lines D1-DL0 are not driven simultaneously. As shown in FIG. 8, three adjacent data lines are collectively named as a bank and three banks B1-B3 are shown in FIG. 8. Multiplexer 302 selects one of the banks such that the three data lines in the selected bank are simultaneously driven. For display 300 in FIG. 8, three processed data items need be simultaneously read during one effectively reading clock to drive three data lines.
The buffers in the embodiments of the invention can be smaller than the total number of the processed data items in a line, such as a half or quarter thereof. An image display system according to embodiments of the invention is less costly and thus more favorable in market behavior.
While the invention has been described by way of examples and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Application
20080030748
