Claims
- 1. An image processing system for semiconductor wafer inspection comprising:
a buffer memory array, for acquiring raw image data and processed image data; and a multiplicity of asynchronous symmetrical image processors connected to said buffer memory array, each of said asynchronous symmetrical image processors being a self-contained image processor for independently performing image cross-correlation and defect detection on image data from equivalent areas of different die on the wafer.
- 2. An image processing system as in claim 1 further comprising an image normalization engine connected to said buffer memory array, for normalizing image contrast and brightness so as to facilitate die to die image comparison as performed by said multiplicity of asynchronous symmetrical image processors.
- 3. An image processing system as in claim 1, wherein said buffer memory array is divided into three independently and simultaneously addressable memory blocks.
- 4. An image processing system as in claim 1, further comprising a multiplicity of parallel data channels connected to said buffer memory array, for delivering raw image data to said buffer memory array.
- 5. An image processing system as in claim 2, further comprising a histogram data link connected to said image normalization engine, for delivering raw image data to said image normalization engine.
- 6. An image processing system as in claim 5, wherein said image normalization engine comprises histogram tabulation engines connected to said histogram data link, for real-time generation of histograms of raw image data.
- 7. An image processing system as in claim 1, further comprising a defect map memory connected to said multiplicity of asynchronous symmetrical image processors, for storing a map of defects as identified by an algorithm programmed into said multiplicity of asynchronous symmetrical image processors.
- 8. An image processing system as in claim 1, further comprising a cross-correlation memory connected to said multiplicity of asynchronous symmetrical image processors, for storing pattern block offset data.
- 9. An inspection system for a semiconductor wafer patterned with an array of identical dies, comprising:
an array of modules, each module comprising a probe forming system and a detector, said array comprising a multiplicity of module rows, the array of die on the wafer being aligned with said module rows; a multiplicity of image processing systems; and a multiplicity of parallel data channels connecting said detectors with said processing systems.
- 10. An inspection system as in claim 9, wherein said probe forming system is a charged particle probe forming system.
- 11. An inspection system as in claim 10, wherein said charged particle probe forming system is an electron probe forming system.
- 12. An inspection system as in claim 10, wherein said detector is a secondary electron detector.
- 13. An inspection system as in claim 9, wherein there is one of said multiplicity of image processing systems dedicated to each of said module rows.
- 14. An inspection system as in claim 9, wherein one of said multiplicity of image processing systems comprises:
a buffer memory array, for acquiring raw image data from said modules and for acquiring processed image data; and a multiplicity of asynchronous symmetrical image processors connected to said buffer memory array, each of said asynchronous symmetrical image processors being a self-contained image processor for independently performing image cross-correlation and defect detection on image data from equivalent areas of different die on the wafer.
- 15. An inspection system as in claim 14, wherein one of said multiplicity of image processing systems further comprises an image normalization engine connected to said buffer memory array, for normalizing image contrast and brightness so as to facilitate die to die image comparison as performed by said multiplicity of asynchronous symmetrical image processors.
- 16. An inspection system as in claim 14 wherein said buffer memory array is divided into three independently and simultaneously addressable memory blocks.
- 17. An inspection system as in claim 15, further comprising a histogram data link connected to said image normalization engine, for delivering raw image data to said image normalization engine.
- 18. An inspection system as in claim 17, wherein said image normalization engine comprises histogram tabulation engines connected to said histogram data link, for real-time generation of histograms of raw image data.
- 19. An inspection system as in claim 9, further comprising an inspection image display module connected to said multiplicity of image processing systems.
- 20. A method for semiconductor wafer defect detection comprising the steps of:
acquiring raw image data from the wafer; simultaneous to said acquiring step, normalizing image data for contrast and brightness; and simultaneous to said acquiring and normalizing steps, performing cross-correlation and defect detection on normalized image data.
- 21. A method for defect detection as in claim 20, wherein said performing step is implemented by a multiplicity of asynchronous symmetrical image processors, operating in parallel.
- 22. A method for defect detection as in claim 20, wherein said acquiring, normalizing and performing steps all access a common buffer memory array.
- 23. A method for defect detection as in claim 22, wherein said buffer memory array is divided into three independently and simultaneously addressable memory blocks.
- 24. A method for defect detection as in claim 21, wherein said asynchronous 15 symmetrical image processors utilize a pattern block inspection sequence designed to minimize the time required to complete cross-correlation.
- 25. A method for defect detection as in claim 20, further comprising the step of taking data from a cross-correlation memory, simultaneous to said performing step, for establishing an efficient starting point for cross-correlation.
- 26. A method for semiconductor wafer defect detection, comprising the steps of:
(a) acquiring raw image data from the wafer into a first buffer memory block; (b) next, acquiring raw image data from the wafer into a second buffer memory block, and simultaneously normalizing data in said first buffer memory block; (c) next, acquiring raw data from the wafer into a third buffer memory block, simultaneously normalizing data in said second buffer memory block, and simultaneously performing cross-correlation and defect detection on image data accessed from said first buffer memory block; (d) next, acquiring raw data from the wafer into a first buffer memory block, simultaneously normalizing data in said third buffer memory block, and simultaneously performing cross-correlation and defect detection on image data accessed from said second buffer memory block; (e) next, acquiring raw data from the wafer into a second buffer memory block, simultaneously normalizing data in said first buffer memory block, and simultaneously performing cross-correlation and defect detection on image data accessed from said third buffer memory block; and (f) next, repeating steps (c) through (e) until all raw image data is acquired and processed.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application No. 60/285,390 filed Apr. 18, 2001.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60285390 |
Apr 2001 |
US |