Patent Application
20090152605
The priority application number JP2007-325635, Image Sensor, Dec. 18, 2007, Toshikazu Ohno, Tatsushi Ohyama, Mamoru Arimoto, Ryu Shimizu, JP2008-197220, Image Sensor, Jul. 31, 2008, Toshikazu Ohno, Yugo Nose, Ryu Shimizu, Mamoru Arimoto, Tatsushi Ohyama, upon which this patent application is based is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to an image sensor and a CMOS image sensor, and more particularly, it relates to an image sensor and a CMOS image sensor each comprising a charge increasing portion for increasing the number of signal charges.
2. Description of the Background Art
An image sensor (CMOS image sensor) comprising a charge increasing portion for increasing the number of signal charges is known in general.
In general, there is disclosed an image sensor (CMOS image sensor) comprising a photodiode portion for storing electrons generated by photoelectric conversion, having a photoelectric conversion function, a multiplier gate electrode applying an electric field for multiplying (increasing) electrons due to impact ionization by an electric field and a transfer gate electrode for transferring the electrons, provided between the photodiode portion and the multiplier gate electrode.
The conventional image sensor is suitable for a product employed under environment of small quantity of light such as a security camera and a dark field camera, and increase in the speed of a shutter is desirable in order to take a clearer image of an object moving fast.
An image sensor according to a first aspect of the present invention comprises a carrier generating portion having a photoelectric conversion function, a voltage conversion portion for converting signal charges to a voltage, a charge increasing portion for increasing carriers generated by the carrier generating portion and a light shielding film formed to cover at least one part of the charge increasing portion.
A CMOS image sensor according to a second aspect of the present invention comprises a carrier generating portion having a photoelectric conversion function, a voltage conversion portion for converting signal charges to a voltage, a charge increasing portion for increasing carriers generated by the carrier generating portion and a light shielding film formed to cover at least one part of the charge increasing portion, wherein at least the carrier generating portion, the voltage conversion portion and the charge increasing portion are included in a pixel.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
Embodiments of the present invention will be hereinafter described with reference to the drawings. Each of the following embodiments of the present invention is applied to an active CMOS image sensor employed as an exemplary image sensor.
A CMOS image sensor according to a first embodiment comprises an imaging portion 51 including a plurality of pixels 50 arranged in the form of a matrix, a row selection register 52 and a column selection register 53, as shown in
As to the sectional structure of the pixels 50 of the CMOS image sensor according to the first embodiment, element isolation regions 2 for isolating the pixels 50 from each other are formed on the surface of a p-type silicon substrate 1, as shown in
The photodiode portion 4 has a function of generating electrons in response to the quantity of incident light and storing the generated electrons. The photodiode portion 4 has a function of generating electrons in response to the quantity of incident light and storing the generated electrons. The photodiode portion 4 is formed to be adjacent to the corresponding element isolation region 2 as well as to the transfer channel 3. A p+-type impurity region 4a for suppressing occurrence of a dark current is formed on a surface of the photodiode portion 4 and a side surface of the photodiode portion 4 on a side contact with the element isolation region 2. Thus, the photodiode portion 4 is employed as a buried photodiode.
The floating diffusion region 5 has an impurity concentration (n+) higher than the impurity concentration (n−) of the transfer channel 3. The floating diffusion region 5 has a function of holding signal charges formed by transferred electrons and converting the signal charges to a voltage. The floating diffusion region 5 is formed to be adjacent to the corresponding element isolation region 2 as well as to the transfer channel 3. Thus, the floating diffusion region 5 is opposed to the photodiode portion 4 through the transfer channel 3.
A gate insulating film 6 is formed on an upper surface of the transfer channel 3. On prescribed regions of an upper surface of the gate insulating film 6, a transfer gate electrode 7, a multiplier gate electrode 8, transfer gate electrodes 9 and 10 and a read gate electrode 11 are formed in this order from the side of the photodiode portion 4 toward the side of the floating diffusion region 5. In other words, the transfer gate electrode 7 is formed to be adjacent to the photodiode portion 4. The transfer gate electrode 7 is formed between the photodiode portion 4 and the transfer gate electrode 8. The transfer gate electrode 9 is formed between the multiplier gate electrode 8 and the transfer gate electrode 10. The multiplier gate electrode 8 is formed on a side opposite to the read gate electrode 11 and the floating diffusion region 5 with respect to the transfer gate electrode 10. The read gate electrode 11 is formed between the transfer gate electrode 10 and the floating diffusion region 5. The read gate electrode 11 is formed to be adjacent to the floating diffusion region 5. The transfer gate electrode 7 is an example of the “first electrode” in the present invention. The multiplier gate electrode 8 is an example of the “second electrode” in the present invention, and the read gate electrode 11 is an example of the “third electrode” in the present invention. The transfer gate electrode 9 is an example of the “fourth electrode” in the present invention. The transfer gate electrode 10 is an example of the “fifth electrode” in the present invention.
As shown in
As shown in
When the ON-state (high-level) clock signal φ2 is supplied to the multiplier gate electrode 8, the portion (electron multiplying portion (charge accumulation well) 3b) of the transfer channel 3 located under the multiplier gate electrode 8 is controlled to the potential of about 25 V, so that a high electric field impact-ionizing electrons and multiplying (increasing) the number thereof is formed in the portion (electron multiplying portion 3b) of the transfer channel 3 located under the multiplier gate electrode 8. The impact ionization of the electrons is caused on the boundary between the portion (electron multiplying portion 3b) of the transfer channel 3 located under the multiplier gate electrode 8 and the portion of the transfer channel 3 located under the transfer gate electrode 9. The electron multiplying portion 3b is an example of the “charge increasing portion” in the present invention.
The portion of the transfer channel 3 located under the transfer gate electrode 7 has a function of transferring the electrons stored in the photodiode portion 4 to the electron multiplying portion 3b when the ON-state (high-level) clock signal φ1 is supplied to the transfer gate electrode 7, while functioning as a photodiode isolation barrier dividing the photodiode portion 4 and the electron multiplying portion 3b from each other when the OFF-state (low-level) clock signal φ1 is supplied to the transfer gate electrode 7.
The portion of the transfer channel 3 located under the transfer gate electrode 9 has a function of transferring the electrons stored in the electron storage portion 3a to the electron multiplying portion 3b and transferring the electrons stored in the electron multiplying portion 3b to the electron storage portion 3a when the ON-state (high-level) clock signal φ3 is supplied to the transfer gate electrode 9. When the OFF-state (low-level) clock signal φ3 is supplied to the transfer gate electrode 9, on the other hand, the portion of the transfer channel 3 located under the transfer gate electrode 9 functions as a charge transfer barrier dividing the electron storage portion 3a and the electron multiplying portion 3b from each other. In other words, the transfer gate electrode 9 is so supplied with the ON-state (high-level) clock signal φ3 that the electrons stored in the electron storage portion 3a can be transferred to the electron multiplying portion 3b and the electrons stored in the electron multiplying portion 3b can be transferred to the electron storage portion 3a.
The portion of the transfer channel 3 located under the read gate electrode 11 has a function of transferring the electrons stored in the electron storage portion 3a to the floating diffusion region 5 when the ON-state (high-level) clock signal φ5 is supplied to the read gate electrode 11, and a function of dividing the electron storage portion 3a and the floating diffusion region 5 from each other when the OFF-state (low-level) clock signal φ5 is supplied to the read gate electrode 11. In other words, the read gate electrode 11 is so supplied with the ON-state (high-level) clock signal φ5 that the electrons stored in the electron storage portion 3a can be transferred to the floating diffusion region 5.
According to the first embodiment, a light shielding film 26 made of metal such as Al for suppressing incidence of light, having openings 261 is so formed as to cover regions from surfaces of the transfer gate electrodes 7 (surfaces of the transfer gate electrodes 7 in the vicinities of ends of the transfer gate electrodes 7 on the sides of the photodiode portions 4) to surfaces of the element isolation regions 2, as shown in
As shown in
As shown in
A read operation of the CMOS image sensor according to the first embodiment will be now described with reference to
The reset gate transistor Tr of each pixel 50 forming a prescribed row is first brought into an ON-state to reset the potential of the signal line 25. Thereafter the reset pixel selection transistor Tr2 of each reset pixel 50 forming the prescribed row is brought into an ON-state to read a reset level signal to the correlated double sampling circuit 27. Then a high-level signal is supplied to the wire 24 of each reset pixel 50 forming the prescribed row, to bring the read gate electrode 11 of each pixel 50 forming the prescribed one row of the imaging portion 51 into an ON-state. Thus, electrons generated in the photodiode portion 4 of each pixel 50 forming the prescribed one row are read on the signal line 25. Then the pixel selection transistor Tr2 of each reset pixel 50 forming the prescribed row is brought into an ON-state from the this state to read a signal of the photodiode portion 4 on the correlated double sampling circuit 27 through the amplification transistor Tr1 and the pixel selection transistor Tr2. The correlated double sampling circuit 27 samples the both of the reset level signal and the signal of the photodiode portion 4 for performing an operation of subtraction, thereby outputting a signal after removing reset noise. Thereafter the column selection transistors are successively brought into ON-states to output signals of the corresponding respective pixels 50. The CMOS image sensor according to the first embodiment reads data by repeating this operation.
An electron transferring operation of the CMOS image sensor according to the first embodiment of the present invention will be described with reference to
In a period A shown in
In a period B shown in
In a period C shown in
In a period D shown in
An electron multiplying operation of the CMOS image sensor according to the first embodiment of the present invention will be described with reference to
In the electron multiplying operation after the transfer operation in the period C shown in
In a period F shown in
In a period G shown in
The CMOS image sensor performs the aforementioned electron transferring operation in the periods B and C shown in
The electrons are stored in the portion (electron multiplying portion 3b) of the transfer channel 3 located under the multiplier gate electrode 8 of each pixel 50 after completing the electron multiplying operation. Thereafter the electrons are read on the floating diffusion regions 5 every row of the pixels 50 arranged in the form of matrix. In other words, the electrons before reading are stored in the portion (electron multiplying portion 3b) of the transfer channel 3 located under the multiplier gate electrode 8, according to the first embodiment.
According to the first embodiment, as hereinabove described, the CMOS image sensor comprises the electron multiplying portions 3b for multiplying the electrons generated by the photodiode portions 4 and the light shielding film 26 formed to cover the surfaces of the electron multiplying portions 3b, whereby incidence of light upon the electron multiplying portions 3b can be suppressed during the electron multiplying operation, and hence influence of light incident upon the electron multiplying portion 3b (noise caused by electrons newly generated by photoelectric conversion) can be suppressed even when the time period of the electron multiplying operation is increased. Thus, it can take a long time to multiply electrons stored for a short imaging period, and hence the speed of a shutter can be increased while enhancing the sensitivity of the image sensor.
According to the first embodiment, as hereinabove described, the light shielding film 26 are formed to cover the region from the surfaces of the transfer gate electrodes 7 to surfaces of the floating diffusion regions 5 (element isolation region 2), whereby incidence of external light upon the electron multiplying portion 3b can be further suppressed during the electron multiplying operation, and hence noise caused by the external light incident upon the electron multiplying portion 3b can be further suppressed even when the time period of the electron multiplying operation can be increased.
According to the first embodiment, as hereinabove described, the floating diffusion regions 5 are provided on the plurality of the pixels 50 respectively and the light shielding film 26 is so formed as to cover the electron multiplying portions 3b provided on the plurality of the pixels 50 respectively, so that the CMOS image sensor can be formed.
According to the first embodiment, as hereinabove described, the CMOS image sensor is so formed as to store the electrons before being read on the floating diffusion regions 5 are stored in the electron multiplying portions 3b, whereby the light shielding film 26 covers the electron multiplying portions 3b, and hence noise caused by external light can be suppressed until the electrons are read on the floating diffusion regions 5. Thus, the electrons may not be reset every reading, and hence global shutter performing reset of the electrons stored in all of the pixels and start of storage of the electrons simultaneously can be achieved.
In a structure of a CMOS image sensor according to a second embodiment, transfer gate electrodes 7 are partially covered with a light shielding film 26a dissimilarly to the aforementioned first embodiment.
The CMOS image sensor according to the second embodiment is so formed that the light shielding film 26a made of metal such as Al for suppressing incidence of light is formed to cover a region from a partial surface of each transfer gate electrode 7 on a side of a corresponding multiplier gate electrode 8 to a surface of each of element isolation regions 2 as shown in
The remaining structure and operation of the CMOS image sensor according to the second embodiment are similar to the aforementioned first embodiment.
According to the second embodiment, as hereinabove described, the light shielding film 26a is so formed as to cover the region from the partial surface of each transfer gate electrode 7 on the side of the corresponding multiplier gate electrode 8 to the surface of each of element isolation regions 2, whereby the partial surface of each transfer gate electrode 7 does not block light and hence light can be obliquely incident upon the photodiode portion 4 from the side of the multiplier gate electrode 8. Thus, the sensitivity of the image sensor can be enhanced.
The remaining effects of the aforementioned second embodiment are similar to those of the aforementioned first embodiment.
In a CMOS image sensor according to a third embodiment, four layers of light shielding films 26, 26c, 26d and 26e are formed dissimilarly to the aforementioned first embodiment.
The CMOS image sensor according to the third embodiment is so arranged as to stack four layers of the light shielding films 26, 26c, 26d and 26e between transfer gate electrodes 7, multiplier gate electrodes 8, transfer gate electrodes 9 and 10 and read gate electrodes 11 and microlenses 28 in a vertical direction as shown in
According to the third embodiment, the openings of the light shielding film arranged on the upper portion among the four layers of the light shielding films 26 and 26c to 26e are formed to be larger than the openings of the light shielding film arranged on the lower portion among the four layers of the light shielding films 26 and 26c to 26e. In other words, the sizes of the openings 261e, 261d, 261c and 261 are increased in this order. Thus, incidence of light upon each electron multiplying portion 3b can be suppressed without blocking collection of light incident upon the light shielding film. The length of the light shielding film arranged on the upper portion among the four layers of the light shielding films 26 and 26c to 26e in the direction (along arrow X) along the electron transfer direction are formed to be smaller than that of the light shielding film arranged on the lower portion among the four layers of the light shielding films 26 and 26c to 26e in the direction (along arrow X) along the electron transfer direction.
The remaining structure and operation of the CMOS image sensor according to the third embodiment are similar to those of the CMOS image sensor according to the aforementioned first embodiment.
According to the third embodiment, as hereinabove described, the openings of the light shielding film arranged on the upper portion among the four layers of the light shielding films 26 and 26c to 26e are formed to be larger than the openings of the light shielding film arranged on the lower portion among the four layers of the light shielding films 26 and 26c to 26e, whereby the light shielding films do not block light incident through each microlens 28 and hence reduction in light condensing performance of each photodiode portion 4 can be suppressed.
The remaining effects of the third embodiment are similar to those of the aforementioned first embodiment.
In a CMOS image sensor according to a fourth embodiment with the structure of the CMOS image sensor according to the aforementioned third embodiment, the centers of microlenses 28 and the centers of photodiode portions 4 are so arranged as to deviate from each other.
In the CMOS image sensor according to the fourth embodiment, the center (centerline A-A) of the microlens 28 in each pixel 50 arranged on sides of ends of an imaging portion 51 (see
The remaining structure and operation of the CMOS image sensor according to the fourth embodiment are similar to those of the CMOS image sensor according to the aforementioned third embodiment.
The remaining effects of the fourth embodiment are similar to those of the aforementioned third embodiment.
In a structure of a CMOS image sensor according to a fifth embodiment, an electron multiplying operation is performed between photodiode portions 4 and portions of transfer channels 3 located under multiplier gate electrodes 8a through portions of the transfer channels 3 located under transfer gate electrodes 7 dissimilarly to the aforementioned first embodiment.
In the CMOS image sensor according to the fifth embodiment, element isolation regions 2 for isolating pixels 50 from each other are formed on a surface of a p-type silicon substrate 1, as shown in
A gate insulating film 6 is formed on an upper surface of the transfer channel 3. On prescribed regions of an upper surface of the gate insulating film 6, the transfer gate electrode 7, the multiplier gate electrode 8a, the read gate electrode 11 are formed in this order from a side of the photodiode portion 4 toward a side of the floating diffusion region 5. In other words, transfer gate electrode 7 is formed to be adjacent to the photodiode portion 4. The transfer gate electrode 7 is formed between the photodiode portion 4 and the multiplier gate electrode 8a. The read gate electrode 11 is formed to be adjacent to the floating diffusion region 5. The multiplier gate electrode 8a is an example of the “second electrode” in the present invention.
A gate length L1 of the multiplier gate electrode 8a in an electron transfer direction is formed to be larger than gate lengths L2 of the transfer gate electrode 7 and the read gate electrode 11. Thus, a larger number of electrons can be stored in a portion of the transfer channel 3 located under the multiplier gate electrode 8a dissimilarly to a case where the gate length L1 of the multiplier gate electrode 8a in the electron transfer direction and the gate lengths L2 of the transfer gate electrode 7 and the read gate electrode 11 are equal. The gate length L1 of the multiplier gate electrode 8a in the electron transfer direction and the gate lengths L2 of the transfer gate electrode 7 and the read gate electrode 11 may be equal.
According to the fifth embodiment, a light shielding film 26b made of metal such as Al for suppressing incidence of light is so formed as to cover regions from surfaces of the transfer gate electrodes 7 to surfaces of the element isolation regions 2, as shown in
The transfer gate electrode 7, the multiplier gate electrode 8a and the read gate electrode 11 are supplied with ON-state (high-level) clock signals, thereby applying voltages of about 2.9 V to the transfer gate electrode 7 and the read gate electrode 11 and applying a voltage of about 24 V to the multiplier gate electrode 8a. Thus, the portion of the transfer channel 3 located under the transfer gate electrode 7 and the portion of the transfer channel 3 located under the read gate electrode 11 are controlled to potentials of about 4 V. The portion of the transfer channel 3 located under the multiplier gate electrode 8a are controlled to a higher potential of about 25 V. The portion of the transfer channel 3 located under the transfer gate electrode 7, the portion of the transfer channel 3 located under the multiplier gate electrode 8a and the portion of the transfer channel 3 located under the read gate electrode 11 are controlled to potentials of about 1 V while supplying OFF-state (low-level) clock signals thereto. The photodiode portion 4 and the floating diffusion region 5 are controlled to potentials of about 3 V and about 5 V respectively.
When the ON-state (high-level) signal is supplied to the multiplier gate electrode 8a, the portion (electron multiplying portion 3c) of the transfer channel 3 located under the multiplier gate electrode 8 is controlled to the potential of about 25 V, so that a high electric field impact-ionizing electrons and multiplying (increasing) the number thereof is formed in the portion (electron multiplying portion 3c) of the transfer channel 3 located under the multiplier gate electrode 8a. The impact ionization of the electrons is caused on the boundary between the portion (electron multiplying portion 3c) of the transfer channel 3 located under the multiplier gate electrode 8 and the portion of the transfer channel 3 located under the transfer gate electrode 7. The electron multiplying portion 3c is an example of the “charge increasing portion” in the present invention.
The remaining structure of the CMOS image sensor according to the fifth embodiment is similar to that of the CMOS image sensor according to the aforementioned first embodiment.
An electron multiplying operation of the CMOS image sensor according to the fifth embodiment of the present invention will be described with reference to
As shown in
Then the transfer gate electrode 7 is brought into an ON-state while the multiplier gate electrode 8a is kept in an ON-state. In other words, the portion of the transfer channel 3 located under the transfer gate electrode 7 is controlled to a potential of about 4 V while controlling the portion of the transfer channel 3 located under the multiplier gate electrode 8a to a potential of about 25 V. Thus, electrons stored in the photodiode portion 4 are transferred to the portion, controlled to a higher potential (about 4 V) than the potential (about 3 V) of the photodiode portion 4, of the transfer channel 3 located under the transfer gate electrode 7, and the electrons transferred to the portion of the transfer channel 3 located under the transfer gate electrode 7 are transferred to the portion, controlled to a further higher potential (about 25 V) than a potential (about 4 V) of the portion of the transfer channel 3 located under the transfer gate electrode 7, of the transfer channel 3 located under the multiplier gate electrode 8a. At this time, the electrons transferred from the portion of the transfer channel 3 located under the transfer gate electrode 7 to the portion of the transfer channel 3 located under the multiplier gate electrode 8a obtain energy from the high electric field when moving through the boundary between the portions of the transfer channel 3 located under the transfer gate electrode 7 and the multiplier gate electrode 8a. Then the electrons having high energy collide with silicon atoms to generate electrons and holes (impact ionization). Thereafter the electrons generated by impact ionization are stored in the portion of the transfer channel 3 located under the multiplier gate electrode 8a by electric field.
A reverse transfer operation of the CMOS image sensor according to the fifth embodiment of the present invention will be now described with reference to
First, the transfer gate electrode 7 is kept in an ON-state and the multiplier gate electrode 8a is brought into an OFF-state. Thus, the portion of the transfer channel 3 located under the multiplier gate electrode 8a is controlled to a potential of about 1 V while controlling the portion of the transfer channel 3 located under the transfer gate electrode 7 to a potential of about 4 V as shown in
The effects of the fifth embodiment are similar to those of the aforementioned first embodiment.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
For example, while the three or five gate electrodes are provided in the one pixel of the image sensor in each of the aforementioned embodiments, the present invention is not restricted to this but the present invention may be applied to an image sensor provided with gate electrodes other than 3 or 5 gate electrodes so far as the image sensor performs the electron multiplying operation.
While the image sensor is formed on the p-type silicon substrate in each of the aforementioned embodiments, the present invention is not restricted to this but a p-type impurity diffusion region formed on an n-type silicon substrate may be employed as a substrate.
While the electrons are employed as carriers in each of the aforementioned embodiments, the present invention is not restricted to this but holes may alternatively be employed as the carriers by entirely reversing the conductivity type of the substrate impurity and the polarities of the applied voltages.
While the electron multiplying operation is formed between the photodiode portion and the floating diffusion region in each of the aforementioned embodiments, the present invention is not restricted to this but the photodiode portion 4 may be provided between the electron multiplying portion 3b and the floating diffusion region 5 as shown in
While the plurality of layers of light shielding films are formed from the four layers of light shielding film in each of the aforementioned third and fourth embodiments, the present invention is not restricted to this but a plurality of layers of light shielding films may be formed from the plurality of layers other than the four layers of light shielding films.
| Number | Date | Country | Kind |
|---|---|---|---|
| JP2007-325635 | Dec 2007 | JP | national |
| JP2008-197220 | Jul 2008 | JP | national |
