Patent Application
20100091155
This application claims the benefit under 35 U.S.C. §119 of Korean Patent Application No. 10-2008-0100576, filed Oct. 14, 2008, which is hereby incorporated by reference in its entirety.
The present disclosure relates to an image sensor and a method for manufacturing the same.
An image sensor is a semiconductor device for converting an optical image into an electric signal. The image sensor may be roughly classified into a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor (CIS).
During the fabrication of image sensors, a photodiode may be formed in a substrate using ion implantation. As the size of a photodiode is reduced for the purpose of increasing the number of pixels without increasing chip size, the area of a light receiving portion is also reduced, thereby resulting in a reduction in image quality.
Also, since a stack height does not reduce as much as the reduction in the area of the light receiving portion, the number of photons incident to the light receiving portion is also reduced due to diffraction of light called Airy disk.
As an alternative to overcome this limitation, an attempt of forming a photodiode using amorphous silicon (Si), or forming a readout circuitry in a silicon (Si) substrate using a method such as wafer-to-wafer bonding and forming a photodiode on and/or over the readout circuitry has been made (referred to as a “three-dimensional (3D) image sensor”). The photodiode is connected with the readout circuitry through a metal interconnection.
According to a related-art, a poor contact between a photodiode and an interconnection may occur, requiring a contact process between the photodiode and the interconnection. In this case, there is a limitation in that a dark current may increases according to the formation of the contact.
In addition, since both the source and the drain of the transfer transistor are heavily doped with N-type impurities in a related art, a charge sharing phenomenon occurs. When the charge sharing phenomenon occurs, the sensitivity of an output image is reduced and an image error may be generated. Also, because a photo charge does not readily move between the photodiode and the readout circuitry, a dark current is generated and/or saturation and sensitivity is reduced.
Embodiments provide an image sensor and a method for manufacturing the same, which capacitively connects an image sensing device to a readout circuitry.
Embodiments also provide an image sensor and a method for manufacturing the same, which can increase a fill factor and avoid a charge sharing phenomenon.
Embodiments also provide an image sensor that can minimize a dark current source and inhibit saturation reduction and sensitivity degradation by forming a smooth transfer path of photo charges between a photodiode and a readout circuit, and a method for manufacturing the same.
In one embodiment, an image sensor comprises: a readout circuitry in a first substrate; an interconnection over the first substrate and electrically connected to the readout circuitry; an insulating layer over the interconnection; an electrode on the insulating layer; and an image sensing device on the electrode.
In another embodiment, a method for manufacturing an image sensor comprises: forming a readout circuitry in a first substrate; forming an interconnection over the first substrate and electrically connected to the readout circuitry; forming an image sensing device at a second substrate; sequentially forming an electrode and an insulating layer on the image sensing device; and bonding the first substrate and the second substrate to contact the insulating layer with the first substrate.
In still another embodiment, a method for manufacturing an image sensor comprises: forming a readout circuitry in a first substrate; forming an interconnection over the first substrate, the interconnection being electrically connected to the readout circuitry; sequentially forming an insulating layer and an electrode over the interconnection, the electrode being separated from the interconnection by the insulating layer; forming an image sensing device at a second substrate; and bonding the first substrate and the second substrate to contact the electrode with image sensing device.
The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.
Hereinafter, embodiments of an image sensor and a method for manufacturing the same will be described with reference to the accompanying drawings.
In the description of embodiments, it will be understood that when a layer (or film) is referred to as being ‘on’ another layer or substrate, it can be directly on another layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being ‘under’ another layer, it can be directly under another layer, or one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being ‘between’ two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
An image sensor according to an embodiment may include: a first substrate 100 having readout circuitry (not shown); an interconnection 150 over the first substrate 100 and electrically connected to the readout circuitry; an insulating layer 230 over the interconnection 150; an electrode 220 on the insulating layer 230; and an image sensing device 210 on the electrode 220.
The image sensing device 210 may be a photodiode, but, without being limited thereto, may be a photogate, or a combination of the photodiode and the photogate. In this embodiment, it will be described as an example that the photodiode is formed in a crystalline semiconductor layer. However, embodiments are not limited thereto. For example, the photodiode may be formed in an amorphous semiconductor layer.
Unexplained reference numerals in
Hereinafter, a method for manufacturing an image sensor according to a first embodiment will be described with reference to
As shown in
Next, as shown in
Next, as shown in
As shown in
As shown in
The method for manufacturing an image sensor may include forming an electrical junction region 140 in the first substrate 100, and forming a first conductive type connection 147 connected to the interconnection 150 at an upper part of the electrical junction region 140.
For example, the electrical junction region 140 may be a P-N junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive type ion implantation layer 143 formed on a second conductive type well 141 or a second conductive type epitaxial layer, and a second conductive type ion implantation layer 145 formed on the first conductive type ion implantation layer 143. For example, as shown in
According to an embodiment, the device is designed to provide a potential difference between the source and drain of the transfer transistor (Tx), thus implementing the full dumping of a photo charge. Accordingly, a photo charge generated in the photodiode is dumped to the floating diffusion region, thereby increasing the output image sensitivity.
That is, referring to
Thus, unlike the related art case of connecting a photodiode simply to an N+ junction, the embodiment makes it possible to inhibit saturation reduction and sensitivity degradation.
Thereafter, a first conductive type connection 147 is formed between the photodiode and the readout circuit to create a smooth transfer path of a photo charge, thereby making it possible to minimize a dark current source and inhibit saturation reduction and sensitivity degradation.
To this end, the first embodiment may form a first conductive type connection 147 for an ohmic contact on the surface of the P0/N−/P− junction 140. The N+ region (147) may be formed such that it pierces the PO region (145) to contact the N− region (143).
The width of the first conductive type connection 147 may be minimized to inhibit the first conductive type connection 147 from being a leakage source. To this end, the embodiment may perform plug implant after etching a contact hole for a first metal contact 151a, but embodiments are not limited thereto. For example, an ion implantation pattern (not shown) may be formed by another method, and the ion implantation pattern may be used as an ion implantation mask to form the first conductive type connection 147.
That is, a reason why an N+ doping is performed only on a contact formation region is to minimize a dark signal and help the smooth formation of an ohmic contact. If the entire Tx source region is N+ doped like the related art, a dark signal may increase due to an Si surface dangling bond.
An interlayer dielectric 160 may be formed on the first substrate 100, and an interconnection 150 may be formed. The interconnection 150 may include the first metal contact 151a, a first metal 151, a second metal 152, and a third metal 153, but embodiments are not limited thereto.
Next, as shown in
Next, as shown in
Next, as shown in
Thereafter, the P+ layer 216 at an upper part of the chip is connected to a ground line through a subsequent process.
Referring to
In this case, the height of a transistor in the readout circuitry of the first substrate 100 may be five to fifteen times a distance between the interconnection 150 and the electrode 220 (e.g., the thickness of the insulating layer therebetween), enabling effective delivery of the voltage change according to electrons generated by light to the readout circuitry 120.
According to embodiments of the image sensor and the method for manufacturing the same, the image sensing device at an upper part of the chip and the readout circuitry of the silicon substrate may be connected using a capacitive coupling (i.e. capacitance), omitting a contact process between the image sensing device at an upper part of the chip and the interconnection. Accordingly, the manufacturing process of a 3D image sensor can be simplified, and an increase of a dark current due to formation of a contact may be inhibited.
A method for manufacturing an image sensor according to a second embodiment may adopt the technical features of the first embodiment.
Different features from the first embodiment will be described below.
In the method for manufacturing an image sensor according to the second embodiment unlike the first embodiment, an insulating layer 230 and an electrode 220 may be sequentially formed on the interconnection 150 instead of on the second substrate 200.
The image sensing device 210 may be formed on the second substrate 200, and the first substrate 100 and the second substrate 200 may be bonded to each other so that the electrode 220 may contact the image sensing device 210.
Subsequent processes may adopt the technical features of the first embodiment.
According to the image sensor and the method for manufacturing the same of the second embodiment, the image sensing device at an upper part of the chip and the readout circuitry of the silicon substrate may be connected using a capacitance, omitting a contact process between the image sensing device at an upper part of the chip and the interconnection. Accordingly, the manufacturing process of a 3D image sensor can be simplified, and an increase of a dark current due to formation of a contact may be inhibited.
Similarly to the first embodiment, an image sensor according to the third embodiment may include: a readout circuitry in a first substrate; an interconnection over the first substrate and electrically connected to the readout circuitry; an insulating layer over the interconnection; an electrode on the insulating layer; and an image sensing device on the electrode.
The third embodiment may adopt the technical features of the first embodiment and the second embodiment.
Different from the structure shown in
The N+ connection region 148 may be formed at the P0/N−/P− junction 140 for an ohmic contact. In a process of forming an N+ connection region and a first metal contact 151a, a leakage source may occur. This is because an electric field (EF) may be generated over the Si surface due to operation while a reverse bias is applied to P0/N−/P− junction 140. A crystal defect generated during the contact forming process inside the electric field may become a leakage source.
Also, when the N+ connection region (see reference 147 of
Therefore, the third embodiment proposes a layout in which the first contact plug 151a is formed in an active region not doped with a PO layer but including N+ connection region 148 that is connected to N-junction 143.
According to the third embodiment, the electric field is not generated on and/or over the Si surface, thereby contributing to reduction in a dark current of a 3-D integrated CIS.
Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments.
Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2008-0100576 | Oct 2008 | KR | national |
