BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, wherein like reference numerals designate corresponding parts in the various drawings, and wherein:
FIGS. 1-8 are schematic cross-sectional views of an image sensor during various stages of a fabrication process according to an embodiment of the present invention.
FIGS. 9-17 are schematic cross-sectional views of an image sensor during various stages of a fabrication process according to an embodiment of the present invention.
FIG. 18 illustrates a further embodiment of an image sensor.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments may be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those who are skilled in the art. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail to avoid the unclear interpretation of the example embodiments. Throughout the specification, like reference numerals in the drawings denote like elements.
It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it may be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there may be no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.
Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Example embodiments may be described herein with reference to cross-section illustrations that may be schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the example embodiments.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
A method of forming an image sensor according to a first embodiment will be described. Then, other embodiments of the present invention will be similarly described.
FIGS. 1-8 are schematic cross-sectional views of an image sensor during various stages of a fabrication process according to an embodiment of the present invention. As shown in FIG. 1, a shallow trench isolation region 3 is formed in a substrate 1 (e.g., a silicon (Si) substrate) to isolate active regions of the substrate 1. A gate structure 8 is formed over the active region, and includes a gate insulator 5 (e.g., formed of silicon dioxide (SiO2)) and a conductive gate 7. The conductive gate 7 may be formed of polysilicon. The patterning process used to form the gate structure is well-known and will not be described in detail. A doping operation takes place to form a photodiode PD in the semiconductor substrate 1 on one side of the gate structure 8. The photodiode PD includes a N-type layer 9 and a P-type layer 11. The photodiode PD converts light incident thereon into an electric potential. As such, the photodiode PD is a photoactive region of the substrate 1. The gate structure 8 functions to selectively transfer the electric potential of the photodiode PD to a drain 13. The drain 13 may be an N-type doped region of the substrate 1. The drain 13 may be formed by doping during formation of the N-type layer 9.
As further shown in FIG. 1, an interlayer dielectric (ILD) 15 is formed over the substrate 1. The ILD 15 may be formed from SiO2, for example. A contact hole is formed in the ILD 15 to expose the drain 13, and the contact hole is filled with a conductive material to create a conductive plug 17. The conductive material may be tungsten, for example.
Next, as shown in FIG. 2, a photo resist pattern 19 is formed over the ILD 15 and patterned. The photo resist pattern 19 serves as an etching mask for a subsequent etching step shown in FIG. 3. In particular, the photo resist pattern 19 leaves a portion of the ILD 15 over the photodiode PD exposed.
Referring to FIG. 3, the ILD 15 is isotropically etched to form a concavity 15c in an upper surface of the ILD 15. Namely, the upper surface of the ILD 15 has a concave portion 15c over the photodiode PD. For example, the isotropic etching may be carried out by wet-etching the ILD 15 using a hydroflourine (HF) based etchant. In this example, the etchant has selectivity such that the photo resist pattern 19 is not attacked. The etch time and etch rate of the etchant may be controlled to achieve a desired radius of curvature for the concavity; and therefore, are a matter of design choice. After etching, the photo resist pattern 19 is removed.
As shown in FIG. 4, an insulating material is formed over the substrate to form an inner lens 21a and an etch stop layer 21b. The inner lens 21a fills the concavity 15c. The etch stop layer 21b covers the inner lens 21a and the ILD 15. Namely, the etch stop layer 21b extends over the ILD 15. In one embodiment the insulating material forming the inner lens 21a and the etch stop layer 21b may be silicon nitride (SiN). However, the lens 21a and/or etch stop layer 21b may be formed of any insulating material such that the refractive indices of the lens 21a and the etch stop layer 21b are higher than the ILD 15. Also, optionally, a planarization process may be performed to planarize the etch stop layer 21b. In one embodiment, the etch stop layer 21b has a thickness of 500 angstroms.
Next, as shown in FIGS. 5 and 6, a dual damascene process may be performed. Referring to FIG. 5, a first inter metal dielectric (IMD) 23 is formed over the etch stop layer 21b. A photo resist pattern (not shown) is formed over the first IMD 23 exposing portions of the first IMD 23 on either side of the inner lens 21a. One of the exposed portions is disposed over the conductive plug 17. Using the photo resist pattern as an etch mask, the first IMD 23 and the etch stop layer 21b are etched to expose the conductive plug 17 on one side of the inner lens 21a and the ILD 15 on the other side of the inner lens 21a.
A first metal interconnect 28a and a second metal interconnect 28b are formed in the vias created by the etching of the first IMD 23 and the etch stop layer 21b. The first and second metal interconnects 28a and 28b include a barrier metal layer 25 and a metal layer 27. The barrier metal layer 25 may include titanium (Ti), tantalum (Ta), etc. The metal layer 27 may include copper (Cu). By planarizing (e.g., chemical mechanical polishing), the first and second metal interconnects 28a and 28b do not extend over the first IMD 23.
Still referring to FIG. 5, a first barrier layer 29 is formed over the substrate 1 to cover the first IMD 23 and the first and second metal interconnects 28a and 28b. The first barrier layer 29 may be silicon nitride (SiN). Then, a second IMD 31 is formed over the first barrier layer 29. The second IMD 31 may be formed from the same material as the first IMD 23; for example, silicon dioxide (SiO2), or a different material. A second barrier layer 33 and a third IMD 35 are subsequently formed. The second barrier layer 33 may be formed from the same material as the first barrier layer 29; for example, silicon nitride, or may be formed of a different material. The third IMD 35 may be formed of the same material as the first and/or second IMDs 23 and 31; for example, silicon dioxide, or may be formed of a different material.
Referring to FIG. 6, as part of the dual damascene process, a via is formed through the layers 35, 33, 31 and 29 to expose the first metal interconnect 28a and form a third metal interconnect 40 in the via. For example, the via may be formed in a same manner as the other vias described above; namely, by etching using a photo resist pattern as an etch mask. The third metal interconnect 40 includes a barrier metal layer 37 and a metal layer 39. The barrier metal layer 37 may include titanium (Ti), tantalum (Ta), etc. The metal layer 39 may include copper (Cu). By planarizing (e.g., chemical mechanical polishing), the third metal interconnect 40 does not extend over the third IMD 35.
Still referring to FIG. 6, a passivation layer 44 is formed over the substrate 1 covering the third IMD 35 and the third metal interconnect 40. The passivation layer 44 may include one or more insulation layers. In the example of FIG. 6, the passivation layer 44 includes a silicon dioxide insulation layer 41 and a silicon nitride insulation layer 43. A photo resist pattern 45 is formed over the passivation layer 44 to expose a portion of the passivation layer 44 over the photodiode PD.
As shown in FIG. 7, using the photo resist pattern 45 as an etch mask, a two stage etching process is carried out to form a cavity 47 over the inner lens 21a. The first stage involves etching using an etchant with low etch selectivity such that the layers 43, 41, 35, 33, 31 and 29 are etched. After the first barrier layer 29 has been etched, the second stage is carried out by etching using an etchant with high selectivity between the material of the first IMD 23 and the material of the etch stop layer 21b. Accordingly, the first IMD 23 is etched, but the etch stop layer 21b is not substantially etched. The resulting cavity 47 extends from the passivation layer 44 to the etch stop layer 21b. By controlling the timing of the etching with the low selectivity etchant, the layers 43, 41, 35, 33, 31 and 29 may be etched away with out completely etching away the first IMD 23.
As shown in FIG. 8, a lower planarization layer 49 may then be formed in the cavity 47 and over the passivation layer 44, after removing the photo resist pattern 45. The lower planarization layer 49 may be formed of resin, and planarized through chemical mechanical polishing. A color filter layer 51, usually of resin, is formed over the low planarization layer 49. Then, an upper planarization layer 53 is formed over the color filter layer 51. The upper planarization layer 53 may be formed of resin, and planarized through chemical mechanical polishing. In one embodiment the upper and lower planarization layers 49 and 53 are formed of a same resin.
FIG. 8 further shows that a micro lens 55 may be formed on the upper planarization layer 53. The micro lens 55 may be formed according to any well-known technique and may be formed of any well-known material. As shown, the micro lens 55 serves to focus incident light rays LE on the photodiode PD. However, the focal point FP of the light rays LE, as focused by the micro lens 55, is well above the photodiode PD. As a result, absent the inner lens 21a, the light rays LE would fall on areas of the image sensor outside the intended photodiode PD as shown by the dashed lines LE′. However, the inner lens 21a serves to further direct the light rays LE to the photodiode PD and reduce and/or prevent this optical cross-talk.
Next, a second embodiment will be described with respect to FIGS. 9-16. FIGS. 9-16 are schematic cross-sectional views of an image sensor during various stages of a fabrication process according to another embodiment of the present invention. FIG. 9 shows the same process as shown in FIG. 1, and therefore this description will not be repeated. As shown in FIG. 10, after the process of FIG. 9, a first barrier layer 22 is formed over the substrate 1 covering the ILD 15 and the conductive plug 17. The first barrier layer 22 may be formed of silicon nitride.
Next, as shown in FIGS. 11-15, a dual damascene process may be performed. Referring to FIG. 11, a first inter metal dielectric (IMD) 23 is formed over the barrier layer 22. A photo resist pattern (not shown) is formed over the first IMD 23 exposing portions of the first IMD 23 on either side of the photodiode PD. One of the exposed portions is disposed over the conductive plug 17. Using the photo resist pattern as an etch mask, the first IMD 23 and the first barrier layer 22 are etched to expose the conductive plug 15 on one side of the photodiode PD and the ILD 15 on the other side of the photodiode PD.
A first metal interconnect 28a and a second metal interconnect 28b are formed in the vias created by the etching of the first IMD 23 and the first barrier layer 22. The first and second metal interconnects 28a and 28b include a barrier metal layer 25 and a metal layer 27. The barrier metal layer 25 may include titanium (i), tantalum (Ta), etc. The metal layer 27 may include copper (Cu). By planarizing (e.g., chemical mechanical polishing), the first and second metal interconnects 28a and 28b do not extend over the first IMD 23.
Next, as shown in FIG. 12, a photo resist pattern 20 is formed over the substrate 1 and patterned. The photo resist pattern 20 serves as an etching mask for a subsequent etching step shown in FIG. 13. In particular, the photo resist pattern 20 leaves a portion of the IMD 23 over the photodiode PD exposed.
Referring to FIG. 13, the IMD 23 is isotropically etched to form a concavity 18c in an upper surface of the IMD 23. Namely, the upper surface of the IMD 23 has a concave portion 18c over the photodiode PD. For example, the isotropic etching may be carried out by wet-etching the IMD 23 using a hydroflourine (HF) based etchant. In this example, the etchant has selectivity such that the photo resist pattern 20 is not attacked. The etch time and etch rate of the etchant may be controlled to achieve a desired radius of curvature for the concavity; and therefore, are a matter of design choice. After etching, the photo resist pattern 20 is removed.
As shown in FIG. 14, an insulating material is formed over the substrate to form an inner lens 24a and an etch stop layer 24b. The inner lens 24a fills the concavity 18c. The etch stop layer 24b covers the inner lens 24a, the IMD 23, and the first and second metal interconnects 28a and 28b. Namely, the etch stop layer 24b extends over the IMD 23. In one embodiment the insulating material forming the inner lens 24a and the etch stop layer 24b may be silicon nitride (SiN). However, the lens 24a and/or etch stop layer 24b may be formed of any insulating material such that the refractive indices of the lens 24a and the etch stop layer 24b are higher than the IMD 23. Also, optionally, a planarization process may be performed to planarize the etch stop layer 24b. In one embodiment, the etch stop layer 24b has a thickness of 500 angstroms.
Referring to FIG. 15, a second IMD 31 is formed over the etch stop layer 24b. The second IMD 31 may be formed from the same material as the first IMD 23; for example, silicon dioxide (SiO2), or a different material. A second barrier layer 33 and a third IMD 35 are subsequently formed. The second barrier layer 33 may be formed from the same material as the first barrier layer 22; for example, silicon nitride, or may be formed of a different material. The third IMD 35 may be formed of the same material as the first and/or second IMDs 23 and 31; for example, silicon dioxide, or may be formed of a different material.
Still referring to FIG. 15, as part of the dual damascene process, a via is formed through the layers 35, 33, 31 and 24b to expose the first metal interconnect 28a and a third metal interconnect 40 is formed in the via. For example, the via may be formed in a same manner as the other vias described above; namely, by etching using a photo resist pattern as an etch mask. The third metal interconnect 40 includes a barrier metal layer 37 and a metal layer 39. The barrier metal layer 37 may include titanium (Ti), tantalum (Ta), etc. The metal layer 39 may include copper (Cu). By planarizing (e.g., chemical mechanical polishing), the third metal interconnect 40 does not extend over the third IMD 35.
Still referring to FIG. 15, a passivation layer 44 is formed over the substrate 1 covering the third IMD 35 and the third metal interconnect 40. The passivation layer 44 may include one or more insulation layers. In the example of FIG. 15, the passivation layer 44 includes a silicon dioxide insulation layer 41 and a silicon nitride insulation layer 43. A photo resist pattern 45 is formed over the passivation layer 44 to expose a portion of the passivation layer 44 over the photodiode PD.
As shown in FIG. 16, using the photo resist pattern 45 as an etch mask, a two stage etching process is carried out to form a cavity 47 over the inner lens 24a. The first stage involves etching using an etchant with low etch selectivity such that the layers 43, 41, 35, and 33 are etched. After the second barrier layer 33 has been etched, the second stage is carried out by etching using an etchant with high selectivity between the material of the second IMD 31 and the material of the etch stop layer 24b. Accordingly, the second IMD 31 is etched, but the etch stop layer 24b is not substantially etched. The resulting cavity 47 extends from the passivation layer 44 to the etch stop layer 24b. By controlling the timing of the etching with the low selectivity etchant, the layers 43, 41, 35, and 33 may be etched away with out completely etching away the second IMD 31.
As shown in FIG. 17, a lower planarization layer 49 may then be formed in the cavity 47 and over the passivation layer 44, after removing the photo resist pattern 45. The lower planarization layer 49 may be formed of resin, and planarized through chemical mechanical polishing. A color filter layer 51, usually of resin, is formed over the low planarization layer 49. Then, an upper planarization layer 53 is formed over the color filter layer 51. The upper planarization layer 53 may be formed of resin, and planarized through chemical mechanical polishing. In one embodiment the upper and lower planarization layers 49 and 53 are formed of a same resin.
FIG. 17 further shows that a micro lens 55 may be formed on the upper planarization layer 53. The micro lens 55 may be formed according to any well-known technique and may be formed of any well-known material. As will be appreciated, this embodiment achieves similar advantages to those described above with respect to the first embodiment.
It will be appreciated from the above described embodiments, that the inner lens is not limited to being formed in the ILD 15 or the first IMD 23. Instead, the inner lens may be formed in other layers. As yet another example, FIG. 18 shows an inner lens 32a formed in the second IMD 31. Because the process steps for forming the inner lens 32a and an etch stop layer 32b in the second IMD 31 are readily apparent from the descriptions of the first and second embodiment, a detailed description of these process steps will be omitted for the sake of brevity.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the invention, and all such modifications are intended to be included within the scope of the invention.
Patent Application
20080042177
