Patent Application
20200295076
This Application claims priority of Taiwan Patent Application No. 108108604, filed on Mar. 14, 2019, the entirety of which is incorporated by reference herein.
The present disclosure relates to an image sensor, and in particular, to an image sensor that can reduce blooming and electrical crosstalk.
In semiconductor technology, an image sensor is used to sense light irradiated onto a semiconductor substrate. Conventional image sensors such as the complementary metal oxide semiconductor (CMOS) image sensor and the charge coupled device (CCD) image sensor are widely used in electronic devices such as digital cameras for capturing images or recording video.
An image sensor has a plurality of pixels. When the light is irradiated on the pixels of the image sensor, the electrons are excited in the image sensor, and the electrons accumulate in the photodiode (PD) of the pixel. Specifically, electrons accumulate in the capacitance formed by the photodiode. However, if the excited electrons are close to the edge of the pixel, the electrons may cross to another pixel and accumulate in the photodiode of the other pixel. This phenomenon is called electrical crosstalk. In addition, if the electrons that have accumulated in the photodiode of the pixel exceed the amount that the photodiode is able to accumulate (i.e., the amount of electrons that the photodiode can store, also known as the full well capacity), the electrons will also cross to other pixels. This phenomenon is called blooming. The electrical crosstalk and the blooming can affect the image displayed by an electronic device (e.g., a digital camera).
In order to prevent blooming, an overflow gate or a surface overflow drain may be formed in some image sensors. However, the overflow gate or the surface overflow drain may reduce the full well capacity of the image sensor, without improving the electrical crosstalk. Therefore, in the present technology, a vertical overflow drain (VOD) is formed in the image sensor to drive out excess electrons (or absorb excess electrons), thereby preventing electrical crosstalk and blooming. However, the vertical overflow drain usually sacrifices the quantum efficiency (QE) of the image sensor and does not completely improve the blooming. Therefore, an image sensor having a new structure is required.
The present disclosure provides an image sensor. The image sensor includes a semiconductor substrate, a first annular doped area, a second annular doped area, an annular isolation area, a photoelectric conversion area, a voltage conversion area, and a gate structure. The first annular doped area is disposed in the semiconductor substrate, wherein the first annular doped area comprises a first type dopant. The second annular doped area is disposed in the semiconductor substrate and over the first annular doped area, the second annular doped region comprises a second type dopant. The annular isolation area is disposed in the semiconductor substrate and over the second annular doped area. The photoelectric conversion area is disposed in the semiconductor substrate surrounded by the annular isolation area. The voltage conversion area is disposed in the semiconductor substrate surrounded by the annular isolation area. The gate structure is disposed on the semiconductor substrate.
The present disclosure provides a method of manufacturing an image sensor. The method includes forming a first annular doped area in a semiconductor substrate, the first annular doped area comprises a first type dopant; forming a second annular doped area in the semiconductor substrate, the second annular doped area comprises a second type dopant; forming an annular isolation area in the semiconductor substrate; forming a gate structure on the semiconductor substrate; forming a photoelectric conversion area in the semiconductor substrate; and forming a voltage conversion area in the semiconductor substrate, wherein the photoelectric conversion area and the voltage conversion area are surrounded by the annular isolation area.
The present disclosure provides a method of manufacturing an image sensor. The method includes forming an annular isolation area in a semiconductor substrate; forming a trench area in the annular isolation area; forming a first annular doped area in the semiconductor substrate, the first annular doped area comprises a first type dopant; forming a second annular doped area in the semiconductor substrate, the second annular doped area comprises a second type dopant; forming an isolation structure in the trench area; forming a gate structure on the semiconductor substrate; forming a photoelectric conversion area in the semiconductor substrate; and forming a voltage conversion area in the semiconductor substrate.
In order to describe the manner in which the above-recited features and other advantages of the disclosure can be obtained, a more particular description of the principles briefly described above will be rendered by reference to specific examples thereof which are illustrated in the appended drawings. It should be understood that these drawings depict only exemplary aspects of the disclosure and are therefore not to be considered to be limiting of its scope. The principles herein are described and explained with additional specificity and detail through the use of the accompanying drawings, in which:
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
For purposes of the present detailed description, unless specifically disclaimed, the singular includes the plural and vice versa; and the word “including” means “including without limitation.” Moreover, words of approximation, such as “about,” “almost,” “substantially,” “approximately,” and the like, can be used herein to mean “at, near, or nearly at,” or “within 3-5% of,” or “within acceptable manufacturing tolerances,” or any logical combination thereof, for example.
Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in. use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over elements described as being “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The semiconductor substrate 102 may be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with P-type dopants (e.g., Boron) or N-type dopants (e.g., Phosphorus)) or undoped. The semiconductor substrate 102 may be a wafer, such as a silicon wafer. In some embodiments, the semiconductor substrate 102 may include an elementary semiconductor (e.g., silicon, germanium, and diamond), a compound semiconductor (e.g., silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or the like), an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, or the like), another kind of semiconductor material, or combinations thereof. In some embodiments, the semiconductor substrate 102 may also include an epitaxial layer on bulk semiconductor, a silicon germanium layer on bulk silicon, a silicon layer on bulk silicon germanium, etc. In other embodiments, the semiconductor substrate 102 may also include an epitaxial layer doped with P-type or N-type dopants.
The photoelectric conversion area 104 is formed in the semiconductor substrate 102. The photoelectric conversion area 104 may include a photoelectric conversion element, such as a photodiode (PD). Specifically, the photoelectric conversion area 104 includes a P-type doped layer and an N-type doped layer formed by an ion implantation process. In other embodiments, the photoelectric conversion area 104 may include other types of photoelectric conversion elements.
The voltage conversion area 106 is formed in the semiconductor substrate 102. The voltage conversion area 106 may include a floating diffusion (FD) area, which may be considered as a voltage conversion element, such as a capacitive structure. Specifically, after electrons accumulated in the photoelectric conversion area 104 are moved to the voltage conversion area 106 by applying a voltage to the gate structure 108, the electrons may be accumulated in the voltage conversion area 106 (i.e., a capacitance structure), and the accumulated electrons have (generate) a voltage value. By reading this voltage value, an image sensed by the image sensor can be generated. in this embodiment, the voltage conversion area 106 has N-type dopants. Specifically, the voltage conversion area 106 is formed by implanting the N-type dopants into the semiconductor substrate 102 by performing an ion implantation process.
The gate structure 108 is fainted on the semiconductor substrate 102 between the photoelectric conversion area 104 and the voltage conversion area 106. The gate structure 108 may include a gate dielectric layer and a gate electrode. The gate dielectric layer may be silicon oxide, silicon nitride, multilayers thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The formation methods of the gate dielectric layer may include molecular-beam deposition (MBD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), or thermal oxidation, and the like. The gate electrode may be formed of single crystal silicon or polycrystalline silicon, but may be formed by using other materials. In some embodiments, the material of the gate electrode may include a metal-containing material such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), cobalt (Co), ruthenium (Ku), aluminum (Al), combinations thereof, or multi-layers thereof. The gate structure 108 may also be referred to as a transfer gate.
The isolation area 110 is formed in the semiconductor substrate 102 and surrounds the photoelectric conversion area 104, the voltage conversion area 106, and the gate structure 108 (i.e., the photoelectric conversion area 104, the voltage conversion area 106, and the gate structure 108 are in the semiconductor substrate 102 surrounded by the isolation area 110). Therefore, the isolation area 110 may also be referred to as an annular isolation area (in top view). The area surrounded by the isolation area 110 is referred to as a pixel area of the image sensor.
When the light is irradiated on the semiconductor structure 100 of the image sensor, electrons are excited. The electrons are accumulated in the capacitance formed by the photoelectric conversion area 104. However, if the excited electrons are close to the edge of the pixel, the electrons may cross to another pixel and accumulate in the photodiode of another pixel (e.g., the electron 112 of
The P-type doped area 202 may be selectively formed, and the P-type doped area 202 may maintain the quantum efficiency (QE) of the image sensor and block the electrons. However, if the electrons accumulated in the photoelectric conversion area 104 are excessive (saturated), the electrons still have a probability to cross the P-type doped area 202 and the isolation area 110. If the electrons cross the P-type doped area 202, the electrons are absorbed by the N-type doped area 204, the blooming will not occur, as shown by the electron 208. If the electrons cross the isolation area 110 to another pixel, the blooming will still occur, as shown by the electron 210. Therefore, in the present embodiment, instead of the P-type doped area 202 and the N-type doped area 204, an annular P-type doped area and an annular N-type doped area are formed to improve the blooming and still prevent the electrical crosstalk.
As shown in
In some embodiments, a portion of the annular P-type doped area 302 and a portion of the annular N-type doped area 304 extend and are directly under the photoelectric conversion area 404 and the voltage conversion area 406 for adjusting some characteristics of the image sensor (e.g., the quantum efficiency, the electron absorption, etc.).
In some embodiments, a shallow trench isolation (STI) structure (i.e., an isolation structure) (not shown) is formed in the isolation area 410 to further reduce the influence between pixels of the image sensor.
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It should be noted that the annular P-type doped area 302, the annular N-type doped area 304, and the isolation area 410 are all formed by the ion implantation process with the photoresist 502 as a mask on the semiconductor substrate 402. Therefore, the annular P-type doped area 302, the annular N-type doped area 304, and the isolation area 410 overlap each other. Furthermore, since no additional processing steps are required to form the photoresist for forming the annular P-type doped area 302 and the annular N-type doped area 304, the process cost is not increased as compared with the conventional process.
In some embodiments, the annular P-type doped area 302, the annular N-type doped area 304, and the isolation area 410 are respectively formed with different photoresists. The annular P-type doped area 302, the annular N-type doped area 304, and the isolation region 410 do not completely overlap each other.
In some embodiments, a shallow trench isolation structure is formed in the isolation area 410. Specifically, after the isolation area 410 is formed, a trench is formed in the isolation area 410 by an etching process. Silicon oxide (SiO2) is then deposited by a deposition process (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), etc.) to form the shallow trench isolation structure.
In some embodiments, the annular P-type doped area 302 and the isolation area 410 are formed by the same ion implantation process. Specifically, after the annular N-type doped area 304 is formed, the annular P-type doped area 302 and the isolation area 410 are simultaneously formed by only one ion implantation process. In other words, the annular P-type doped area 302 and the isolation area 41.0 are the same area. This process method can reduce process costs.
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In some embodiments, the annular P-type doped area 302, the annular N-type doped area 304, and the isolation area 410 may be formed by another process sequence.
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It should be noted that the annular P-type doped area 302 and the annular N-type doped area 304 are formed with the isolation area 410 having the trench area 610. In this case, the distance from the surface of the semiconductor substrate 402 to the position where the annular P-type doped area 302 and the annular N-type doped area 304 are to be formed is smaller. Therefore, the annular P-type doped area 302 and the annular N-type doped area 304 can be formed using a lower energy ion implantation process or less process time, and the formed annular P-type doped area 302 and the formed annular N-type doped area 304 will have a relatively narrow width (i.e., the annular P-type doped area 302 and the annular N-type doped area 304 are not easy to be formed/extended/diffused below the subsequently formed photoelectric conversion region 404 and voltage conversion region 406).
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The structure shown in the present embodiments of the disclosure is a rolling shutter structure. However, the partial VOD (the annular P-type doped area and the annular N-type doped area) of the present embodiments may also be applied to a global shutter structure.
The above embodiments are applied to a P-type substrate or a P-type well (e.g., the semiconductor substrate 402 is a P-type substrate or a P-type well area). However, it should be understood that the technique of the present disclosure may also be applied to an N-type substrate or an N-type well. In this case, the doping type of the P-type doped area and the N-type doped area of the above embodiment is reversed.
The embodiments of the present disclosure offer advantages over existing art, though it should be understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and that no particular advantage is required for all embodiments.
By utilizing the embodiments of the present disclosure, an image sensor having a partial vertical overflow drain (also referred to as an annular vertical overflow drain or a grid like vertical overflow drain) can be formed. Compared to conventional image sensors having a generally vertical overflow drain, the image sensor of the present embodiments can prevent blooming and does not reduce quantum efficiency.
The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms “including,” “includes,” “having,” “has,” “with,” or variants thereof, are used in either the detailed description and/or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 108108604 | Mar 2019 | TW | national |
