Image sensor comprising pixels with one transistor

Abstract

A pixel having a MOS-type transistor formed in and above a semiconductor substrate of a first doping type, a buried semiconductor layer of a second doping type being placed in the substrate under the MOS transistor and separated therefrom by a substrate portion forming a well. The buried semiconductor layer comprises a thin portion forming a pinch area placed under the transistor channel area and a thick portion placed under all or part of the source/drain areas of the transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a previously-described diagram of a known pixel;

FIG. 2 is a cross-section view of a portion of a sensor according to an embodiment of the present invention;

FIG. 3 is an electric diagram of a pixel array of an example of a sensor according to an embodiment of the present invention;

FIG. 4 is a diagram indicating the voltage variations in a pixel of the sensor shown in FIG. 2, between the surface and an internal portion of the substrate;

FIG. 5 is a diagram indicating the voltage variations through the wells of the pixels of the sensor shown in FIG. 2; and

FIGS. 6A, 6B, 6C, and 6D are cross-section views of structures obtained after successive steps of a method for manufacturing an image sensor comprising pixels according to an embodiment of the present invention.

Claims

1. A pixel comprising a MOS-type transistor formed in and above a semiconductor substrate of a first doping type, a buried semiconductor layer of a second doping type being placed in the substrate under the MOS transistor and separated therefrom by a substrate portion forming a well, wherein the buried semiconductor layer comprises a thin portion forming a pinch area placed substantially under the transistor channel area and a thick portion placed under all or part of the source/drain areas of the transistor.

2. The pixel of claim 1, wherein said pinch area is placed in the upper portion of the buried semiconductor layer, close to the substrate surface.

3. The pixel of claim 1, wherein an insulating area placed in the upper portion of the substrate surrounds the source/drain areas and the channel area of the transistor, said thick portion of the semiconductor layer surrounding the pinch area and extending under the insulating area.

4. The pixel of claim 1, wherein a tank area of the same doping type as the semiconductor substrate, but more heavily-doped than said substrate, is placed at the level of the channel area, at the substrate surface.

5. The pixel of claim 1, wherein the transistor comprises an insulated gate placed above the semiconductor substrate, the source/drain areas being placed on either side of the gate in the upper portion of the substrate, the surface portion of the substrate located between the source/drain areas under the gate forming said channel area.

6. The pixel of claim 5, wherein the gate and the source/drain areas of the transistor as well as the buried semiconductor layer are connected to conductive lines placed above the substrate, said well being floating.

7. An image sensor comprising pixels of claim 1, wherein the buried semiconductor layers of the pixels form one and the same buried semiconductor layer.

8. The image sensors of claim 7 as attached to claim 3, wherein said insulating areas of the pixels separate the pixel transistors from one another, the depth of the insulating areas being smaller than that of the pixel wells.

9. The image sensor of claim 8, wherein the wells of a pixel assembly extend under the insulating areas surrounding the transistors of these pixels, the wells of this pixel assembly being adjacent to one another.

10. A method for forming a pixel, comprising: forming, in a semiconductor substrate of a first doping type, an insulating area surrounding an upper portion of the substrate called active area;forming, in the semiconductor substrate, a buried semiconductor layer of a second doping type;forming a deep buried semiconductor pocket of the first doping type by ion implantation in a lower portion of the buried layer, whereby the thickness of the buried layer is decreased above this buried pocket, the buried pocket being placed substantially above a central strip of the active area intended to form a channel area;forming an insulated gate above the central strip of the active area;forming source/drain areas of the second doping type in the active area, on either side of the gate.