Integrated circuits (ICs) with complementary metal-oxide-semiconductor (CMOS) image sensors are used in a wide range of modern-day electronic devices, such as, for example, cameras and cell phones. Some CMOS image sensors are based on avalanche photodiodes (APD) and single-photon avalanche photodiodes (SPAD). Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Some modern integrated chips include image sensors. For example, an image sensor includes a photodetector (e.g., a photodiode, an avalanche photodiode (APD), a single-photon avalanche diode (SPAD) or the like) in a substrate. The photodetector includes a first doped region in the substrate and a second doped region in the substrate. The first doped region has a first doping type (e.g., p-type) and the second doped region has a second doping type (e.g., n-type), different from the first doping type. In some image sensors, the first doped region is disposed along a frontside of the substrate and the second doped region is disposed directly over (or directly under) the first doped region. The first doped region and the second doped region meet at a p-n junction that extends in a lateral (e.g., horizontal) direction along the first and second doped regions. For example, the p-n junction extends laterally along the top of the first doped region and the bottom of the second doped region.
Many image sensors include a plurality of individual pixels along the substrate. As technology advances, the lateral distance between the pixels of the image sensor (e.g., pitch) is reduced. A challenge with some photodetectors is that because the p-n junction extends laterally along the first and second doped regions, reducing the lateral distance between pixels of the image sensor requires reducing the size of the p-n junction. Further, reducing the size of the p-n junction may reduce a performance of the photodetector.
Various embodiments of the present disclosure are related to an image sensor including a first doped region and a second doped region laterally beside the first doped region so that a p-n junction between the first and second doped regions extends in a vertical direction. For example, the first doped region and the second doped region are in a first semiconductor layer having a first doping type. A second semiconductor layer having the first doping type is between sidewalls of the first semiconductor layer and extends vertically from a bottom side of the first semiconductor layer toward a top side of the first semiconductor layer. The first doped region has the first doping type and is laterally beside the second semiconductor layer. The second doped region has a second doping type, different than the first doping type, and is laterally beside the first doped region. The first and second doped regions form a p-n junction. By disposing the second doped region laterally beside the first doped region (e.g., instead of vertically over or under the first doped region), the p-n junction extends in a vertical direction (e.g., instead of a lateral or horizontal direction). Because the p-n junction extends in the vertical direction, the width of the pixel can be reduced without reducing the size of the p-n junction. Thus, the lateral distance between pixels of the image sensor can be reduced without diminishing a performance of the image sensor.
The image sensor includes a pixel 102 along the first semiconductor layer 104. The first semiconductor layer 104 has a first side 104a (e.g., a frontside) and a second side 104b (e.g., a backside), opposite the first side 104a. The first side 104a and the second side 104b extend laterally (e.g., along a horizontal direction 101x). The first side 104a is in a first plane 120 (e.g., that extends in horizontal direction 101x) and the second side 104b is in a second plane 122 (e.g., that extends in horizontal direction 101x). The first semiconductor layer 104 has a pair of sidewalls 104s and a lower surface 104c that extends between the pair of sidewalls 104s. The first semiconductor layer 104 comprises a first semiconductor (e.g., silicon or some other suitable material). The first semiconductor layer 104 has a first doping type (e.g., p-type doping).
The second semiconductor layer 106 is directly between the sidewalls 104s and directly below the lower surface 104c of the first semiconductor layer 104. The second semiconductor layer 106 extends vertically (e.g., along a vertical direction 101z) along the sidewalls 104s of the first semiconductor layer 104 from the first side 104a of the first semiconductor layer 104 toward the second side 104b of the first semiconductor layer 104. The second semiconductor layer 106 has an upper surface 106u that extends laterally along the lower surface 104c of the first semiconductor layer 104. The second semiconductor layer 106 has a pair of sidewalls 106s that extend vertically along the sidewalls 104s of the first semiconductor layer 104. The second semiconductor layer 106 comprises a second semiconductor (e.g., germanium, gallium nitride, gallium arsenide, some other group III-V semiconductor, or some other suitable material), different than the first semiconductor. The second semiconductor layer 106 has the first doping type.
The first doped region 108 in the first semiconductor layer 104 is laterally beside the second semiconductor layer 106. The first doped region 108 extends vertically along the second semiconductor layer 106. For example, a side 108s of the first doped region 108 extends vertically along a sidewall 106s of the second semiconductor layer 106. A bottom 108b of the first doped region 108 is spaced apart from the first side 104a of the first semiconductor layer 104. The first doped region 108 has the first doping type.
The second doped region 110 in the first semiconductor layer 104 is laterally beside the first doped region 108. The second doped region 110 extends vertically along the first doped region 108 from the first side 104a of the first semiconductor layer 104 toward the second side 104b of the first semiconductor layer 104. For example, a side 110s of the second doped region 110 extends vertically along a side 108s of the first doped region 108. The second doped region 110 has a second doping type (e.g., n-type doping), different from the first doping type.
The first doped region 108 and the second doped region 110 form a photodetector (e.g., a single-photon avalanche diode or the like) in the first semiconductor layer 104. For example, the first doped region 108 and the second doped region 110 form a p-n junction 118 where the first doped region 108 and the second doped region 110 meet. By disposing the first doped region 108 and the second doped region 110 laterally beside one another in the first semiconductor layer 104, the p-n junction 118 extends in a vertical direction (e.g., vertical direction 101z) between the first and second doped regions 108, 110. For example, the p-n junction 118 extends in a third plane 124 (e.g., that extends in extends in vertical direction 101z) that intersects the first plane 120 and the second plane 122. Further, because the p-n junction 118 extends vertically, a lateral width of the pixel 102 can be reduced without reducing the size of the p-n junction 118. Thus, a lateral distance between the pixel 102 and neighboring pixels of the image sensor can be reduced without diminishing a performance of the image sensor.
In some embodiments, the second semiconductor layer 106 further forms the photodetector and increases the photosensitive area of the pixel 102. For example, by including the second semiconductor layer 106 in the image sensor and laterally beside the first doped region 108, a depletion region of the photodetector can be increased. As a result, the photosensitive area of the pixel 102 can be increased. Thus, a fill factor of the pixel 102 (e.g., a ratio of the photosensitive area of the pixel 102 to the total area of the pixel 102) can be improved. Further, in some embodiments, the second semiconductor layer is lightly doped (e.g., has a low dopant concentration) and comprises a semiconductor material having a small bandgap so that the second semiconductor layer 106 is highly sensitive at some wavelengths (e.g., short-wave infrared (SWIR) or the like). Thus, a sensitivity of the image sensor at such wavelengths can be improved.
In some embodiments, a first contact region 112 is in the second semiconductor layer 106 and a second contact region 114 is in the second doped region 110. The first and second contact regions 112, 114 are disposed along the first side 104a of the first semiconductor layer 104. The first contact region 112 is a heavily doped region having the first doping type and the second contact region 114 is a heavily doped region having the second doping type.
In some embodiments, a trench isolation structure 116 extends through the first semiconductor layer 104 and surrounds the pixel 102 along the perimeter of the pixel 102 in a ring shape. The trench isolation structure 116 extends between the first side 104a and the second side 104b of the first semiconductor layer 104. The trench isolation structure 116 electrically and/or optically isolates the pixel 102 from neighboring pixels (not labeled).
In some embodiments, the first semiconductor layer 104 is on the upper surface 106u of the second semiconductor layer 106 and on tops of the first and second doped regions 108, 110. In some embodiments, the first doped region 108 is directly between the second semiconductor layer 106 and the second doped region 110. Further, in some embodiments, the first semiconductor layer 104 is directly between the second semiconductor layer 106 and the second doped region 110 along a bottom of the first doped region 108 and along a top of the first doped region 108. In some embodiments, the third plane 124 is perpendicular to the first plane 120 and the second plane 122. In some embodiments, the first side 104a of the first semiconductor layer 104 may be referred to as the bottom side or the bottom surface of the first semiconductor layer 104 and the second side 104b of the first semiconductor layer 104 may be referred to as the top side or the top surface of the first semiconductor layer 104.
In some embodiments, a width (e.g., a distance between outer sides) of the second doped region 110 is greater than a width of the first doped region 108 (e.g., as measured along horizontal direction 101x). Further, a width of the second semiconductor layer 106 is greater than the width of the second doped region 110. In some embodiments, increasing the width of the second semiconductor layer 106 increases the sensitivity of the photodetector at some wavelengths (e.g., short-wave infrared (SWIR) or the like).
In some embodiments, a top of the second semiconductor layer 106 is above a top 108t of the first doped region 108 and a bottom of the second semiconductor layer 106 is below a bottom 108b of the first doped region 108. In some embodiments, a top 110t of the second doped region 110 is above the top 108t of the first doped region 108 and a bottom 110b of the second doped region 110 is below the bottom 108b of the first doped region 108.
In some embodiments, a dopant concentration of the second semiconductor layer 106 is less than a dopant concentration of the first doped region 108 and a dopant concentration the first semiconductor layer 104. In some embodiments, a dopant concentration of the first contact region 112 is greater than a dopant concentration of the first semiconductor layer 104, the second semiconductor layer 106, and the first doped region 108. In some embodiments, a dopant concentration of the second contact region 114 is greater than a dopant concentration of the second doped region 110.
The color filter 202 is directly over the first semiconductor layer 104 and the micro-lens 204 is directly over the color filter 202. Photons may enter the pixel 102 through the micro-lens 204 and the color filter 202 before they impinge on the photodetector. In some embodiments, the image sensor further includes a dielectric structure 206 directly below the first semiconductor layer 104 (e.g., on the first side 104a of the first semiconductor layer 104) and a plurality of conductive interconnects 208 disposed within the dielectric structure 206.
In some embodiments, the color filter 202 and micro-lens 204 are disposed along the second side 104b (e.g., backside) of the first semiconductor layer 104. In such embodiments, the image sensor may be referred to as a backside illuminated (BSI) image sensor. In some other embodiments (not shown), the color filter 202 and micro-lens 204 are alternatively disposed along the first side 104a (e.g., frontside) of the first semiconductor layer 104 and over the dielectric structure 206. In such embodiments, the image sensor may be referred to as a frontside illuminated (FSI) image sensor.
In some embodiments, the first doped region 108 laterally extends into the second semiconductor layer 106. For example, the first doped region 108 may diffuse into the second semiconductor layer 106, thereby causing the overlap between the first doped region 108 and the second semiconductor layer 106. The overlapping area may be referred to as a diffused region of the first doped region 108. In such embodiments, the second semiconductor layer 106 is directly over the top of the first doped region 108. For example, an upper surface 106u and a sidewall 106s of the second semiconductor layer 106 are directly over a top 108t of the first doped region 108, and the sidewall 106s of the second semiconductor layer 106 is directly below a bottom 108b of the first doped region 108.
The first doped region 108, the second doped region 110, and the second semiconductor layer 106 extend laterally in horizontal direction 101x and horizontal direction 101y. In some embodiments, the first doped region 108, the second doped region 110, and the second semiconductor layer 106 have rectangular shaped top views. In some embodiments, the first semiconductor layer 104 has a square shaped top view and the trench isolation structure 116 has a square ring shaped top view. In some other embodiments (not shown), the first semiconductor layer 104 may alternatively have a circular shaped top view and the trench isolation structure 116 may alternatively have a circular ring shaped top view.
In some embodiments, the second semiconductor layer 106, the first doped region 108, and the second doped region 110 are arranged along a diagonal of the pixel 102 so that the second semiconductor layer 106 is arranged along a first corner of the pixel 102 and the second doped region 110 is arranged along a second corner of the pixel 102, opposite the first corner.
In some embodiments (e.g., as shown in
The second semiconductor layer 106 is in a center of the pixel 102. The first doped region 108 is ring shaped and laterally surrounds the second semiconductor layer 106 in a first closed path. When viewed in cross-sectional (e.g., as shown
In some embodiments, the second contact region 114 is directly below the second doped region 110 and sides of the second contact region 114 are approximately aligned with sides of the second doped region 110. In some embodiments, the second contact region 114 is laterally spaced apart from the second semiconductor layer 106 by the first semiconductor layer 104.
In some embodiments, the first and second contact regions 112, 114 are disposed along sides of the pixel, as illustrated by dashed boxes 112a, 114a. In some other embodiments, the first and second contact regions 112, 114 are disposed along corners of the pixel 102, as illustrated by dashed boxes 112b, 114b.
The second doped region 110 is in a center of the pixel 102. The first doped region 108 laterally surrounds the second doped region 110 in a ring shape. When viewed in cross-sectional (e.g., as shown
The separate second semiconductor layers 106 each surround and border the first doped region 108. The first doped region 108 surrounds the second doped region 110. The separate second semiconductor layers 106 are separated from one another by isolation regions 1002. In some embodiments, the isolation regions 1002 extend laterally between the second semiconductor layers 106 from the trench isolation structure 116 toward the second doped region 110. In some embodiments, the isolation regions 1002 are doped regions of the first semiconductor layer 104 and electrically isolate the separate second semiconductor layers 106 from one another along lateral directions 101x, 101y.
The isolation regions 1002 are on opposite sides of the second doped region 110. In some embodiments, the isolation regions 1002 are directly between the second doped region 110 and the trench isolation structure 116. In some embodiments, the first doped region 108 extends directly between the isolation regions 1002 and the second doped region 110. In some embodiments, the isolation regions 1002 extend vertically through the first semiconductor layer from the first side 104a of the first semiconductor layer 104 towards the second side of the first semiconductor layer 104. In some embodiments, the first semiconductor layer 104 is on tops of the isolation regions 1002. In some other embodiments, the isolation regions 1002 extend through the first semiconductor layer 104 to the second side 104b of the first semiconductor layer 104 (e.g., similar to the trench isolation structure 116).
For example, in some embodiments, instead of the isolation regions 1002 separating the separate second semiconductor layers 106, the trench isolation structure 116 alternatively extends between the separate second semiconductor layers 106. In some embodiments, the first doped region 108 extends along the trench isolation structure 116 and is directly between the trench isolation structure 116 and the second doped region 110.
For example, in some embodiments, the pixel 102 is not separated from neighboring pixels by the trench isolation structure 116. Instead, the first semiconductor layer 104 continuously extends between the pixel 102 and neighboring pixels. In some embodiments, the pixel 102 operates independently of the neighboring pixels and thus the trench isolation structure 116 may not be needed to isolate neighboring pixels. By removing the trench isolation structure 116 in such instances, a cost of forming the image sensor and/or a time required to form the image sensor may be reduced. Further, a size of the pixel 102 may be reduced.
As shown in cross-sectional view 1800 of
In some embodiments, the first and second doped regions 108, 110 are formed in the first semiconductor layer 104 one at a time. In some embodiments, the deeper of the first and second doped regions 108, 110 is formed in the first semiconductor layer 104 before the shallower of the first and second doped regions 108, 110. For example, in some embodiments, the second doped region 110 is formed in the first semiconductor layer 104 and the first doped region 108 is subsequently formed in the first semiconductor layer 104 laterally beside the second doped region 110. In some other embodiments, the first doped region 108 may alternatively be formed in the first semiconductor layer 104 before the second doped region 110 is formed in the first semiconductor layer 104.
In some embodiments, the first doped region 108 is formed in the first semiconductor layer 104 below the first side 104a of the first semiconductor layer 104 and extends vertically towards the second side 104b of the first semiconductor layer 104. Thus, in some embodiments, the first doped region 108 may be referred to as a buried doped region. In some embodiments, the second doped region 110 is formed along the first side 104a of the first semiconductor layer 104 and extends vertically towards the second side 104b of the first semiconductor layer 104.
Forming the first and second doped regions 108, 110 laterally beside one another in the first semiconductor layer 104 forms a p-n junction 118 along the interface between the first and second doped regions 108, 110. For example, by forming the first doped region 108 laterally beside the second doped region 110 so that a side of the first doped region 108 extends along a side of the second doped region 110, the p-n junction 118 at which the first doped region 108 and the second doped region 110 meet extends in a vertical direction (e.g., vertical direction 101z). Thus, a width of the pixel 102 can be reduced without reducing a size of the p-n junction 118. As a result, a lateral distance between the pixel 102 and neighboring pixels can be reduced without reducing a performance of the image sensor.
In some embodiments, a height (e.g., along a vertical direction 101z) of the p-n junction 118 can be controlled by controlling the depths of the first doped region 108 and the second doped region 110. Thus, when a width of the pixel 102 is reduced, a height of the p-n junction 118 can be increased to maintain the total size of the p-n junction 118. As a result, a performance of the image sensor can be improved.
As shown in cross-sectional view 1900 of
As shown in cross-sectional view 2000 of
As shown in cross-sectional view 2100 of
As shown in cross-sectional view 2200 of
As shown in cross-sectional view 2300 of
As shown in cross-sectional view 2400 of
As shown in cross-sectional view 2500 of
As shown in cross-sectional view 2600 of
At block 2702, form a first doped region and a second doped region laterally beside one another in a first semiconductor layer so that a p-n junction between the first doped region and the second doped region that extends along a vertical direction.
At block 2704, etch the first semiconductor layer to form a trench in the first semiconductor layer laterally beside the first doped region.
At block 2706, form a second semiconductor layer in the trench and along the first doped region.
At block 2708, form a first contact region in the second semiconductor layer and a second contact region in the second doped region.
At block 2710, form an interconnect structure over the first contact region and the second contact region.
At block 2712, form a trench isolation structure around the first doped region, the second doped region, and the second semiconductor layer.
At block 2714, form a color filter and a micro-lens over the first doped region, the second doped region, and the second semiconductor layer.
Thus, the present disclosure relates to an image sensor including a first doped region and a second doped region laterally beside the first doped region so that a p-n junction between the doped regions extends in a vertical direction along the first and second doped regions.
Accordingly, in some embodiments, the present disclosure relates to an image sensor including a first semiconductor layer having a bottom side and a top side. The first semiconductor layer has a first doping type. A second semiconductor layer is between sidewalls of the first semiconductor layer and extends vertically along the sidewalls of the first semiconductor layer from the bottom side of the first semiconductor layer toward the top side of the first semiconductor layer. The second semiconductor layer has the first doping type. A first doped region is in the first semiconductor layer and laterally beside the second semiconductor layer. The first doped region extends vertically along a sidewall of the second semiconductor layer. The first doped region has the first doping type. A second doped region is in the first semiconductor layer and laterally beside the first doped region. The second doped region has a second doping type, different from the first doping type. The second doped region extends vertically along a side of the first doped region and forms a p-n junction with the first doped region.
In other embodiments, the present disclosure relates to an image sensor including a first semiconductor layer having a bottom side in a first plane and a top side in a second plane. The first semiconductor layer has a first doping type. A first doped region is in the first semiconductor layer and extends vertically along a first sidewall of the first semiconductor layer. The first doped region has the first doping type. A second semiconductor layer extends vertically along a first side of the first doped region from the bottom side of the first semiconductor layer toward the top side of the first semiconductor layer. The second semiconductor layer is between the first sidewall of the first semiconductor layer and a second sidewall of the first semiconductor layer. The second semiconductor layer has the first doping type. A second doped region is in the first semiconductor layer and extends vertically along a second side of the first doped region from the bottom side of the first semiconductor layer toward the top side of the first semiconductor layer. The second doped region has a second doping type, different from the first doping type. The second doped region and the first doped region meet at a p-n junction, wherein the p-n junction extends vertically along the second side of the first doped region and along a side of the second doped region, and wherein the p-n junction is in a third plane that intersects the first plane and the second plane.
In yet other embodiments, the present disclosure relates to a method for forming an image sensor. The method includes doping a first semiconductor layer having a first doping type with a first dopant to form a first doped region having the first doping type in the first semiconductor layer. The first semiconductor layer is doped with a second dopant to form a second doped region having a second doping type, different than the first doping type, in the first semiconductor layer. The first doped region and the second doped region are formed laterally beside one another in the first semiconductor layer. A first side of the first doped region extends vertically along a side of the second doped region at a p-n junction between the first doped region and the second doped region. The first semiconductor layer is etched to form a trench in the first semiconductor layer laterally beside the first doped region. A sidewall of the first semiconductor layer that delimits the trench extends vertically along a second side of the first doped region, opposite the first side. A second semiconductor layer having the first doping type is formed in the trench and along the second side of the first doped region.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.