Patent Application
20130015323
The present invention relates to image sensing technology that utilizes a charge-based readout circuit performing correlated double sampling. Additionally, the invention may employ a ping-pong technique to enhance the overall performance of an image sensor.
Complementary metal-oxide-semiconductor (CMOS) image sensors, which are a type of active-pixel sensor (APS), typically are used in digital cameras to convert optical signals received by a pixel array to electronic signals. CMOS image sensors contain a plurality of sensor elements (or pixel circuits) which form a pixel array of columns and rows (say, N columns and M rows). When an image is detected by the pixel array, pixel circuits in the pixel array generate an electric signal corresponding to image information at each pixel location. Each pixel circuit contains a photosensitive component, such as a photodiode, which converts light signals into electric signals, and an amplifier, which amplifies the electric signals generated by the photosensitive component. The electric signals then are converted into the digital domain using analog-to-digital converters (ADCs) for signal processing purposes.
Many commercially available CMOS sensors employ a technique called column-parallel analog-to-digital conversion. This technique provides a single ADC for each column of a pixel array, digitizes pixel data from the array at the columns, and transfers that information off the sensor in the digital domain. There are two fundamental problems with this technique. First, increasing the number of ADCs on a chip increases power consumption and therefore raises the temperature of the sensor. This increase in temperature is disadvantageous because temperature is directly related to noise power. Second, mismatches in both offsets and gain errors of multiple ADCs may contribute to fixed-pattern noise in a sensor and can appear as image artifacts when the image data is displayed.
Thus, the inventor perceives a need in the art for a readout system in an image sensor that is low power and accurate.
Embodiments of the present invention may provide a charged-based readout system for an image sensor that includes a plurality of column readout circuits and a differential channel readout circuit selectively connected to the column readout circuits. A column readout circuit may perform sampling on signals received from a pixel array and may transfer a corresponding correlated double sample (CDS) signal to the differential channel readout circuit. The differential channel readout circuit may amplify CDS signals from the column readout circuits using an output amplifier system. The output amplifier system may be composed of two output amplifier paths so that ping-ponging is possible.
The readout system may operate in the charge domain, using an operational amplifier (op-amp) to force charge from a pair of input capacitors onto its feedback capacitors, where a voltage is developed. More precisely, the charge may be transferred from a pair of capacitors, allowing a correlated double sample operation by subtracting a sampled ‘reset’ charge from a sampled ‘signal’ charge (both of which are received from a pixel in a pixel array). The output of the amplifier, which is the voltage across the feedback capacitors, may then be buffered so this signal can be driven off chip.
Moreover, the circuit architecture permits one of the voltage supplies to the amplifier (e.g., VDD or ground) to be used as the amplifier input common-mode voltage. Use of an amplifier supply voltage as the input common-mode voltage allows high select switch conductance with low capacitance and, as a result, preserves high signal integrity. Accordingly, selection switches may be made smaller than for similar designs in which an input common-mode voltage were set at some other voltage, for example, ½ VDD.
During operation, the pixels are controlled to output reset (RST) values and signal (SIG) values to the CROs 120.1-120.N on a row-by-row basis. The RST values represent output signals generated by the pixels prior to exposure to incident light. Due to reset noise associated with resetting the pixel, the RST values from each pixel typically exhibit some variation from a nominal voltage. The SIG values represent output signals generated by the pixels after exposure to incident light. Because the incident light generally adds an additional signal value to an existing RST value, the same reset noise is typically present in both the RST and SIG values (i.e. they are correlated). Reset noise can therefore be removed by subtracting an RST sample from a SIG sample, also known as correlated double sampling.
The CROs 120.1-120.N may sample and store the RST and SIG signals from each pixel. Each CRO 120.1-120.N may be connected to the CH RO 130 by the router 140 in succession. When connected to the CH RO 130, each CRO 120.1-120.N may transfer a CDS signal to the CH RO 120 which may amplify the CDS signal and output it to the output pins P1, P2.
Controller 150 may be an on chip processor or state machine that controls operation of the pixel array, operation of switches in the CROs and CH ROs (described in
Optionally, an image sensor 100 may include multiple channels (not shown) each composed of its own CROs 120, multiplexer 140, CH RO 130, and output buffer 160. Color image sensors often utilize red, green, and blue pixels in a repeating pattern composed of 1 red pixel, 2 green pixels, and 1 blue pixel. In some systems, it may be desirable to read out the red and blue pixels on a first channel, and the green pixels on a second channel. In another system, it may be desirable to have 4 channels corresponding to 1 red, 1 blue, and 2 green. In yet other systems, it may be desirable to make the number of channels programmable via the routing fabric. Using multiple CH ROs 130 (not shown in
A CRO 210.1 may include an input terminal VIN, a pair of sampling capacitors CSIG, CRST, input switches SWINS, SWINR, sampling switches SWSMPS, SWSMPR, a transfer switch SWTR and select switches SWSELS, SWSELR. The input switches SWINS and SWINR may couple the input terminal VIN selectively to first terminals of a respective sampling capacitor CSIG or CRST. Sampling switches SWSMPS, SWSMPR may couple second terminals of a respective sampling capacitor CSIG or CRST to a sampling voltage 215 (shown as ground, in the example of
Operation of the CRO 210.1 may occur in several phases. In a first phase (or RST value sample phase), an RST value is output from a selected pixel in the pixel array to the CRO 210.1. During this time, a first input switch SWINR and a first sampling switch SWSMPR may be closed, causing a first sampling capacitor CRST to capture a voltage representing the RST signal. At the conclusion of the first phase, the switches SWINR and SWSMPR may open, holding the captured voltage on sampling capacitor CRST.
In a second phase (or SIG value sample phase), a SIG value is output from the selected pixel of the pixel array to the CRO 210.1. During this time, a second input switch SWINS and a second sampling switch SWSMPS may be closed, causing a second sampling capacitor CSIG to capture a voltage representing the SIG signal. At the conclusion of the second phase, the switches SWINS and SWSMPS may open, holding the captured voltage on sampling capacitor CSIG. At the conclusion of the second phase, the voltages on the first and second sampling capacitors CRST, CSIG may be held until the CRO 210.1 is connected to the CRO 220.
During a third phase (or transfer phase) of operation, the CRO 210.1 may be connected to the differential CH RO 220 by closing the select switches SWSELS, SWSELR. During the third phase, the transfer switch SWTR also may be closed. Because SWTR shorts the “sample” sides of CSIG and CRST together, closure of the transfer switch SWTR allows the charge difference between the two sampling capacitors CSIG, CRST to be transferred to the CH RO 220. This charge difference represents a subtraction of the RST value from the SIG value (CDS signal).
During operation, the CROs 210.1-210.N may perform operations of the first and second phases in parallel with each other. That is, the CROs 210.1-210.N may capture RST and SIG values in common, parallel operations. The CROs 210.1-210.N each may perform their third phases in a staggered fashion because they share a common CH RO 220. Thus, the CH RO 220 may receive an output signal first from CRO 210.1 and may generate an output from it, then reset and receive an output signal from CRO 210.2. After the CH RO 220 receives output signals from all the CROs 210.1-210.N, the CROs 210.1-210.N may return to the first phase to receive RST and SIG values from selected pixels in another row of the pixel array.
The CH RO 220 also may operate in multiple phases of operation. During a reset phase, the CH RO 220 may be reset for a new iteration of operation. Specifically, the common-mode switches SWCM and shorting switch SWSHORT may be closed. Inputs of the op-amp 222 (readout lines 212 and 214) may be set to an identical voltage by the common-mode switches SWCM. Similarly, output terminals of the op-amp 222 may be set to an identical voltage by the shorting switch SWSHORT. Thus, voltages on the feedback capacitors CFBS and CFBR may be equalized.
In an amplification phase (which may coincide with the transfer phase of CRO 210.1), the switches SWCM and SWSHORT of the differential CH RO 220 may be opened. The differential CH RO 220 may receive the signal output from CRO 210.1. The feedback around op-amp 222 forces its inputs to be substantially identical, transferring the charge difference between CSIG and CRST to CFBS and CFBR, generating a differential voltage signal on output terminals VOP and VON.
Specifically, as described in the third phase (or transfer phase) of CRO 210.1, the charge difference between CSIG and CRST may be transferred to CFBS and CFBR. The negative feedback around differential op-amp 222 holds readout lines 212 and 214 at substantially identical voltages (0V differential). If the series combination of CSIG and CRST has 0V across it, there can be no net charge from the equation Q=CV, where Q is charge, C is capacitance, and V is voltage. Consequently, due to conservation of charge, the original charge is transferred to CFBS and CFBR. Because the charge is transferred from CSIG and CRST to CFBS and CFBR, the voltage across CSIG and CRST is amplified by a ratio of CSIG/CFBS or CRST/CFBR (assuming CSIG=CRST and CFBS=CFBR). This amplified signal is presented as a differential voltage signal at output terminals VOP and VON.
It is important to note that this simple CDS operation is a direct result of the differential charge transfer that takes place between CRO 210.1 and differential CH RO 220. Without the differential charge transfer, and accompanying differential architecture of the amplifier, this operation would be more complicated. Indeed, a common method of accomplishing this CDS is the use of individual column amplifiers which may lead to increased power consumption, required chip area, and fixed-pattern noise (FPN).
In the embodiment illustrated in
Odd and even CROs 310.1-310.N may be substantially similar to the CRO 210.1 described above with respect to
Odd CH RO 321 and even CH RO 322 may be substantially similar to CH RO 220 described above with respect to
Switches SWSH-O and SWSH-E may be similar to switch SWSHORT described with respect to
Control switches 325 and 326 connect the respective CH ROs 321, 322 to common output buffer 330 based on control signals CLK and CLKB, respectively. Control signals CLK, CLKB may be controlled by an internal controller (not shown in
The common output buffer 330 may have inputs to receive output signals VONO, VOPO from the odd CH RO 321, and output signals VONE, VOPE from the even CH RO 322. Additionally, the common output buffer 330 may have differential outputs for outputting differential output signals OUTN and OUTP.
In the present embodiment, a respective one of the odd CROs 310.1-310.N-1 may be connected to odd CH RO 321, forming an “odd pixel signal chain.” Similarly, a respective one of the even CROs 310.2-310.N may be connected to even CH RO 322, forming an “even pixel signal chain.” Specifically, respective odd and even CROs 310.1-310.N may be connected to corresponding odd CH RO 321 and even CH RO 322 in a manner similar to how CRO 210.1 and CH RO 220 may be connected as described with reference to
The general concept of operation of readout system 300 is as follows: while a respective “odd pixel signal chain” (formed by connecting a respective odd CRO 310.1-310.N-1 to odd CH RO 321) may be in one state (e.g., amplify), the “even pixel signal chain” (formed by connecting a respective even CRO 310.2-310.N to even CH RO 322) may be in another state (e.g., reset). Specifically, a controller (not shown in
For example, while the sampled signals from one odd CRO (e.g., 310.1) are being amplified in the odd CH RO 321 during an amplify phase, switches 325 may be closed in response to a high control signal CLK and SWSH-O may be opened. Amplified signals VONO and VOPO may be applied to inputs of common output buffer 330 and may be output as output signals OUTN and OUTP, which represent a selected odd pixel signal value after CDS has been performed for the respective odd pixel being read out.
In the above example, while the odd pixel signal chain is in the amplify phase, the even pixel signal chain may be in the reset phase. Specifically, in the reset phase, switches 326 may be open in response to a low control signal CLKB, and switch SWSH-E may be closed to allow even CH RO 322 to reset as explained above with respect to
After the odd pixel signal chain completes the amplify phase and the even pixel signal chain completes the reset phase, the operations may switch, and the odd pixel signal chain may begin a reset phase, and the even pixel signal chain may begin an amplify phase. When the odd pixel signal chain is in a reset phase, switches 325 may be open in response to a low CLK signal and switch SWSH-O may be closed. Opening switches 325 prevents the shorting switch SWSH-O from interfering with the even pixel signal being read out.
When the even pixel signal chain is in an amplify phase, switches 326 may be closed in response to a high CLKB signal and SWSH-E may be opened. Amplified signals VONE and VOPE may be output to common output buffer 330. Common output buffer 330 may then output differential signals OUTN and OUTP, which represent the CDS values for the respective even pixel being read out. The process may then switch back, and the respective operations may repeat for the next odd and even CROs. This process is known as “ping-ponging.”
In the embodiment illustrated in
Advantages of the ping-ponging process described above in readout system 300 include reducing noise and providing a better power/speed trade-off. The configuration cuts the number of select switches for any one amplifier in half, thus reducing the parasitic capacitance on the amplifiers' summing nodes which may reduce noise. In addition, the use of two amplifiers means each can run at half the speed, allowing for a better power/speed trade-off than is possible with one amplifier.
Out-of-phase clocks CLK and CLKB may control the operation of switches 325, 326, SWSH-O, and SWSH-E. Each CH RO 321, 322 may have a half-period time of T, which is the time to output a signal from a selected pixel of a pixel array. Individual differential outputs VOPO-VONO, VOPE-VONE of respective CH ROs 321, 322 are shown in amplify and reset phases. The ping-ponging function can be realized when comparing timing diagrams for VOPE-VONE with VOPO-VONO. For example, when VOPE-VONE (which are the outputs of even CH RO 322) may be in an amplify state at a given time, VOPO-VONO (which are the outputs of odd CH RO 321) may be in a reset phase.
The combined differential output OUTP-OUTN from common output buffer 330 is also shown. As seen in the combined differential output OUTP-OUTN, an additional advantage of ping-ponging between the odd and even CH ROs 321, 322 is that no time is wasted by waiting a half-period T for an amplifier to reset. For example, while odd CH RO 321 may be in a reset phase, even CH RO 322 may be in an amplify phase (and vice versa). This effectively doubles the maximum readout rate of the system.
The techniques of the foregoing embodiments allow circuit designers to place ADCs off-chip. Consequently, the heat dissipated by the ADCs is away from the image sensor. Additionally, because the foregoing techniques reduce the number of parallel ADCs required, the number of potential sources of fixed-pattern noise is reduced.
Although the foregoing techniques have been described above with reference to specific embodiments, the invention is not limited to the above embodiments and the specific configurations shown in the drawings. For example, some components shown may be combined with each other as one embodiment, or a component may be divided into several subcomponents, or any other known or available component may be added. Further, although it has been convenient to refer to the CROs of the foregoing embodiments as being associated with “columns” of the array, such designations should not be interpreted to exclude CROs being associated with “rows” of the array. Moreover, although the preceding discussion has presented the column readout circuits as connected to “columns” of the pixel array, the discussion is not meant to impose any specific orientation with respect to the array; the principles of the present invention also extend to configurations in which the readout circuits are connected instead to respective rows of a pixel array. Those skilled in the art will appreciate that these techniques may be implemented in other ways without departing from the sprit and substantive features of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive.
| Number | Date | Country | |
|---|---|---|---|
| 61507980 | Jul 2011 | US |
