Patent Application
20240405039
This disclosure relates generally to image sensors, and in particular but not exclusively, relates to stacked CMOS image sensors and applications thereof.
Image sensors are one type of semiconductor device that have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, as well as, medical, automobile, and other applications. As image sensors are integrated into a broader range of electronic devices it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, size, etc.) through both device architecture design as well as image acquisition processing. However, it is appreciated that many of these metrics are inversely related. For example, pixel size may be increased to improve dynamic range but have increased noise. In another example, resolution may be increased by increasing the number of pixels, but if pixel size is maintained then the physical size of the image sensor increases. Accordingly, improving one or more performance metrics of semiconductor devices such as image sensors while mitigating adverse effects on other performance metrics remains challenging.
The typical image sensor operates in response to image light reflected from an external scene being incident upon the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption of the image light. The image charge photogenerated by the pixels may be measured as analog output image signals on column bit lines that vary as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is readout as analog image signals from the column bit lines and converted to digital values to produce digital images (i.e., image data) representative of the external scene.
Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. Not all instances of an element are necessarily labeled so as not to clutter the drawings where appropriate. The drawings are not necessarily to scale; emphasis instead being placed upon illustrating the principles being described.
Embodiments of an apparatus, system, and/or method related to an image sensor with shared gate architecture for metal layer reduction and metal layer utilization improvement are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. It should be noted that element names and symbols may be used interchangeably through this document (e.g., Si vs. silicon); however, both have identical meaning.
Image sensors with small-pixel layouts (e.g., submicron pixel pitch) face manufacturing space constraints. For example, it may be difficult to meet the design rules of a given processing node set by a manufacturing foundry, which risks process variation during fabrication. Process variation may correspond to variation in oxide thickness, dopant fluctuations, and variance in structure geometry and location. It is appreciated that structure geometry relates to length, width, and height of one or more components that form or are otherwise included in a given image sensor. In image sensors with small-pixel layouts, these variations can constitute a significant percentage of a given pixel, which may cause pixel and circuit performance abnormalities that may lead to production yield loss, performance degradation, or otherwise have a negative impact on image sensor performance.
One way to facilitate fabrication of small-pixel layouts is to employ a stacked chip scheme (e.g., a stacked semiconductor device that utilizes multiple semiconductor substrates or wafers) to conserve space by distributing components of the image sensor across multiple semiconductor substrates. In such a way, components may be offloaded to different substrates and occupancy area or fill factor of photodiodes and/or other components of the image sensor may be increased. In other words, lateral space on or in a given substrate may be more efficiently utilized. Additionally, the overall lateral space available within the image sensor package may be increased by utilizing a stacked chip scheme. However, it is appreciated that manufacturing costs of an image sensor with a stacked chip scheme may be appreciably affected since more masks and processing steps are necessary to fabricate the device. Accordingly, the issues of variance and cost may hinder the development and adoption of image sensors with small-pixel layouts and there is a need for a solution to reduce unit pixel space and cost.
Embodiments described herein employ a stacked chip scheme with a layout that enables a submicron pixel pitch, reduces fabrication costs, and further mitigates processing variance by being able to meet design rules of a given processing node set by a manufacturing foundry (e.g., 45 nm technology node). This is achieved, at least in part, by arranging components of pixel cell circuitry (e.g., transistor and other circuitry elements for pixel operation and readout) in a manner such that gate electrodes may be shared across adjacent transistors and/or threshold voltage implant areas may be shared across adjacent transistors. In some embodiments, this is achieved by a shared polysilicon (or other conductive material) architecture formed in or on a given semiconductor substrate that functions as local routing (e.g., in lieu of internal metal interconnects). As a result, the required metal layers for the image sensor may be decremented by at least one, which enables greater routing flexibility of metal layers, conserves space, and reduces fabrication cost. For example, a “metal 1” layer may correspond to the closest metallization layer to an active region of a semiconductor substrate and typically be utilized for internal routing (e.g., using metal lines or wires and contact vias disposed within an intermetal dielectric layer) to couple individual components (e.g., transistors). However, in embodiments of the disclosure, transistor source/drain regions are arranged to be sufficiently close that polycrystalline silicon (i.e., polysilicon) or other conductive materials may be utilized to form shared gate electrodes of transistors. In other words, instead of forming two separate transistors and then coupling them together using one or more metal layers (e.g., coupling a first gate electrode of a first transistor to a second gate electrode of a second transistor via one or more metal wires and/or contact vias), the transistors may be coupled together at the component level (e.g., a shared gate electrode extends over the active regions of both the first and second transistor). In such embodiment, the shared gate electrode may be formed as a monolithic structure. Accordingly, shared gate electrodes of transistors formed using polycrystalline silicon (i.e., polysilicon) or other conductive materials in embodiments of the disclosure may provide internal routing functionality that may displace the need of using the aforementioned “metal 1” layer for pixel circuit component via contact routing (i.e., internal routing) employed by conventional image sensors. Such embodiments advantageously facilitate reduced fabrication cost and routing flexibility.
In some embodiments, this may be achieved by sharing gate electrodes between adjacent transistors. In the same or other embodiments, source and/or drain regions of adjacent transistors are coupled together by using a common junction formed in the semiconductor substrate. In the same or other embodiments, transistors are arranged to form a small-pixel layout in which threshold voltage implant areas (e.g., doped areas for controlling threshold voltage of transistors) are shared by multiple transistors across separate and adjacently disposed 4C pixel cells. In the same or other embodiments, oxide defined regions (e.g., areas in or on the semiconductor substrate defined by shallow trench isolation structures, deep trench isolation structures, other isolation structures, or combinations thereof) in conjunction with gate electrode arrangement are utilized to facilitate formation of transistors that may otherwise have dimensions below critical dimensions for a given processing node. It is appreciated that the above-described features may facilitate formation of image sensors with small-pixel layouts but are also applicable to larger pixel layouts. Defined herein, a small-pixel layout corresponds to an image sensor having a separation distance between midpoints of two adjacent pixels being less than 1 μm (e.g., submicron pixel pitch), such as approximately 0.9 μm, 0.8 μm, 0.7 μm, 0.6 μm, 0.5 μm, 0.4 μm, 0.3 μm or otherwise. It is appreciated that the term “approximately” corresponds to within 10%, ±0.1 μm, or otherwise corresponds to variance associated with a given processing node utilized to fabricate the image sensor. It is further appreciated that while embodiments disclosed herein generally focus on image sensors with submicron pixel pitch, other embodiments may have a pixel pitch greater than 1 μm.
It is appreciated that embodiments of the disclosure reference “source” and “drain” regions of various transistors (e.g., row select, reset, source-follower, dual-floating diffusion, and other transistors associated with operation or readout of pixels or pixel cells) that correspond to doped regions within a semiconductor material or substrate. In such embodiments, a specific relationship may be described (e.g., drain regions of different transistors coupled together, source regions of different transistors coupled together, a source region of one transistor coupled to a drain region of another transistor, common junctions corresponding to source or drain regions of different transistors, and the like). While the terms “source” and “drain” generally refer to the direction charge carriers flow charge transfer (e.g., carriers moving from source region to drain region), it is appreciated that the transistors described herein may be symmetrical devices and thus can be operated with bidirectionality (e.g., carrier transfer from source to drain or carrier transfer from drain to source). Accordingly, one of ordinary skill in the art will understand that reference to an element as a “source” region or “drain” region does not necessarily limit the directionality of charge transfer of the associated transistor(s).
In the illustrated embodiment of
The stacked chip scheme of the imaging system 100 illustrated in
In some embodiments, the plurality of pixel cells 105 may be coupled to the pixel cell circuitry 155 through one or more hybrid bonds, through-silicon vias, other suitable circuitry coupling technologies, or combinations thereof. In some embodiments, the space saved on the first semiconductor substrate 101 by offloading circuitry to the second semiconductor substrate 151 (or other subsequent substrates in the stacked chip scheme) may be repurposed to increase the size of individual photodiodes included in each individual pixel included in the plurality of pixel cells 105 to allow for increased pixel size, density, sensitivity, full well capacity, combinations thereof, or the like. Additionally, or alternatively, functionality of the imaging system 100 may be facilitated as the second semiconductor substrate 151 may have room for additional components or circuitry that may not otherwise fit on an individual substrate that contains both the plurality of pixel cells 105 and the pixel cell circuitry 155 without affecting the performance and/or functionality of the imaging system 100. Additionally, it is appreciated that when reducing the pixel pitch of the plurality of pixel cells 105, there may be a commensurate increase in density for the pixel cell circuitry 155, which may place further constraints (e.g., in terms of meeting the design rule requirements dependent on the technology node being used for fabrication) on the design and layout of the pixel cell circuitry 155. Accordingly, the layout for the pixel cell circuitry 155 described in embodiments of the disclosure provides a suitable configuration for facilitating reduced pixel pitch (e.g., submicron pixel pitch) while simultaneously mitigating processing variations and reducing fabrication costs by utilizing a layout of the pixel cell circuitry 155 that includes, inter alia, repeat units having a shared gate electrode, a shared junction, a shared threshold voltage implant region, or combinations thereof.
In the illustrated embodiment, the second semiconductor substrate 151 is coupled to the first semiconductor substrate 101 and the third semiconductor substrate 191 (e.g., the second semiconductor substrate 151 is disposed between the first semiconductor substrate 101 and the third semiconductor substrate 191) to form the stacked semiconductor device. The first semiconductor substrate 101 includes the plurality of pixel cells 105, which are arranged in rows (e.g., R1, R2, R3, . . . . RY) and columns (e.g., C1, C2, C3, . . . . CX) to form the array of pixel cells. Each of the plurality of pixel cells 105 may include any number of pixels (e.g., one, two, four, eight, or more pixels per pixel cell). In most embodiments, the number of pixels per pixel cell included in the plurality of pixel cells 105 is uniform. In one embodiment, each pixel cell included in the plurality of pixel cells 105 have a regular arrangement (e.g., a two-by-two arrangement of four pixels, a two-by-three arrangement of six pixels, a two-by-four arrangement of eight pixels, a four-by-four arrangement of sixteen pixels, or otherwise). In some embodiments, an individual pixel cell included in the plurality of pixel cells 105 may correspond to a minimal repeating unit of the first semiconductor substrate 101, or more specifically, the plurality of pixel cells 105. In other embodiments, a group of pixel cells included in the plurality of pixel cells 105 may correspond to a minimal repeating unit of the first semiconductor substrate 101 and/or the plurality of pixel cells 105 (e.g., a two-by-two group of pixel cells included in the plurality of pixel cells 105 may correspond to a minimal repeating unit). In some embodiments, the pixel cell circuitry 155 of the second semiconductor substrate 151 is arranged based on a corresponding arrangement of the plurality of pixel cells 105 on the first semiconductor substrate 101. For example, in some embodiments, one or more pixel cells included in the plurality of pixel cells 105 of the first semiconductor substrate 101 may be respectively coupled to respective repeat units included in the pixel cell circuitry 155 of the second semiconductor substrate 151 on a per-pixel or per-pixel cell basis, which may result in an arrangement of the pixel cell circuitry 155 being regular and/or repeating (e.g., in rows and columns as illustrated).
As illustrated in
As illustrated, the imaging system 100 further includes a plurality of photodiodes 104 (e.g., a first photodiode 104-1, a second photodiode 104-2, and so on until a Nth photodiode 104-N, where “N” corresponds to the total number of photodiodes included in the plurality of photodiodes 104) disposed between a first side 102 (e.g., a front side, a backside, or a non-illuminated side) and a second side 103 (e.g., a backside, a front side, or an illuminated side) opposite the first side 102 of the first semiconductor substrate 101, a plurality of color filters 107 (e.g., a first color filter 107-1, a second color filter 107-2, and so on until an Mth color filter 107-M, where “M” corresponds to the total number of color filters included in the plurality of color filters 107), and a plurality of microlenses 108 to collectively form a plurality of pixels 110 (e.g., a first pixel 110-1, a second pixel 110-2, and so until an Nth pixel 110-N, where “N” corresponds to the total number of pixels included in the plurality of pixels 110). As discussed previously the plurality of pixels 110 are segmented to form pixel cells included in the plurality of pixel cells 105 (e.g., a first pixel cell 105-1 as illustrated, which may be representative of any other pixel cell included in the plurality of pixel cells 105). It is appreciated that in some embodiments, the total number of color filters (e.g., “M”) included in the plurality of color filters 107 may be equal to the total number of photodiodes (e.g., “N”) included in the plurality of photodiodes 104 (e.g., a one-to-one ratio of color filters to photodiodes). However, in other embodiments the plurality of color filters 107 may be shared by adjacent photodiodes included in the plurality of photodiodes 104 such that “M” is less than “N.” For example, in some embodiments each pixel cell included in the plurality of pixel cells 105 may include multiple pixels included in the plurality of pixels 110. In some embodiments, pixels included in the plurality of pixels 110 for a common pixel cell included in the plurality of pixel cells 105 (e.g., the first pixel 110-1 and the second pixel 110-2 are included in the first pixel cell 105-1) may share the same color filter or otherwise have a common color filter configuration (e.g., the first color filter 107-1 and the second color filter 107-2 may have a common spectral photoresponse).
As illustrated, the plurality of color filters 107 are optically disposed between the plurality of microlenses 108 and the plurality of photodiodes 104 such that light 198 propagates through both the plurality of microlenses 108 and the plurality of color filters 107 before reaching the plurality of photodiodes 104 (i.e., when the imaging system 100 is a backside illuminated image sensor). Each microlens included in the plurality of microlenses 108 is configured to direct or otherwise focus the light 198 through an underlying color filter included in the plurality of color filters 107 and the second side 103 of the first semiconductor substrate 101 towards a respective one of the plurality of photodiodes 104 in the first semiconductor substrate 101. The plurality of color filters 107 filter or otherwise attenuate the light 198 focused by the plurality of microlenses 108. In some embodiments, the plurality of color filters 107 may include one or more red, green, blue, infrared, clear, transparent, cyan, magenta, yellow, black, or any other color filter to filter visible or non-visible light (e.g., light 198). Similar to the plurality of color filters 107, the total number of microlenses included in the plurality of microlenses 108 may be equal to the total number of photodiodes (e.g., “N”) included in the plurality of photodiodes 104 (e.g., a one-to-one ratio of microlenses to photodiodes) and/or the total number of color filters (e.g., “M”) included in the plurality of color filters 107 (e.g., a one-to-one ratio of microlenses to color filters). However, in other embodiments the plurality of microlenses 108 may be shared by adjacent photodiodes included in the plurality of photodiodes 104 (e.g., a group of adjacent photodiodes included in the plurality of photodiodes 104, such as the first photodiode 104-1, the second photodiode 104-2, and/or other photodiodes adjacent to the first photodiode 104-1 and the second photodiode 104-2, may be optically aligned with or otherwise share an individual microlens included in the plurality of microlenses 108).
As illustrated in
In the illustrated embodiment of
In the illustrated embodiment, each two-by-two array of transfer gates are shaped (when viewed from a top view) to correspond to a rectangle or square with a corner or vertex cut off (e.g., a convex pentagon with three adjacent right angles). The cut off corners of the transfer gates may be arranged adjacently for a given 4C pixel cell to form an edge parallel with an edge of a diagonally disposed transfer gate to laterally (when viewed from a top view) surround a floating diffusion region (“FD”) formed in the semiconductor substrate 101. For example, transfer gates 120-1 through 120-4 included in the plurality of transfer gates 120 laterally surround floating diffusion region 121-1. It is appreciated that the plurality of transfer gates 120 for a given 4C pixel cell included in the plurality of pixel cells 105 are coupled to the same or a common floating diffusion region (e.g., 121-1, 121-2, 121-3, and 121-4) included in the plurality of floating diffusion regions 121 formed in the semiconductor substrate 101. It is appreciated that the shape and/or dimension of the plurality of transfer gates 120 may be configured based on a specific layout of a given 4C pixel cell. For example, other polygonal shape such as triangular or trapezoidal may also be employed.
More generally, it is appreciated that in the illustrated embodiment, each 4C pixel cell included in the plurality of pixel cells 105 is associated with an individual floating diffusion region included in the plurality of floating diffusion regions 121 (see, e.g.,
The cross-sectional view 101-ZZ′ includes pixels 110-1 and 110-2, which each include a respective transfer gate (e.g., 120-1 and 120-4), pinning region (e.g., 111-1 and 111-4), doped region (112-1 and 112-4), and deep doped region (e.g., 113-1 and 113-4). The pinning region, doped region, and deep doped region collectively form a pinned photodiode included in a given pixel (e.g., pixels 110-1 and 110-4). Disposed between the pinned photodiode of the given pixel and the corresponding transfer gate is gate insulation layer 118 that functions as a gate dielectric. It is appreciated that in the illustrated embodiment, the floating diffusion region is shared for a given 4C pixel cell (e.g., as illustrated in
In some embodiments, the DTI structure 115 includes an oxide material (e.g., silicon dioxide) or other insulating material. In some embodiments, a depthwise thickness of the DTI structure 115 may be substantially the same as a thickness of the semiconductor substrate 101. In the same or other embodiments, the pinning regions 111-1 and 111-4, the doped regions 112-1 and 112-4, the deep doped regions 113-1 and 113-4, well 114-1, and floating diffusion region 121-1 correspond to doped regions of the semiconductor substrate 101 in which dopants have been implanted or otherwise diffused into the semiconductor substrate within specified locations. For example, pinning regions 111-1 and 111-4 and well 114-1 may have a first conductivity type (e.g., P-type or N-type) that is opposite of a second conductivity type (e.g., N-type or P-type) of the doped region 112-1 and 112-4, deep region regions 113-1 and 113-4, and floating diffusion region 121-1. However, it is appreciated that in some embodiments certain elements may be omitted (e.g., pinning regions 111-1 and 111-4 and deep doped regions 113-1 and 113-4 may be optionally omitted when the photodiode is not a pinned photodiode).
As illustrated in
As illustrated, reset transistor 144 is coupled to the floating diffusion region 121-1 via the PLHB to reset the 4C pixel cell 105-4C (e.g., discharge or charge the photodiodes 104-1, 104-2, 104-3, and 104-4) and the floating diffusion region 121-1 to a preset voltage in response to a reset signal RST. The gate of the source-follower transistor 146 is also coupled to the floating diffusion region 121-1 such that the source-follower transistor 146 outputs an image signal (e.g., image data) in response to image charge in the floating diffusion region 121-1. A first row select transistor 147 and a second row select transistor 148 are coupled together and further coupled to the source-follower transistor 146 to output the image data signal to a selected bitline (e.g., bitline N or bitline N+1) in response to row select signals RS1 and/or RS2. It is appreciated that in some embodiments having dual row select transistors (e.g., first row select transistor 147 and second row select transistor 148) provides selective binning of image data during readout. In some embodiments, a dual floating diffusion transistor 135 may optionally be coupled between the floating diffusion region 121-1 and the reset transistor 144 to provide additional dynamic range capabilities to the 4C pixel cell 105-4C, if desired, in response to a dual floating diffusion signal DFD. In some embodiments, the additional dynamic range is provided by a capacitor such as a lateral overflow integration capacitor or a junction capacitor (e.g., corresponding to FD2). In the illustrated embodiments, the capacitor, denoted by FD2, may have one end coupled to a source of dual floating diffusion transistor 135 and the other end coupled to receive a biasing voltage (e.g., V_bias) for conversion gain configuration and signal readout operation control.
In some embodiments, components included in the repeat unit 180 illustrated in
Referring back to
Additionally, the gates of the dual floating diffusion transistor 135 for adjacent instances of the repeat unit 180 may correspond to a shared gate electrode (see, e.g.,
The embodiment illustrated in
In the illustrated embodiment, the pixel cell circuitry 255 includes a plurality of source follower gate electrodes 215 (e.g., SF1 gate electrodes 215-1, 215-2, 215-3, and 215-4) and 216 (e.g., SF2 gate electrodes 216-1, 216-2, 216-3, and 216-4), a plurality of row select gate electrodes 225 (e.g., RS1 gate electrodes 225-1, 225-2, 225-3, 225-4, 225-5, 225-7, 225-7, 225-8, and 225-9) and 226 (e.g., RS2 gate electrodes 226-1, 226-2, 226-3, 226-4, 226-5, and 226-6), source regions 227 of row select transistors (e.g., RS1 source regions 227-1, 227-2, 227-3, and 227-4) and 228 (e.g., RS2 source regions 228-1, 228-2, 228-3), isolation structure 229 (e.g., corresponding to the white regions of the second semiconductor substrate 251 that may define perimeter boundaries of the regions with a diagonally striped pattern for pixel cell circuitries in the illustrated embodiment), a plurality of reset gate electrodes 230 (e.g., RST gate electrodes 230-1, 230-2, 230-3, and 230-4), a plurality of dual floating diffusion (DFD) gate electrodes 235 (e.g., DFD gate electrodes 235-1, 235-2, 235-3, and 235-4), source regions 236 of the DFD transistors (e.g., 236-1, 236-2, 236-3, 236-4), common junctions 260 (e.g., 260-1, 260-2, 260-3), common junctions 261 (e.g., 261-1 and 261-2), common junctions 262 (e.g., 262-1, 261-2, 261-3, and 264-4), a plurality of ground contact regions 270 (e.g., 270-1, 270-2, 270-3, 270-4, 270-5, and 270-6), first threshold voltage doped region 271, second threshold voltage doped region 272, third threshold voltage doped region 273, and fourth threshold voltage doped region 274.
It is appreciated that
As illustrated in
It is noted that the second repeat unit 280-2, which is adjacent to the first repeat unit 280-1 includes the same components that may all necessarily be labeled. Accordingly, symmetry occurs along a direction extending between the first repeat unit 280-1 and the second repeat unit 280-2 (e.g., direction or axis 298 which extends along the interface where the first repeat unit 280-1 interfaces with the second repeat unit 280-2. It is appreciated that individual repeat units included in the plurality of repeat units 280 are each mirror symmetric along a direction bisecting a respective one of the individual repeat units. For example, the second repeat unit 280-2 is mirror symmetric about axis 297, which bisects the second repeat unit 280-2 or otherwise extends between the two source-follower gate electrodes (e.g., SF1 gate electrodes 215-2 and SF2 gate electrode 216-2), and through the reset gate electrode (e.g., RST gate electrode 230-2) and optionally the dual floating diffusion gate electrode (e.g., DFD gate electrode 235-2) included in the second repeat unit 280-2. It is appreciated that while the second repeat unit 280-2 has mirror symmetry about axis 297, the second repeat unit 280-2 does not have mirror symmetry about a corresponding axis perpendicular to axis 297. In other words, individual repeat units included in the plurality of repeat units 280 may be mirror symmetry about a first axis or first direction while being asymmetric about a second axis or second direction perpendicular to the first axis or first direction (e.g., the second repeat unit 280-2 is asymmetric about an axis that is perpendicular to the axis 297). However, it is still appreciated that while individual repeat units included in the plurality of repeat units 280 may be respectively mirror symmetric and asymmetric along perpendicular directions or about axis (e.g., mirror symmetric about the y-axis and asymmetric about the x-axis based of coordinate system 300), the regular and repeating arrangement of the plurality of repeat units 280 results in symmetry about both the x-axis and the y-axis of the coordinate system 300 (e.g., symmetry where along directions parallel to the x-axis and the y-axis of the coordinate system 300, such as axis 298, where individual repeat units included in the plurality of repeat units 280 interface with an adjacent repeat unit).
It is appreciated that each repeat unit included in the plurality of repeat units 280 further provides internal routing that would normally occur within the metallization region of at least a metal layer for both intra-coupling within a given 16C pixel cell to couple 4C pixel cells included in the given 16C pixel cell and inter-coupling of adjacent 16C pixel cells by virtue of shared gate electrodes and/or common junctions. For example, the first reset transistor and the second reset transistor of the first repeat unit 280-1 have respective drain regions that correspond to a common junction (e.g., a first common junction corresponding to common junction 261-1) that is also shared by the drain regions of the first source-follower transistor and the second source follower transistor and further coupled to receive a supply voltage (e.g., VDD as illustrated). Accordingly, the drain regions of the first source-follower transistor, the second source-follower transistor, the first reset transistor, and the second reset transistor are each coupled together and further coupled to receive the supply voltage. It is appreciated that formation of said common junction is attributed to oxide or isolation structure defined regions (e.g., isolation structure 229) that defines the location of the common junction 261-1 (as well as other common junctions, source, drain, and active regions of components throughout the illustrated embodiment). In some embodiments, formation of said common junction is attributed to oxide or isolation structure defined regions (e.g., isolation structure 229) that further defines the shape of the common junction. For example, a cross-sectional shape of common junction 261-1 that is shared among the first source-follower transistor, the second source-follower transistor, the first reset transistor, and the second reset transistor are at least in part defined by isolation structure 229. Furthermore, common junction 260-1 (e.g., a second common junction formed in the semiconductor substrate 251) couples the source region of the first source-follower transistor (e.g., source-follower transistor associated with SF1 gate 215-1) with drain regions of two adjacent row select transistors (e.g., row select transistors associated with RS1 gate 225-1 and RS2 gate 226-1). Similarly, common junction 260-2 (e.g., a third common junction formed in the semiconductor substrate 251) couples the source region of the second source-follower transistor (e.g., source-follower transistor associated with SF2 gate 216-1) with drain regions of two adjacent row select transistors (e.g., row select transistors associated with RS1 gate 225-2 and RS2 gate 226-2).
Additionally, internal routing that would normally occur within the metallization region for both intra-coupling within a given 16C pixel cell to couple 4C pixel cells included in the given 16C pixel cell and inter-coupling of adjacent 16C pixel cells is further provided by shared gate electrodes of the pixel cell circuitry 255. In the illustrated embodiment, the row select gate electrodes provide coupling between adjacent 16C-pixel cells (e.g., a common row select signal utilized for readout of the adjacent 16C pixel cells). For example, in the illustrated embodiment RS1 gate electrode 225-1 is coupled to source regions 227-1 (e.g., coupled to bitline N−1 included in a plurality of bitlines) and 227-2 (e.g., coupled to bitline N included in the plurality of bitlines that is different than bitline N) of row select transistors associated with different repeat units included in the plurality of repeat units 280 (e.g., to form first and second transistors that have a common gate electrode with active regions defined by isolation structure 229). A similar configuration is also provided by the RS2 gate electrode 226-1 or 226-2 such that adjacent row select transistors of a given repeat unit included in the plurality of repeat units 280 along a vertical direction (e.g., axis 298) have coupled drain regions that are coupled to a source of a source-follower transistor of the given repeating unit enabling selective binning of image data of multiple 16C cells during readout, and adjacent row select transistors of an adjacent repeat unit included in the plurality of repeat units 280 have their gate electrodes coupled together. In other words, the shared gate electrode (e.g., RS1 gate electrode 225-1, RS2 gate electrode 226-1, RS1 gate electrode 225-2, RS2 gate electrode 226-1, or other row select gate electrodes) corresponds to the gate electrode of two different transistors that are disposed on two different repeat units that are adjacently disposed such as repeat units 280-1 and 280-2. In contrast, intra-coupling within a given 16C pixel cell is provided by shared gate electrodes of the reset transistors and the dual floating diffusion transistors. For example, in the illustrated embodiment RST gate electrode 230-1 is coupled to source regions (e.g., correspond to common junctions 262-1 and 262-2) of reset transistors associated with different 4C pixel cells that are within an individual repeat unit (e.g., repeat unit 280-1) included in the plurality of repeat units 280 (e.g., to form first and second transistors that have a common gate electrode with active regions defined by isolation structure 229). Similarly, in the illustrated embodiment DFD gate electrode 235-1 is coupled to source regions 236-1 and 236-2 of dual floating diffusion transistors associated with different 4C pixel cells that are within an individual repeat unit (e.g., repeat unit 280-1) included in the plurality of repeat units 280 (e.g., to form first and second transistors that have a common gate electrode with active regions defined by isolation structure 229).
In some embodiments, the common junctions corresponding to the source/drain regions of reset and dual floating diffusion transistors (e.g., common junctions 262-1 and 262-2) are respectively coupled to different floating diffusion regions. For example, the common junction 262-1 may be coupled to a first floating diffusion region (e.g., the floating diffusion region 121-1 illustrated in
It is appreciated that in some embodiments, the four row select transistors that are positioned adjacent to one another and associated with two adjacent repeat units included in the plurality of repeat units 280 may be referred to as first, second, third, and fourth row select transistors. For example, the first source region 227-1 may form, in part, a first row select transistor, the second source region 227-2 may form, in part, a second row select transistor, the third source region 228-2 may form, in part, a third row select transistor, and the fourth source region 228-1 may form, in part, a fourth row select transistor. The first row select transistor and the fourth row select transistor may be coupled via their drain regions e.g., share a common drain junction. The second row select transistor and the third row select transistor may be coupled via their respective drain regions e.g., common junction 260-1). Accordingly, the first source region (e.g., 227-1) of the first row select transistor and the second source region (e.g., 227-2) are separated from one another by isolation structure 229. Similarly, the third source region (e.g., 228-2) included in the third row select transistor and a fourth source region (e.g., 228-1) included in a fourth row select transistor are separated from one another by isolation structure 229. In the same or different embodiments, the shared or otherwise coupled drain regions of the first row select transistor and the fourth row select transistor and the shared or otherwise coupled drain regions of the second row select transistor and the third row select transistor are also separated and isolated from one another by isolation structure 229. In some embodiments, the coupled first row select transistor and the fourth row select transistor may be included in a repeat unit included in the plurality of repeat units 280 that is arranged adjacent to the first repeat unit 280-1, and the coupled second row select transistor and the third row select transistor may be included in the first repeat unit 280-1.
It is appreciated that the isolation structure 229 may be segmented such that a first isolation structure (e.g., first portion of the isolation structure 229) is disposed between the first source region (e.g., 227-1) and the second source region (e.g., 227-2) and a second isolation structure (e.g., second portion of the isolation structure 229) is disposed between the third source region (e.g., 228-2) and the fourth source region (e.g., 228-1). A third isolation structure (e.g., third portion of the isolation structure 229) is disposed between shared drain regions (e.g., common junction 260-1) of the second and third row select transistors and the shared drain regions (e.g., common junction 261-1) of the first source-follower transistor (e.g., SF1 gate electrode 215-1.
It is further appreciated that the first isolation structure and the second isolation structure of isolation structure 229 in one embodiment may be structured interconnected isolations structure (e.g., oxide-filled trench isolations structure) disposed to provide isolation between i) the first source region (e.g., 227-1) of the first row select transistor and the second source region (e.g., 227-2) of the second row select transistor, and ii). the third source region (e.g., 228-2) of the third row select transistor and the fourth source region (e.g., 228-1) of the fourth row select transistor. In such an embodiment, RS1 gate electrode 225-1 may be referred to as a first shared gate electrode that is coupled to the first source region (e.g., 227-1) of the first row select transistor and the second source region (e.g., 227-2) while RS2 gate electrode 226-1 may be referred to as a second gate electrode that is coupled to the third source region (e.g., 228-2) included in the third row select transistor and the fourth source region (e.g., 228-1) included in the fourth row select transistor.
In the illustrated embodiment, RS1 gate electrode 225-1 and RS2 gate electrode 226-1 each extend longitudinally (i.e., lengthwise) along parallel directions (e.g., directions parallel to the x-axis of coordinate system 300) when the image sensor is viewed from a plan view. In some embodiments, RS1 gate electrode 225-1 and RS2 gate electrode 226-1 each may be disposed on and extended laterally across respective portions of isolation structure 229. In other words, RS1 gate electrode 225-1 and RS2 gate electrode 226-1 may be positioned parallel to one another. Similarly, the shared reset gate electrode (e.g., RST gate electrode 230-1) and the shared dual floating diffusion gate electrode (e.g., DFD gate electrode 235-1) may each extend longitudinally (i.e., lengthwise) along parallel directions (e.g., directions parallel to the x-axis of coordinate system 300), which may further be parallel to the shared row select gate electrodes (e.g., RS1 gate electrodes 225-1 and 225-2 and RS2 gate electrodes 226-1 and 226-2) as well as parallel to source-follower gate electrodes (e.g., SF1 gate electrode 215-1 and SF2 gate electrode 216-1). However, it is appreciated that in some embodiments the source-follower gate electrodes (e.g., SF1 gate electrode 215-1 and SF2 gate electrode 216-1) of a given repeat unit (e.g., first repeat unit 280-1) included in the plurality of repeat units 280 are aligned along a common direction (e.g., such that a line extending parallel to the x-direction of the coordinate system 300 extends across the entire lengths of both SF1 gate electrode 215-1 and SF2 gate electrode 216-1).
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In some embodiments, the pixel cell circuitry 255 can further be described or otherwise segmented into columns (or rows) of row select transistors and ground contact regions (e.g., first segment 285) and columns of source-follower transistors, reset transistors, and optionally dual floating diffusion transistors (e.g., second segment 286). In the illustrated embodiment, the first segment 285 is coupled to the second segment 286 via the corresponding source-follower transistors (e.g., source of source-follower transistors coupled to drains of row select transistors). Instances of the first segment 285 and the second segment 286 may be repeated to form the pixel cell circuitry 255.
The arrangement of components of the pixel cell circuitry 255 is compatible with image sensors submicron pixel pitch, which is provided at least in part by shared components (e.g., shared gate electrodes and/or common junctions) and symmetry (mirror or otherwise) to efficiently utilize the lateral space of the second semiconductor substrate 251. The particular arrangement of components of the pixel cell circuitry 255 further provides reduced fabrication costs by allowing for shared gate electrodes to be utilized for internal routing without the need to additional metal line connections (e.g., reduce the number of metal layers needed during back end of line processing). Further still, the arrangement of components are positioned to facilitate compatibility with foundry design rules such that individual components (e.g., source/drain regions of transistors) may have sizes that are below the critical dimensions set by the design rule requirements of the given technology node. For example, while each individual transistor's required threshold voltage doped region may not meet the foundry's required minimum design dimensions for fabrication, the arrangement of the transistor components allows multiple components to share one threshold voltage doped region meeting the minimum critical dimension. Moreover, implantation for source/drain electrodes may occur after formation of shared gate electrodes such that the gate electrodes may be utilized as self-alignment masks to separate the individual transistor components, while sharing the overall threshold voltage doped region.
Additionally, components are arranged such that lightly doped regions for threshold voltage control may have substantially similar (e.g., within 10% or otherwise based on the manufacturing variance of a given technology node) doping concentrations for adjacent transistors that have the same function (e.g., adjacent source-follower transistors have the same or similar threshold voltage dopant concentration, adjacent row-select transistors have the same or similar threshold voltage dopant concentration that may be different than that of the source-follower transistors threshold voltage dopant concentration and the like). Accordingly, source-follower transistors, row select transistors, reset transistors, and dual floating diffusion transistors of the pixel cell circuitry 255 may have different doping concentrations for threshold voltage control. For example, in the illustrated embodiment a first threshold voltage doped region 271 may be utilized for ion implantation (e.g., before formation of RS1 gate electrode 225-3 and RS2 gate electrode 226-3) to provide substantially equal (e.g., within 10% or otherwise based on manufacturing variance of a given technology node) doping concentrations of dopants to the active regions associated with the row select transistors (e.g., the four row select transistors associated with RS1 gate electrode 225-3 and RS2 gate electrode 226-3). threshold voltage control. In the same or other embodiments, a second threshold voltage doped region 272 may be utilized for ion implantation (e.g., before formation of SF1 gate electrode 215-4 and SF2 gate electrode 216-4) to provide substantially equal (e.g., within 10% or otherwise based on manufacturing variance of a given technology node) doping concentrations of dopants to the active regions associated with the source-follower transistors (e.g., the two source-follower transistors associated with SF1 gate electrode 215-4 and SF2 gate electrode 216-4). In the same or other embodiments, a third threshold voltage doped region 273 may be utilized for ion implantation (e.g., before formation of RST gate electrode 230-4) to provide substantially equal (e.g., within 10% or otherwise based on manufacturing variance of a given technology node) doping concentrations of dopants to the active regions associated with the reset transistors (e.g., the two reset transistors associated with the shared gate electrode RST gate 230-4). In the same or other embodiments, a fourth threshold voltage doped region 274 may be utilized for ion implantation (e.g., before formation of DFD gate electrode 235-4) to provide substantially equal (e.g., within 10% or otherwise based on manufacturing variance of a given technology node) doping concentrations of dopants to the active regions associated with the dual floating diffusion transistors (e.g., the two dual floating diffusion transistors associated with the shared gate electrode DFD gate 235-4).
In the illustrated embodiment, the second semiconductor substrate 251 includes a first side 252 (e.g., front side or backside) and a second side 253 (e.g., a backside or front side). Disposed between the RS1 gate electrode 225 (e.g., a shared gate electrode that forms two row select transistors with respective active regions 275-1 and 275-2 that are defined at least in part by isolation structure 229) is a gate dielectric 258 (e.g., one or more insulating materials such as silicon dioxide, hafnium oxide, or any other insulating material or combination of insulating materials with appropriate properties to form the two row select transistors). The second semiconductor substrate 251 includes a doped region 266 with a first conductivity type (e.g., N-type or P-type) that may be the same or different than the bulk conductivity type of the second semiconductor substrate 251. The second semiconductor substrate 251 further includes a well isolation region 267 having a second conductivity type opposite the first conductivity type (e.g., P-type or N-type). The doped region 266 may form active regions (e.g., active regions 275-1 and 275-2) of transistors (e.g., the two row select transistors in the illustrated embodiments). In some embodiments, a portion (e.g., first threshold voltage doped region 271) of the doped region 266 proximate to the first side 252 of the second semiconductor substrate 251 may be lightly doped (e.g., N-type or P-type) to provide threshold voltage control of the transistors associated with the underlying gate electrode (e.g., the two row select transistors associated with RS1 gate electrode 225). Accordingly, respective active regions 275-1 and 275-2 included in the two row select transistors include dopants proximate to the first side 252 of the second semiconductor substrate 251 to respectively adjust a threshold voltage of the two row select transistors of the adjacently disposed first and second 16C pixel cells. As illustrated the dopants of the threshold voltage doped region 271 are disposed between the RS1 gate electrode 225 and the second side 253 of the second semiconductor substrate 251. In the illustrated embodiment, the isolation structure 229 is structured to separate the active region 275-1 from the active region 275-2 (e.g., to form two separate active regions and thus two separate row select transistors).
In the illustrated embodiment, the RS1 gate electrode 225 directly contacts the gate dielectric 258 and is formed within inter-layer dielectric (ILD) 263. It is appreciated ILD 263 is closer to the first side 252 of the second semiconductor substrate 251 than any other ILD included in the metallization region 209. In other words, the RS1 gate electrode 225 provides internal routing for the second semiconductor substrate 251 and is disposed closer to the first side 252 than any metal layer (e.g., metal 1, metal 2, and so on) included in the metallization region 209. It is appreciated that the RS1 gate electrode 225 may be formed of polycrystalline silicon or other conductive material or combination of materials with sufficient conductivity to function as a shared gate electrode for the two row select transistors associated with active regions 275-1 and 275-2. The RS1 gate electrode 255 as illustrated is disposed across the area of the first and second 16C pixel cells. For example, RS1 gate electrode 255 may be formed partly on isolation structure 229 (e.g., first isolation structure segment) that is disposed in the semiconductor substrate 251 within a given pixel region associated first 16C pixel cell, and extends over to have part formed on isolation structure 229 (e.g., second isolation structure segment) that is disposed in the semiconductor substrate 251 within a given pixel region associated second 16C pixel cell.
The RS1 gate electrode 225 is coupled to metal wire 231-1 (e.g., a first metallization layer corresponding to a metal 1 layer) via one or more contact vias 233 disposed within ILD 263. Specifically, the contact vias 263 extend from the metal wire 231-1 to the RS1 gate electrode 225 to couple the RS1 gate electrode 225 to the metal wire 231-1. The metal wire 231-1 is disposed within the inter-metal dielectric (IMD) 264, which is further coupled to receive a row select control signal for activating or deactivating the row select transistors associated with the RS1 gate electrode 225 of both first and second 16C pixel cells. As illustrated the ILD 263 is disposed proximate to the first side 252 of the second semiconductor substrate 251. In the illustrated embodiment, the ILD 263 at least partially encapsulates the RS1 gate electrode 225 (e.g., ILD 263 directly contacts RS1 gate electrode 225). In the illustrated embodiment, the ILD 263 is disposed between the IMD 264 and the first side 252 of the second semiconductor substrate 251.
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The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
