This U.S. patent application claims priority under 35 U.S.C. 119(a) to Korean Patent Application No. 10-2022-0168873 filed on Dec. 6, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.
The present disclosure relates to an image sensor.
An image sensor is a semiconductor-based sensor which receives light and generates a electrical signal based on the received light. Examples of the image sensor include a charge-coupled device (CCD) sensor and a complementary metal-oxide-semiconductor (CMOS) sensor.
The image sensor may include a pixel array having a plurality of pixels and a logic circuit for driving the pixel array and generating an image. Each of the plurality of pixels may include a photodiode and a pixel circuit for converting electric charges generated in the photodiode into the electrical signal. Some of the pixels may additionally provide an auto focus function. However, a cross-talk phenomenon may occur that causes degradation of the auto focus function.
An aspect of the present disclosure may provide an image sensor having increased auto focusing characteristics.
According to an aspect of the present disclosure, an image sensor includes: a chip structure, a grid structure, and color filter regions. The chip structure includes normal pixel regions (e.g., normal pixels) and auto focus pixel regions (e.g., auto focus pixels). The grid structure is disposed on the chip structure. The color filter regions are defined by the grid structure over the chip structure. The color filter regions include normal filter regions and auto focus filter regions. The normal filter regions correspond to the normal pixel regions. One auto focus filter region among the auto focus filter regions corresponds to at least two auto focus pixel regions disposed adjacent to each other among the auto focus pixel regions. The chip structure include a first region spaced from a central region of a pixel array region of the chip structure by a first distance, and a second region spaced from the central region of the pixel array region of the chip structure by a second distance greater than the first distance. The auto focus filter regions include a first auto focus filter region disposed on the first region and a second auto focus filter region disposed on the second region. A first width of a first grid portion disposed adjacent to the first auto focus filter region among the grid structure is narrower than a second width of a second grid portion disposed adjacent to the second auto focus filter region among the grid structure.
According to an aspect of the present disclosure, an image sensor includes: a chip structure, a grid structure, and color filter regions. The chip structure includes normal pixel regions and auto focus pixel regions. The grid structure is disposed on the chip structure. The color filter region are defined by the grid structure over the chip structure. The color filter regions including normal filter regions and auto focus filter regions. The normal filter regions correspond to the normal pixel regions. One auto focus filter region among the auto focus filter regions corresponds to at least two auto focus pixel regions disposed adjacent to each other among the auto focus pixel regions. The chip structure includes a first region spaced from a central region of a pixel array region of the chip structure by a first distance, and a second region spaced from the central region of the pixel array region of the chip structure by a second distance greater than the first distance. The auto focus filter regions include a first auto focus filter region disposed on the first region and a second auto focus filter region disposed on the second region. A first length of the first auto focus filter region in a first horizontal direction is shorter than a second length of the second auto focus filter region in the first horizontal direction.
According to an aspect of the present disclosure, an image sensor includes: a first chip structure, a second chip structure, a grid structure, color filter regions, and micro lens regions. The first chip structure includes a first substrate and a first circuit element disposed on the first substrate. The second chip structure is disposed on the first chip structure, and includes a second substrate including normal pixel regions and auto focus pixel regions and a second circuit device between the second substrate and the first chip structure. The grid structure is disposed on the second chip structure. The color filter regions are defined by the grid structure over the second chip structure. The micro lens regions are disposed on the color filter regions. The color filter regions include normal filter regions and auto focus filter regions. The normal filter regions correspond to the normal pixel regions. One auto focus filter region among the auto focus filter regions corresponds to at least two auto focus pixel regions disposed adjacent to each other among the auto focus pixel regions. The second chip structure includes a first region spaced from a central region of a pixel array region of the second chip structure by a first distance, and a second region spaced from the central region of the pixel array region of the chip structure by a second distance greater than the first distance. The auto focus filter regions include a first auto focus filter region disposed on the first region and a second auto focus filter region disposed on the second region. A first width of a first grid portion defining a side surface of the first auto focus filter region in a first horizontal direction among the grid structure is narrower than a second width of a second grid portion defining a side surface of the second auto focus filter region in the first horizontal direction among the grid structure.
The present disclosure may provide an image sensor with increased auto focus characteristics by providing a grid structure formed to increase a width of a grid portion near the auto focus pixel region as it moves away from a central region of the pixel array region. However, effects of the present application are not limited thereto.
The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings. Hereinafter, it may be understood that the expressions such as “on,” “above,” “upper,” “below,” “beneath,” “lower,” and “side,” merely indicated based on drawings, except that they are indicated by drawings and referred to separately. Terms such as “upper,” “immediate,” and “lower” may be replaced with other terms such as “first,” “second,” and “third” and be used to describe components of the present disclosure. The terms such as “first,” “second,” and “third” may be used to describe various components, but the components are not limited thereto, and a “first component” may be referred to as a “second component.”
Referring to
The pixel array 10 may include a plurality of pixels PX arranged in an array form along a plurality of rows and a plurality of columns. Each of the plurality of pixels PX may include at least one photoelectric conversion element for generating an electric charge in response to light, and a pixel circuit for generating a pixel signal corresponding to the electric charge generated by the photoelectric conversion element. The photoelectric conversion device may include a photodiode formed of a semiconductor material, and/or an organic photodiode formed of an organic material.
In an example embodiment, the pixel circuit may include a floating diffusion, a transmission transistor, a reset transistor, a driving transistor, a select transistor, and the like. The configuration of the plurality of pixels PX may vary according to example embodiments. For example, each of the plurality of pixels PX may include an organic photodiode including an organic material, or may be implemented as digital pixels. When the plurality of pixels PX are implemented as the digital pixels, each of the pixels PX may include an analog-to-digital converter for outputting a digital pixel signal.
The logic circuit 20 may include circuits for controlling the pixel array 10. For example, the logic circuit 20 may include a row driver 21 (e.g., a row driver circuit), a readout circuit 22, a column driver 23 (e.g., a column driver circuit), and a control logic 24 (e.g., a logic circuit). The row driver 21 may drive the pixel array 10 in units of row lines. For example, the row driver 21 may generate a transmission control signal for controlling the transmission transistor of the pixel circuit, a reset control signal for controlling the reset transistor, and a select control signal for controlling the select transistor and input these signals into the pixel array 10 in units of row lines.
The readout circuit 22 may include a correlated double sampler (CDS) and an analog-to-digital converter (ADC). The correlated double samplers may be connected to the plurality of pixels PX through column lines. The correlated double samplers may read a pixel signal through the column lines from a pixel PX connected to a row line selected by a row line select signal of the row driver 21. The analog-to-digital converter may convert the pixel signal detected by the correlated double sampler into a digital pixel signal and transmit the digital pixel signal to the column driver 23.
The column driver 23 may include a latch or a buffer circuit and an amplification circuit configured to temporarily store a digital pixel signal, and may process the digital pixel signal received from the readout circuit 22. The row driver 21, the readout circuit 22, and the column driver 23 may be controlled by the control logic 24. The control logic 24 may include a timing controller for controlling operation timings of the row driver 21, the readout circuit 22, and the column driver 23.
Pixels PX disposed at the same position in a horizontal direction among the plurality of pixels PX may share the same column line. For example, pixels PX disposed at the same position in a vertical direction among a plurality of pixels PX may be simultaneously selected by the row driver 21 and may output pixel signals through the column lines. For example, the readout circuit 22 may simultaneously obtain the pixel signals from the plurality of pixels PX selected by the row driver 21 through the column lines. The pixel signal may include a reset voltage and a pixel voltage, and the pixel voltage may be a voltage at which electric charges generated in response to light in each of the plurality of pixels PX are reflected in the reset voltage.
In an example embodiment, referring to
The photodiode PD may generate and accumulate the electric charges in response to light incident from the outside. The pixel circuit may further include a floating diffusion region FD in which the electric charges generated from the photodiode PD are accumulated.
The photodiode PD may be replaced with a phototransistor, a photogate, or a pinned photodiode according to example embodiments. In the present disclosure, the photodiode PD may be referred to and described as an “optical conversion element.” The photoelectric conversion element may include a photo diode, a photo transistor, a photo gate, or a pinned photo diode.
The transmission transistor TX may transfer the electric charges generated from the photodiode PD to the floating diffusion region FD. The floating diffusion region FD may store the electric charges generated from the photodiode PD. A voltage output by the driving transistor DX may vary depending on the amount of electric charges accumulated in the floating diffusion region FD.
The reset transistor RX may reset a voltage of the floating diffusion region FD by removing the electric charges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode may be connected to a power voltage VDD. When the reset transistor RX is turned on, the power voltage VDD connected to the source electrode of the reset transistor RX is applied to the floating diffusion region FD, and electric charges accumulated in the floating diffusion region FD may be removed.
The driving transistor DX may operate as a source follower buffer amplifier. The driving transistor DX may amplify a voltage change of the floating diffusion region FD and output the amplified voltage change to one of the column lines COL1 and COL2. The select transistor SX may select pixels PX to be read in units of rows. When the select transistor SX is turned on, a voltage of the driving transistor DX may be output to one of the column lines COL1 and COL2. When the select transistor SX is turned on, the reset voltage or the pixel voltage may be output through the column lines COL1 and COL2.
In an example embodiment illustrated in
In a modified example embodiment, referring to
In an example embodiment, a first photodiode PD1 and a first transmission transistor TX1 of a first pixel may be connected to the floating diffusion region FD. Similarly, second to fourth photodiodes PD2 to PD4 of second to fourth pixels may be connected to the floating diffusion region FD through second to fourth transmission transistors TX2 to TX4.
As one example, the floating diffusion regions FD included in each of the pixels may be connected to each other by a wiring pattern, and the first to fourth transmission transistors TX1 to TX4 may be commonly connected to one floating diffusion region FD.
As another example, the floating diffusion regions FD included in each of the pixels may form one region in a substrate that may be formed of a semiconductor material.
The pixel circuit may include the reset transistor RX, the first and second driving transistors DX1 and DX2, and the select transistor SX. The reset transistor RX may be controlled by a reset control signal RG, and the select transistor SX may be controlled by a select control signal SEL. For example, each of the four pixels may further include one transistor in addition to the transmission transistor TX. Two of the four transistors included in the four pixels may be connected to each other in parallel to supply the first and second driving transistors DX1 and DX2, one of the remaining two transistors may be supplied as the select transistor SX, and the other thereof may be supplied as the reset transistor RX.
The pixel circuit described with reference to
Referring to
The chip structure 13 may have pixel regions PDn and PDaf. The pixel regions PDn are normal pixel regions and the pixel regions PDaf are auto focus pixel regions. For example, the normal pixel regions may include normal pixels and the auto focus pixel regions may include auto focus pixels. Each of the auto focus pixel regions PDaf may be pixel regions configured to perform an auto focusing function. The normal pixel regions PDn may refer to the remaining pixel regions except the auto focus pixel regions PDaf. The normal pixel regions PDn may be, for example, regions including the photodiode PD described in
The chip structure 13 may further include a separation structure 215 (e.g., separation layers) defining the pixel regions PDn and PDaf. Each of the normal pixel regions PDn, each of the auto focus pixel regions PDaf, and the normal pixel regions PDn and the auto focus pixel regions PDaf may be spaced from each other by the separation structure 215. The separation structure 215 may be disposed to surround each of the pixel regions PDn and PDaf. In an embodiment, the separation structure 215 includes or is an insulating material, and the number of layers constituting the separation structure 215 may be variously changed.
The insulating structure 240 may be formed to have a conformal thickness on the chip structure 13. The insulating structure 240 may include an antireflection layer configured to prevent reflection of light that may be caused by a sudden change in a refractive index on a surface of the chip structure 13. The insulating structure 240 may include an antireflection layer that may provide light incident by adjusting the refractive index so that light is emitted from the pixel regions PDn and PDaf with a high transmittance. The insulating structure 240 may be referred to as an antireflection structure or an antireflection layer. The number of layers constituting the insulating structure 240 may be variously changed.
The grid structure 250 may be disposed on the insulating structure 240. The grid structure 250 may include an insulating material or a conductive material of the grid structure 250 on the insulating structure 240. For example, the grid structure 250 may include a first layer including at least one of a metal such as Ti, Ta and W, or a metal nitride such as TiN and TaN, and a second layer including a low refractive index (LRI) material (e.g., an oxide or nitride including Si, Al Ehsms, or combinations thereof, an silicon oxide having a porous structure, or silica nanoparticles having a network structure). However, the material constituting the grid structure 250 and the number of layers constituting the grid structure 250 may be variously changed.
The color filters CF may be disposed over the insulating structure 240. The color filters CF may allow light at a specific wavelength to pass and reach the pixel regions PDn and PDaf. The color filters CF may include color filters of different colors. For example, each of the color filters CF may be one of a green color filter, a blue color filter, and a red color filter.
The color filters CF may include color filter regions 260 defined by the grid structure 250. The color filter regions 260 may include normal filter regions 260n corresponding to the normal pixel regions PDn and auto focus filter regions 260af corresponding to the auto focus pixel regions PDaf.
As one example, one normal filter region 260n of the normal filter regions 260n may correspond to N normal pixel regions, and one auto focus filter region 260af of the auto focus filter regions 260af may correspond to at least M auto focus pixel regions disposed adjacent to each other. N and M may be different natural numbers, and M may be greater than N. For example, each of the normal filter regions 260n may correspond to one normal pixel region PDn, and each of the auto focus pixel regions 260af may correspond to two adjacent auto focus pixel regions PDaf (e.g., first and second phase difference detection regions AF1 and AF2). In an embodiment, each of the auto focus filter regions 260af may have a form in which a first portion 260af_1 corresponding to the first phase difference detection region AF1 and a second portion 260af_2 corresponding to the second phase difference detection region AF2 are integrally connected to each other. In an embodiment, the first portion 260af_1 includes the same color filter as the second portion 260af_2. The color filter may be, for example, a green filter. The grid structure 250 may surround external sides of the first portion 260af_1 and the second portion 260af_2 without being disposed between the first portion 260af_1 and the second portion 260af_2.
In an example embodiment, the color filter regions 260 have a portion extending onto an upper surface of the grid structure 250. For example, the color filter regions 260 may extend on the upper surface of the grid structure 250. Accordingly, the upper surface of each of the color filters CF may be disposed at a higher level than the upper surface of the grid structure 250.
The micro lenses MF may be disposed on the color filters CF. Each of the micro lenses ML may have a convex shape in a direction moving away from the chip structure 13. The micro lenses ML may concentrate incident light to the pixel regions PDn and PDaf. The micro lenses ML may be formed of a transparent photoresist material or a transparent thermosetting resin material. For example, the micro lenses (ML) may be formed of a TMR-based resin (produced by Tokyo Ohka Kogo, Co.) or an MFR-based resin (produced by Japan Synthetic Rubber Corporation), but the present disclosure is not limited to these materials.
The micro lenses MF may include micro lens regions 270 corresponding to each of the color filter regions 260. The micro lens regions 270 may include normal lens regions 270n corresponding to the normal filter regions 260n and auto focus lens regions 270af corresponding to the auto focus filter regions 260af. In an exemplary embodiment, each of the normal lens regions 270n correspond to one normal filter region 260n, and each of the auto focus lens regions 270af correspond to one auto focus filter region 260af. In an embodiment, a size or area of each of the normal lens regions 270n is smaller than a size or area of each of the auto focus lens regions 270af. For example, a first length of each of the normal lens regions 270n in an X-direction may be shorter than a second length of each of the auto focus lens regions 270af in the X-direction. The second length may be in a range between about 1.5 times and about 2.5 times greater than the first length. This may be because the first length is a length of a region corresponding to one normal pixel region PDaf, and the second length is a length of a region corresponding to two auto focus pixel regions PDaf (e.g., the first and second phase difference detection regions AF1 and AF2).
In an example embodiment, the auto focus pixel regions PDaf includes a first phase difference detection region AF1 and a second phase difference detection region AF2 disposed adjacent to each other in a first horizontal direction, for example, in the X-direction. The first phase difference detection region AF1 and the second phase difference detection region AF2 may form an auto focus group, as one unit for performing an auto focus function. In an embodiment, the automatic focus function is performed using a sensitivity difference between the first phase difference detection region AF1 and the second phase difference detection region AF2. For example, the auto focus function may be performed using the sensitivity difference between the first and second phase difference detection regions AF1 and AF2 according to light incident at a certain angle with the first horizontal direction. Performance of the auto focus function may increase with an increase in the sensitivity difference between the first and second phase difference detection regions AF1 and AF2. The first chip structure 13 may include a plurality of auto focus groups, and each of the auto focus groups may be surrounded by the normal pixel regions PDn on a plane.
In an example embodiment, the chip structure 13 includes a first region R1 spaced from a central region CR of the pixel array region of the chip structure 13 by a first distance, a second region R2 spaced from the central region CR of the pixel array region of the chip structure 13 by a second distance, and a third region R3 spaced from the central region CR of the pixel array region of the chip structure 13 by a third distance greater than the second distance. In the present specification, each of the first to third regions R1, R2 and R3 may refer to a region in a predetermined range including a portion spaced from the central region CR of the pixel array region of the chip structure 13 by the first to third distances. The central region CR may be disposed at a center of the pixel array region. The auto focus pixel regions PDaf may include a first auto focus group including first auto focus pixel regions PDaf1 disposed in the first region R1, a second auto focus group including second auto focus pixel regions PDaf2 disposed in the second region R2, and a third auto focus group including third auto focus pixel regions PDaf3 disposed in the third region R3. Each of the first to third auto focus groups may perform the auto focus function. However, directions of light incident to perform the automatic focus function may be different from each other in the first to third regions R1, R2 and R3. This may be because light is incident toward the chip structure 13 from a point-shaped light source disposed above a Z-direction perpendicular to the central region CR of the pixel array region of the chip structure 13.
The auto focus filter regions 260af may include a first auto focus filter region 260af1 disposed on the first region R1, a second auto focus filter region 260af2 disposed on the second region R2, and a third auto focus filter region 260af3 disposed on the third region R3. In an example embodiment, the first auto focus filter region 260af1 corresponds to the first auto focus group, the second auto focus filter region 260af2 corresponds to the second auto focus group, and the third auto focus filter region 260af3 corresponds to the third auto focus group.
The auto focus lens regions 270af may include a first auto focus lens region 270af1 disposed on the first region R1, a second auto focus lens region 270af2 disposed on the second region R2, and a third auto focus lens region 270af3 disposed on the third region R3. In an example embodiment, the first auto focus lens region 270af1 corresponds to the first auto focus filter region 260af1, the second auto focus lens region 270af2 may correspond to the second auto focus filter region 260af2, and the third auto focus lens region 270af3 corresponds to the third auto focus filter region 260af3.
The grid structure 250 may include a first grid portion 250_P1 disposed adjacent to the first auto focus filter region 260af1, a second grid portion 250_P2 disposed adjacent to the second auto focus filter region 260af2, and a third grid portion 250_P3 disposed adjacent to the third auto focus filter region 260af3.
In an exemplary embodiment, the first grid portion 250_P1 is a region defining at least a portion of side surfaces of the first auto focus filter region 260af1, for example, a side surface in the X-direction, the second grid portion 250_P2 is a region defining at least a portion of side surfaces of the second auto focus filter region 260af2, for example, a side surface in the X-direction, and the third grid portion 250_P3 is a region defining at least a portion of side surfaces of the third auto focus filter region 260af3, for example, a side surface in the X-direction.
In an exemplary embodiment, the first grid portion 250_P1 is a portion of the grid structure 250 disposed between the first auto focus filter region 260af1 and the normal filter region 260n disposed adjacent to the first auto focus filter region 260af1 in the X-direction, the second grid portion 250_P2 is a portion of the grid structure 250 disposed between the second auto focus filter region 260af2 and the normal filter region 260n disposed adjacent to the second auto focus filter region 260af2 in the X-direction, and the third grid portion 250_P3 is a portion of the grid structure 250 disposed between the third auto focus filter region 260af3 and the normal filter region 260n disposed adjacent to the third auto focus filter region 260af3 in the X-direction.
In an embodiment, a first width w1 of the first grid portion 250_P1 is narrower or smaller than a second width w2 of the second grid portion 250_P2, and the second width w2 of the second grid portion 250_P2 is narrower or smaller than a third width w3 of the third grid portion 250_P3. The first width w1 may be defined as a distance between the first portion 260af_1 of the first auto focus filter region 260af1 and the normal filter region 260n disposed adjacent to the first portion 260af_1 in the X-direction, or a distance between the second portion 260af_2 of the first auto focus filter region 260af1 and the normal filter region 260n disposed adjacent to the second portion 260af_2 in the X-direction.
When light is incident to perform the auto focus function, a cross talk phenomenon may occur in which light incident on the normal filter region 260n disposed adjacent to the auto focus filter region 260af enters an auto focus pixel region PDaf corresponding to the auto focus filter region 260af. Due to such a crosstalk phenomenon, a sensitivity difference between the first and second phase difference detection regions AF1 and AF2 may be reduced to deteriorate the auto focus function. With an increase in the width of the grid structure 250 disposed between the auto focus filter region 260af and the normal filter region 260n, the cross talk phenomenon may be reduced, but the amount of light incident into the pixel regions PDn and PDaf may deteriorate.
The directions of the light incident to perform the auto focus function may be different from each other in the first to third regions R1, R2 and R3, and the cross talk phenomenon may increase toward a region far from the central portion CR of the pixel array region of the chip structure 13. As the widths of the grid structures 250 on the first to third regions R1, R2, and R3 are differently adjusted, the cross talk phenomenon may be reduced, and the image sensor 1 having the auto focus function with an increased performance or quality may be provided. For example, the second grid portion 250_P2 having the second width w2 greater than the first width w1 of the first grid portion 250_P1 may be provided on the second region R2 farther than the first region R1, thereby increasing performance or quality of the auto focus function of each of the auto focus groups as a whole.
The grid structure 250 may include a fourth grid portion 250_P4 between the adjacent normal filter regions 260n, and the fourth grid portion 250_P4 has a fourth width w4. In an embodiment, the fourth width w4 is narrower or smaller than at least one of the first to third widths w1, w2 and w3. In an exemplary embodiment, the fourth width w4 is identical to or substantially identical to the first width w1 and is illustrated as being narrower or smaller than the second width w2 and the third width w3, but is not limited thereto as described below in
In an exemplary embodiment, the grid structure 250 includes a fifth grid portion 250_P5 disposed between the first auto focus filter region 260af1 and the normal filter region 260n disposed adjacent to the first auto focus filter region 260af1 in a Y-direction, a sixth grid portion 250_P6 disposed between the second auto focus filter region 260af2 and the normal filter region 260n disposed adjacent to the second auto focus filter region 260af2 in the Y-direction, and a seventh grid portion 250_P7 disposed between the third auto focus filter region 260af3 and the normal filter region 260n disposed adjacent to the third auto focus filter region 260af3 in the Y-direction. The fifth grid portion 250_P5 may have a fifth width w5, the sixth grid portion 250_P6 may have a sixth width w6, and the seventh grid portion 250_P7 may have a seventh width w7. In an exemplary embodiment, the fifth width w5, the sixth width w6, and the seventh width w7 are identical to or substantially identical to each other, but may be different from each other as described below in
In an exemplary embodiment, on a plane, a first distance misaligned between a central region of the first auto focus filter region 260af1 and a central region of the second auto focus lens region 270af1 is shorter than a second distance misaligned between a central region of the second auto focus filter region 260af2 and a central region of the second auto focus lens region 270af2. In an embodiment, the second distance is shorter than a third distance misaligned between a central region of the third auto focus filter region 260af3 and a central region of the third auto focus lens region 270af3. This may be because the directions of light incident to perform the automatic focus function are different from each other in the first to third regions R1, R2 and R3, as described above.
In an example embodiment, a first length d1 of the first auto focus filter region 260af1 in the X-direction is shorter than a second length d2 of the second auto focus filter region 260af2 in the X-direction, and the second length d2 is shorter than a third length d3 of the third auto focus filter region 260af3. This may be because the first to third grid portions 250_P1, 250_P2 and 250_P3 are formed to adjust the size of the auto focus filter regions 260af while uniformly maintaining the size of the adjacent normal filter regions 250n as illustrated in
Next, various modifications of an image sensor according to example embodiments will be described with reference to
Referring to
Referring to
Referring to
In a grid structure 250c, a first width w1″ of the first grid portion 250_P1 defining a side surface of the first auto focus filter region 260af1 in the X-direction may be identical to or substantially identical to a fifth width w5″ of the fifth grid portion 250_P5 defining a side surface of the first auto focus filter region 260af1 in the Y-direction.
In the grid structure 250c, the first width w1″ of the first grid portion 250_P1 defining the side surface of the first auto focus filter region 260af1 in the X-direction may be narrower or smaller than a second width w2″ of the second grid portion 250_P2 defining a side surface of the second auto focus filter region 260af2 in the X-direction. The second width w2″ may be narrower or smaller than a third width w3″ of the third grid portion 250_P3 defining a side surface of the third auto focus filter region 260af3 in the X-direction.
Referring to
Referring to
Referring to
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The first chip structure 103 may include a first substrate 106, an element separation film 109s defining an active region 109a on the first substrate 106, a first circuit element 112 and a first wiring structure 115 disposed over the first substrate 106, and a first insulating structure 118 covering the first circuit element 112 and the first wiring structure 115 over the first substrate 106.
The first substrate 106 may be a semiconductor substrate. The first substrate 106 may be a substrate formed of a semiconductor material, for example, a single crystalline silicon substrate. The first circuit element 112 may include an element such as a transistor including a gate 112a and a source/drain 112b.
The second chip structure 203 may include a second substrate 206, an element separation film 218 disposed in the second substrate 206 and limiting an active region, a second circuit element 224 and a second wiring structure 227 disposed between the second substrate 206 and the first chip structure 103, and a second insulating structure 230 covering the second circuit element 224 and the second wiring structure 227 between the second substrate 206 and the first chip structure 103. The second chip structure 203 may further include normal pixel regions PDn and a separation structure 215 in the second substrate 206. In a region not illustrated, the second chip structure 203 may include auto focus pixel regions PDaf (see
The second substrate 206 may have a first surface 206S1 and a second surface 206S2 facing the first surface 206S1. The first surface 206S1 of the second substrate 206 may face the first chip structure 103. The second substrate 206 may be a semiconductor substrate. The second substrate 206 may be a substrate formed of a semiconductor material, for example, a single crystalline silicon substrate.
The element separation film 218 may be disposed on the first surface 206S1 of the second substrate 206 and may limit the active region. The element separation film 218 may be formed of an insulating material such as silicon oxide.
The second circuit element 224 and the second wiring structure 227 may be disposed between the first surface 206S1 of the second substrate 206 and the first chip structure 103.
The second circuit element 224 may include a transfer gate TG and active elements 221. The active elements 221 may be transistors including a gate 221a and a source/drain 221b. The transfer gate TG may transfer electric charges from an adjacent normal pixel region PDn to an adjacent floating diffusion region. The active elements 221 may be various transistors of the pixel circuit described in
The transfer gate TG may be a vertical transfer gate including a portion extending from the first surface 206S1 of the second substrate 206 to an interior of the second substrate 206.
The second wiring structure 227 may include multi-layered wirings disposed at different height levels and vias configured to electrically connect the multi-layered wirings and electrically connect the multi-layered wirings to the second circuit element 224.
The second insulating structure 230 may cover the second circuit element 224 and the second wiring structure 227 between the first surface 206S1 of the second substrate 206 and the first chip structure 103.
The second insulating structure 230 may be in contact with and bonded to the first insulating structure 118. Each of the first and second insulating structures 118 and 230 may be formed of multiple layers including different types of insulating layers. For example, the second insulating structure 230 may be formed of multiple layers including at least two or more of a silicon oxide layer, a low dielectric layer, and a silicon nitride layer.
The normal pixel regions PDn may generate and accumulate electric charges corresponding to incident light. The normal pixel regions PDn may include, for example, a photo diode, a photo transistor, a photo gate, a pinned photo diode (PPD), and combinations thereof. The normal pixel regions PDn may include first to third normal pixel regions on which light of different colors is incident, and an arrangement relationship thereof may be variously changed according to example embodiments.
The separation structure 215 may be disposed to surround each of the normal pixel regions PDn. The separation structure 215 may vertically penetrate through at least a portion of the second substrate 206. For example, the separation structure 215 may vertically penetrate through the second substrate 206. The separation structure 215 may be connected to the element separation film 218. The separation structure 215 may include a separation pattern 213b and a separation insulating layer 213a covering a side surface of the separation pattern 213b. For example, the separation insulating layer 213a may surround or enclose the separation pattern 213b. For example, the separation insulating layer 215a may include silicon oxide, and the separation pattern 213b may include polysilicon. However, according to an example embodiment, the number of layers of the separation structure 215 may be variously changed.
The image sensor 1000 may include an insulating structure 240 disposed on the second chip structure 203. The insulating structure 240 may include a plurality of layers sequentially stacked. For example, the insulating structure 240 may include a lower layer 240a and an upper layer 240b disposed on the lower layer 240a. In an embodiment, the lower layer 240a has permeability at a visible wavelength and may include a material that has a negative charge to prevent a charge by means of a dangling bond of the second surface 206S2 of the second substrate 206. In an embodiment, the upper layer 240b includes a first upper material layer configured to have the permeability at the visible wavelength and adjust a peak of the permeability by adjusting a thickness thereof, and a second upper material layer configured to have the permeability at the visible wavelength and perform passivation. The lower layer 240a may include a high-k dielectric, for example, aluminum oxide, and the upper layer 240b may include at least one high-k dielectric layer and at least one silicon oxide layer.
The image sensor 1000 may include a grid structure 250 disposed on the insulating structure 240. The grid structure 250 may include a plurality of layers sequentially stacked, for example, a first layer 250a and a second layer 250b disposed on the first layer 250a. In an embodiment, a thickness of the second layer 250b is greater than that of the first layer 250a. In an embodiment, a first material of the first layer 250a is different from a second material of the second layer 250b. As an example, the first material of the first layer 250a may include or be a conductive material. For example, the first layer 250a may be formed of the conductive material including at least one of a metal or a metal nitride. For example, the first layer 250a may include at least one of Ti, Ta, TiN, TaN, or W. As an example, the second material of the second layer 250b may include an insulating material. The second material of the second layer 250b may be a low refractive index (LRI) material. For example, the second layer 250b may have a refractive index ranging from about 1.1 to about 1.8. The second layer 250b may include an oxide or a nitride including Si, Al, or combinations thereof. For example, the second layer 250b may include silicon oxide having a porous structure or silica nanoparticles having a network structure. The first layer 250a formed of a conductive material may serve as a charge path for removing a charge, and the second layer 250b may be formed of a low refractive index (LRI) material without including a conductive material that may reduce sensitivity in the pixel regions, thereby reducing an optical cross-talk phenomenon of the image sensor 1000. As described with reference to
The image sensor 1000 may include color filters CF covering the grid structure 250 on the insulating structure 240. The color filters CF may include first to third color filters CF1, CF2 and CF3 of different colors. For example, the first color filter CF1 may be a green color filter, the second color filter CF2 may be a blue color filter, and the third color filter CF3 may be a red color filter. The color filters CF may include color filter regions 260n and 260af defined by the grid structure 250 as described in
The image sensor 1000 may further include micro lenses MF disposed on the color filters CF. The micro lenses MF may include lens regions 270n and 270af as described with reference to
The method of
The first chip structure 103 including the first circuit element 112 may be formed. An element separation film 109s limiting an active region 109a may be formed on the first substrate 106, and the first circuit element 112 may be formed over the first substrate 106. Next, a first wiring structure 115 electrically connected to the first circuit element 112 and a first insulating structure 118 covering the first circuit element 112 and the first wiring structure 115 may be formed over the first substrate 106. In an exemplary embodiment, the first wiring structure 115 and the first insulating structure 118 may be formed to be divided several times so that the first wiring structure 115 may include wiring lines disposed at a plurality of levels. The first circuit element 112 and the first wiring structure 115 may be referred to as a circuit wiring structure.
The second chip structure 203 including pixel regions PDn and PDaf may be formed. For example, the second chip structure 203 may be formed on the first chip structure 103. Forming the second chip structure 203 may include forming the separation structure 215 and the pixel regions PDn and PDaf in the second substrate 206, forming the element separation film 218 limiting the active region on the first surface 206S1 of the second substrate 206, forming the second circuit element 224 on the first surface 206S1 of the second substrate 206, and forming the second wiring structure 227 and the second insulating structure 230 covering the second circuit element 224 and the second wiring structure 227 on the first surface 206S1 of the second substrate 206. The order of forming the separation structure 215, the pixel regions PDn and PDaf, and the element separation film 218 may be variously modified. In one example, two auto focus pixel regions PDaf are disposed adjacent to each other in the X-direction, and normal pixel regions PDn are disposed to surround the two auto focus pixel regions PDaf, but an arrangement relationship of the pixel regions PDn and PDaf may be variously changed.
The chip structure 13 may be formed by bonding the first chip structure 103 and the second chip structure 203. For example, the first chip structure 103 may be bonded to the second chip structure 203. In an example embodiment, the chip structure 13 may be formed by performing a wafer bonding process of bonding two wafers. Accordingly, the first insulating structure 118 of the first chip structure 103 and the second insulating structure 230 of the second chip structure 203 may be bonded to each other. For example, the separation structure 215 may be exposed by performing a grinding process of reducing a thickness of the second substrate 206.
Next, an insulating structure 240 may be formed on the chip structure 13, and a grid structure 250 having different widths for each region may be formed on the insulating structure 240 (S20). For example, the grid structure 250 having different widths may be formed on the chip structure 13.
The insulating structure 240 may be formed on the second surface 206s2 of the second substrate 206, conductive materials and insulating materials may be sequentially deposited, and then the grid structure 250 may be formed to have a mesh shape on the insulating structure 240 through a patterning process. The grid structure 250 may be formed to have different widths for each region through the patterning process.
In an example embodiment, the chip structure 13 includes a first region R1 spaced from the central region CR of the pixel array region of the chip structure 13 by a first distance, a second region R2 spaced from the central region CR of the pixel array region of the chip structure 13 by a second distance greater than the first distance, and a third region R3 spaced from the central region CR of the pixel array region of the chip structure 13 by a third distance greater than the second distance. In an embodiment, the auto focus pixel regions PDaf includes a first auto focus group including first auto focus pixel regions PDaf1 disposed in the first region R1, a second auto focus group including second auto focus pixel regions PDaf2 disposed in the second region R2, and a third auto focus group including third auto focus pixel regions PDaf3 disposed in the third region R3. The grid structure 250 may have a first grid portion 250_P1 having a first width w1 on a region adjacent to the first region R1, a second grid portion 250_P2 having a second width w2 on a region adjacent to the second region R2, and a third width 250_P on a region adjacent to the third region R3. In an embodiment, the first width w1 is narrower or smaller than the second width w2, and the second width w2 is narrower or smaller than the third width w3. With an increase in a distance from the central region CR of the pixel array region of the chip structure 13, a grid portion having a greater width may be disposed to provide an image sensor that reduces a cross-talk phenomenon of the auto-focus groups and having increased uniformity of auto-focus capabilities.
Next, color filter regions 260 defined by the grid structure 250 are formed (S30).
Color filters CF may be formed by depositing a color filter material on the insulating structure 240. The color filters CF may be formed to cover the grid structure 250, and the color filters CF may include color filter regions 260 defined by the grid structure 250. The color filter regions 260 may be formed to correspond to the normal pixel regions PDn and the auto focus pixel regions PDaf.
Next, micro lenses MF are formed on the color filters CF (S40).
On the color filters CF, a TMR-based resin (produced by Tokyo Ohka Kogo, Co.) or an MFR-based resin (produced by Japan Synthetic Rubber Corporation) that conformally covers the color filters CF may be formed to form a lens material layer. However, the material of the lens material layer is not limited thereto. Next, after removing the lens material layer by a predetermined depth through exposure and etching processes, a reflow process and an etch-back process may be performed to form the micro lenses MF.
The present disclosure is not limited to the above-described embodiments and the accompanying drawings. It will be understood by those skilled in the art that various substitutions, modification and changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims, which also belongs to the present disclosure.
Number | Date | Country | Kind |
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10-2022-0168873 | Dec 2022 | KR | national |