The present disclosure relates to an imaging device.
Charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors are widely used for digital cameras and the like. These image sensors have a photodiode formed on a semiconductor substrate.
For example, as disclosed in International Publication No. WO 2012/147302, there is also proposed a structure in which a photoelectric conversion layer is disposed above the semiconductor substrate in place of the photodiode. An imaging device having such a structure is sometimes called a stack-type imaging device. In a stack-type imaging device, as signal charges, charges generated by photoelectric conversion are temporarily accumulated in, e.g., a diffusion region formed at the semiconductor substrate. A signal according to the amount of charges accumulated is read via a CCD circuit or a CMOS circuit formed at the semiconductor substrate.
In one general aspect, the techniques disclosed here feature an imaging device including: a photoelectric converter that generates a signal charge by photoelectric conversion; a semiconductor substrate that includes a first semiconductor layer containing an impurity of a first conductivity type; a charge accumulation region that is an impurity region of a second conductivity type in the first semiconductor layer and that accumulates the signal charge; a transistor that includes, as one of a source and a drain, a first impurity region of the second conductivity type in the first semiconductor layer; and a blocking structure located between the charge accumulation region and the first impurity region. The blocking structure includes a second impurity region of the first conductivity type in the first semiconductor layer and a third impurity region of the first conductivity type in the first semiconductor layer, the third impurity region having an impurity concentration different from an impurity concentration of the second impurity region.
Comprehensive or specific aspects may be implemented as an element, a device, a module, a system, or method. Comprehensive or specific aspects may be also implemented as any selective combination of the element, the device, an apparatus, the module, the system.
Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and/or advantages may be individually obtained by the various embodiments and features of the specification and drawings, which need not all be provided in order to obtain one or more of such benefits and/or advantages.
The present disclosure can reduce dark current.
Charges different from signal charges representing an image may cause noise when flowing into a diffusion region that temporarily holds the signal charges, and the noise degrades a resultant image. It is beneficial if such unintended charge movement can be reduced. In the following, such unintended charge movement may be expressed as dark current or leak current.
The present disclosure provides an imaging device that can reduce dark current.
An overview of aspects of the present disclosure are as follows.
An imaging device according to an aspect of the present disclosure includes: a photoelectric converter that generates a signal charge by photoelectric conversion; a semiconductor substrate that includes a first semiconductor layer containing an impurity of a first conductivity type; a charge accumulation region that is an impurity region of a second conductivity type in the first semiconductor layer and that accumulates the signal charge; a transistor that includes, as one of a source and a drain, a first impurity region of the second conductivity type in the first semiconductor layer; and a blocking structure located between the charge accumulation region and the first impurity region. The blocking structure includes a second impurity region of the first conductivity type in the first semiconductor layer and a third impurity region of the first conductivity type in the first semiconductor layer, the third impurity region having an impurity concentration different from that of the second impurity region. On a line connecting the charge accumulation region and the first impurity region, the charge accumulation region, the second impurity region, the third impurity region, and the first impurity region are disposed in this order.
When the blocking structure thus includes a region with a high concentration of an impurity of the first conductivity type between the first impurity region of the second conductivity type and the charge accumulation region, recombination of minority carriers generated at the p-n junction of the first impurity region of the second conductivity type can be accelerated, which helps prevent minority carriers from flowing into the charge accumulation region. Thus, the provision of the blocking structure enables reduction in dark current flowing to the charge accumulation region.
Meanwhile, minority carriers not recombined in the blocking structure of the first conductivity type have the property of being diffused in the direction of a lower impurity concentration. For this reason, the minority carriers may flow not only into the first impurity region but also into the charge accumulation region.
According to the imaging device according to the aspect of the present disclosure, in a plan view, a distance between the second impurity region and the charge accumulation region may be shorter than a distance between the third impurity region and the charge accumulation region. For example, the second impurity region may have a higher impurity concentration than the third impurity region.
Thus, the second impurity region functions as a diffusion barrier against minority carriers generated at the p-n junction of the first impurity region. This helps prevent minority carriers from flowing into the charge accumulation region. Consequently, image degradation due to dark current generated in the charge accumulation region can be reduced even more.
For example, the second impurity region may be in direct contact with the third impurity region.
An imaging device according to another aspect of the present disclosure includes: a photoelectric converter that generates a signal charge by photoelectric conversion; a semiconductor substrate that includes a first semiconductor layer containing an impurity of a first conductivity type; a charge accumulation region that is an impurity region of a second conductivity type in the first semiconductor layer and that accumulates the signal charge; a transistor that includes, as one of a source and a drain, a first impurity region of the second conductivity type in the first semiconductor layer; and a blocking structure located between the charge accumulation region and the first impurity region. The blocking structure includes a second impurity region of the first conductivity type in the first semiconductor layer and a third impurity region of the first conductivity type in the first semiconductor layer, the third impurity region having an impurity concentration different from an impurity concentration of the second impurity region. The first semiconductor layer may include a second semiconductor layer containing an impurity of the first conductivity type and a third semiconductor layer being adjacent to the second semiconductor layer in a plan view and having an impurity concentration different from an impurity concentration of the second semiconductor layer. The charge accumulation region may be included in the third semiconductor layer. The first impurity region may be included in the second semiconductor layer. In the plan view, the second impurity region may overlap with a border between the second semiconductor layer and the third semiconductor layer.
This allows the region surrounding the charge accumulation region to have a lower impurity concentration and thus can reduce the p-n junction leakage in the charge accumulation region.
For example, the semiconductor substrate may further include a fourth semiconductor layer containing an impurity of the second conductivity type, and the first semiconductor layer may be located between the photoelectric converter and the fourth semiconductor layer.
Thus, minority carriers generated at the p-n junction of the first impurity region are likely to be released to the fourth semiconductor layer through the third semiconductor layer with a low impurity concentration. This helps prevent minority carriers from flowing into the charge accumulation region, and dark current can be reduced even more.
For example, the third semiconductor layer may have a lower impurity concentration than the second semiconductor layer.
When the third semiconductor layer thus has a lower impurity concentration, p-n junction leakage in the charge accumulation region inside the third semiconductor layer can be reduced. Consequently, dark current can be reduced even more.
For example, at least part of the second impurity region, at least part of the third impurity region, or both of the at least part of the second impurity region and the at least part of the third impurity region may be located at a surface of the semiconductor substrate.
For example, the transistor may include a first gate electrically connected to the photoelectric converter.
For example, in a plan view, the second impurity region may surround the charge accumulation region.
For example, in a plan view, the third impurity region may surround the transistor.
For example, in a plan view, the second impurity region may not overlap with the third impurity region.
An imaging device according to still another aspect of the present disclosure includes: a photoelectric converter that generates a signal charge by photoelectric conversion; a semiconductor substrate that includes a first semiconductor layer containing an impurity of a first conductivity type; a charge accumulation region that is an impurity region of a second conductivity type in the first semiconductor layer and that accumulates the signal charge; a transistor that includes, as one of a source and a drain, a first impurity region of the second conductivity type in the first semiconductor layer; and a blocking structure located between the charge accumulation region and the first impurity region. The blocking structure includes a second impurity region of the first conductivity type in the first semiconductor layer and a third impurity region of the first conductivity type in the first semiconductor layer, the third impurity region having an impurity concentration different from an impurity concentration of the second impurity region. The second impurity region is in direct contact with the third impurity region, and in a plan view, the second impurity region does not overlap with the third impurity region.
For example, in the plan view, a distance between the second impurity region and the charge accumulation region may be shorter than a distance between the third impurity region and the charge accumulation region, and the second impurity region may have a higher impurity concentration than the third impurity region.
In the present disclosure, all or some of the circuits, units, apparatuses, members, or portions or all or some of the functional blocks of the block diagram may be executed by one or more electric circuits including a semiconductor apparatus, a semiconductor integrated circuit (IC), or a large scale integration (LSI). The LSI or the IC may be integrated in one chip or may be formed by a combination of a plurality of chips. For example, the functional blocks except for a storage element may be integrated in one chip. Although electric circuits called LSI or IC are used herein, the electric circuits are called differently depending on the degree of integration, and ones called system LSI, very large scale integration (VLSI), or ultra large scale integration (ULSI) may be used. A field-programmable gate array (FPGA) programmed after manufacturing of an LSI or a reconfigurable logic device capable of reconfiguring the connections between the internal constituents of the LSI or setting up circuit sections inside the LSI can also be used for the same purpose.
Further, the functions or operations of all or some of the circuits, units, apparatuses, members, or portions may be executed by software processing. In this case, the software is recorded in one or more non-temporary recording media such as a ROM, an optical disk, and a hard disk drive, and when the software is executed by a processor, a function identified by the software is executed by the processor and a peripheral device. The system or apparatus may include one or more non-temporary recording media in which software is recorded, the processor, and necessary hardware devices such as, for example, an interface.
Embodiments of the present disclosure are described in detail below with reference to the drawings. Note that the embodiments described below each show a comprehensive or specific example. Numeric values, shapes, materials, constituents, the arrangement and connection of the constituents, steps, the order of the steps, and the like shown in the following embodiments are examples and are not intended to limit the present disclosure. Various aspects described herein can be combined as long as no contradiction arises. Also, of constituents in the following embodiments, ones not described in independent claims are described as optional constituents. The following description may use the same reference numeral for constituents having substantially the same function and omit descriptions. Also, in order for the drawings not to be overly complicated, some elements may be omitted in the drawings.
Also, various elements shown in the drawings are shown schematically only for the understanding of the present disclosure, and may have actual dimensional ratios and outer appearances different from actual ones. In other words, the drawings are schematic diagrams and are not necessarily depicted precisely. Thus, for example, the reduction scales are not necessarily the same between the drawings.
Also, herein, terms describing the relation between elements, such as parallel or uniform, terms describing the shape of an element, such as circular or rectangular, and numerical ranges are meant not only to express the exact meanings, but also to include a substantially equivalent range with a difference of, for example, approximately a few percent.
Also, herein, terms “above” and “below” are not used to refer to the upward direction (upward vertically) and the downward direction (downward vertically) in the absolute spatial recognition, but used as terms defined by the relative positional relation based on the stacking order in a stacked configuration. Specifically, the light receiving side of the imaging device is “above,” and the opposite side from the light receiving side is “below.” The same applies to the “upper surface” and the “lower surface” of each member; the surface facing the light receiving side of the imaging device is an “upper surface,” and the surface facing the opposite side from the light receiving side is a “lower surface.” Note that the terms “above,” “below,” “upper surface,” and “lower surface” are used only to specify the placement of members relative to each other and are not intended to limit the posture of the imaging device during use. Also, the terms “above” and “below” are used not only for a state where two constituents are disposed apart from each other with another constituent being present between the constituents, but also for a state where two constituents are disposed closely to each other and in contact with each other. Also, herein, a “plan view” is a view seen in a direction perpendicular to the semiconductor substrate.
Each pixel 10 has a photoelectric converter 12. The photoelectric converter 12, upon receipt of light, generates positive and negative charges, or typically, hole-electron pairs. The photoelectric converter 12 may be a photoelectric conversion structure including a photoelectric conversion layer disposed above the semiconductor substrate 60 or may be a photodiode formed at the semiconductor substrate 60. Although
In the example shown in
The number and arrangement of the pixels 10 are not limited to the example shown in
In the configuration exemplified in
The vertical scanning circuit 42 is also called a row scanning circuit and has connections to address signal lines 34 provided in correspondence to the respective rows of the plurality of pixels 10. As will be described later, signal lines provided in correspondence to the respective rows of the plurality of pixels 10 are not limited to the address signal lines 34, and a plurality of kinds of signal lines may be connected to the vertical scanning circuit 42 for each row of the plurality of pixels 10. The horizontal signal reading circuit 44 is also called a column scanning circuit and has connections to vertical signal lines 35 provided in correspondence to the respective rows of the plurality of pixels 10.
The control circuit 46 performs overall control of the imaging device 100 by receiving command data, clock signals, and the like given from, e.g., the outside of the imaging device 100. Typically, the control circuit 46 has a timing generator and supplies driving signals to the vertical scanning circuit 42, the horizontal signal reading circuit 44, the voltage supply circuit, and the like. In
The photoelectric converter 12 of each pixel 10 has a connection to an accumulation control line 31. When the imaging device 100 is in operation, a predetermined voltage is applied to the accumulation control line 31. For example, if positive charges are used as signal charges out of the positive and negative charges generated by photoelectric conversion, positive charges of, for example, approximately 10 V may be applied to the accumulation control line 31 when the imaging device 100 is in operation. An example of using holes as signal changes is shown below.
In the configuration exemplified in
As schematically shown in
The drain of the signal detection transistor 22 is connected to power source wiring 32 that supplies a power source voltage VDD of, for example, approximately 3.3 V to each pixel 10 when the imaging device 100 is in operation, and the source of the signal detection transistor 22 is connected to a vertical signal line 35 via the address transistor 24. When supplied with the power source voltage VDD to its drain, the signal detection transistor 22 outputs a signal voltage according to the amount of signal charges accumulated in the charge accumulation node FD.
The address signal line 34 is connected to the gate of the address transistor 24 connected between the signal detection transistor 22 and the vertical signal lines 35. The vertical scanning circuit 42 applies a row selection signal for controlling the on and off of the address transistor 24 to the address signal line 34. As a result of this, an output from the signal detection transistor 22 of the selected pixel 10 can be read to the corresponding vertical signal line 35. Note that the placement of the address transistor 24 is not limited to the example shown in
A load circuit 45 and a column signal processing circuit 47 are connected to each of the vertical signal lines 35. The load circuit 45 forms a source-follower circuit with the signal detection transistor 22. The column signal processing circuit 47 is also called a row signal accumulation circuit and performs noise reduction signal processing typified by correlated double sampling, analog-to-digital conversion, and the like. The horizontal signal reading circuit 44 sequentially reads signals from the plurality of column signal processing circuits 47 to a horizontal shared signal line 49. The load circuit 45 and the column signal processing circuit 47 may be part of the above-described peripheral circuits 40.
A reset signal line 36 having a connection to the vertical scanning circuit 42 is connected to the gate of the reset transistor 26. The reset signal line 36 is provided for each row of the plurality of pixels 10, like the address signal lines 34. The vertical scanning circuit 42 can select the pixels 10 to be reset on a row basis by applying a row selection signal to the address signal line 34 and can switch the reset transistor 26 of the selected row on and off by applying a reset signal to the gate of the reset transistor 26 via the reset signal line 36. When the reset transistor 26 is turned on, the potential at the charge accumulation node FD is reset.
In this example, one of the drain and source of the reset transistor 26 is connected to the charge accumulation node FD, and the other one of the drain and source of the reset transistor 26 is connected to a corresponding one of feedback lines 53 provided for the respective rows of the plurality of pixels 10. In other words, in this example, a voltage from the feedback line 53 is supplied to the charge accumulation node FD as a reset voltage for resetting charges from the photoelectric converter 12.
In the configuration exemplified in
As shown in
The photoelectric converter 12 includes a pixel electrode 12a formed on the interlayer insulating layer 90, an opposite electrode 12c disposed on the light entry side, and the photoelectric conversion layer 12b disposed between the pixel electrode 12a and the opposite electrode 12c. The photoelectric conversion layer 12b is formed of an organic material or an inorganic material such as amorphous silicon, and performs photoelectric conversion when receiving light via the opposite electrode 12c and thereby generates positive and negative charges. The photoelectric conversion layer 12b is typically formed continuously over a plurality of pixels 10. The photoelectric conversion layer 12b is, in a plan view, formed in the form of a single plate covering a large portion of the image capture region R1 of the semiconductor substrate 60. Thus, the photoelectric conversion layer 12b is shared by a plurality of pixels 10. In other words, the photoelectric converter 12 provided for each pixel 10 includes a part of the photoelectric conversion layer 12b, the part being different for each of the pixels 10. Also, the photoelectric conversion layer 12b may include a layer formed of an organic material and a layer formed of an inorganic material. The photoelectric conversion layer 12b may be provided separately for each pixel 10.
The opposite electrode 12c is a translucent electrode formed of a transparent conductive material such as indium tin oxide (ITO). The term “translucent” used herein means that at least part of the light of a wavelength that the photoelectric conversion layer 12b can absorb is transmitted, and it is not essential that light of the entire wavelength range of visible light be transmitted. Typically, the opposite electrode 12c is, like the photoelectric conversion layer 12b, continuously formed over a plurality of pixels 10. Thus, the opposite electrode 12c is shared by a plurality of pixels 10. In other words, the photoelectric converter 12 provided for each pixel 10 includes a part of the opposite electrode 12c, the part being different for each of the pixels 10. The opposite electrode 12c may be provided separately for each pixel 10.
The opposite electrode 12c has a connection to the above-described accumulation control line 31, although the connection is not shown in
The pixel electrode 12a is an electrode formed of a metal such as aluminum or copper, a metal nitride, or polysilicon made to be conductive by impurity doping. The pixel electrode 12a is electrically separated from the pixel electrodes 12a of the other neighboring pixels 10 by being spatially separated from the pixel electrodes 12a of the other pixels 10.
The conductive structure 89 typically includes a plurality of wiring portions and plugs formed of a metal such as copper or tungsten or of a metal compound such as a metal nitride or a metal oxide and a polysilicon plug. One end of the conductive structure 89 is connected to the pixel electrode 12a. The other end of the conductive structure 89 is connected to a circuit element formed at the semiconductor substrate 60, so that the pixel electrode 12a of the photoelectric converter 12 and the circuit on the semiconductor substrate 60 are electrically connected to each other.
Now, focusing on the semiconductor substrate 60, as schematically shown in
The semiconductor substrate 60 has a first surface and a second surface opposite from the first surface. The first surface is a surface on the light entry side. Specifically, the first surface is, of a plurality of surfaces that the semiconductor substrate 60 has, a surface on the side where the photoelectric converter 12 is provided. Herein, the “front surface” of the semiconductor substrate 60 corresponds to the first surface, and the “back surface” of the semiconductor substrate 60 corresponds to the second surface. The surface of the semiconductor substrate 60 where the support substrate 61 is provided is the second surface, although the second surface is not shown in
The support substrate 61 contains an impurity of a first conductivity type. In the present embodiment, the first conductivity type is a p-type. Here, a p-type silicon substrate is shown as an example of the support substrate 61. The p-type impurity contained in the support substrate 61 is, for example, boron.
The support substrate 61 has a connection to a substrate contact provided outside the image capture region R1, although the connection is not shown in
The n-type semiconductor layer 62n contains an impurity of a second conductivity type different from the first conductivity type and is an example of the fourth semiconductor layer located on the opposite side of the p-type semiconductor layer 65p from the photoelectric converter 12. The n-type semiconductor layer 62n is located between the p-type semiconductor layer 65p and the support substrate 61. In the present embodiment, the second conductivity type is an n-type. The n-type impurity contained in the n-type semiconductor layer 62n is, for example, phosphorus.
A well contact (not shown) is connected to the n-type semiconductor layer 62n, although not shown in
The p-type semiconductor layer 65p is an example of the first semiconductor layer containing an impurity of the first conductivity type. The p-type semiconductor layer 65p is provided closer to the front surface of the semiconductor substrate 60 than the n-type semiconductor layer 62n. Specifically, the p-type semiconductor layer 65p is provided on and is in contact with the upper surface of the n-type semiconductor layer 62n.
Each of the n-type semiconductor layer 62n and the p-type semiconductor layer 65p is typically formed by ion implantation of impurity into an epitaxially grown semiconductor film.
The p-type semiconductor layer 65p has a higher impurity concentration than the support substrate 61. The impurity concentration of the support substrate 61 is, for example, approximately 1015 cm−3, and the impurity concentration of the p-type semiconductor layer 65p may be, for example, approximately 1017 cm−3.
As schematically shown in
The charge accumulation region 67n is an impurity region of the second conductivity type inside the p-type semiconductor layer 65p and is an example of the charge accumulation region where the signal charges are accumulated. The n-type charge accumulation region 67n is formed near the front surface of the semiconductor substrate 60, and at least part of the charge accumulation region 67n is located at the front surface of the semiconductor substrate 60. Here, the charge accumulation region 67n includes a first region 67a and a second region 67b being located inside the first region 67a and having a higher impurity concentration than the first region 67a. The impurity concentration of the first region 67a is, for example, approximately 1017 cm−3, and the impurity concentration of the second region 67b is, for example, approximately 3×1018 cm−3. Here, “×” means multiplication.
An insulating layer is disposed on the front surface of the semiconductor substrate 60. In the example shown in
The stack structure of the first insulating layer 71, the second insulating layer 72, and the third insulating layer 73 has a contact hole h1 on the second region 67b of the charge accumulation region 67n. In the example shown in
A junction capacitance formed by a p-n junction between the p-type semiconductor layer 65p as a p-well and the n-type charge accumulation region 67n has a function as a charge accumulation region that temporarily holds signal charges. The conductive structure 89 and the n-type charge accumulation region 67n can be said to form at least part of the above-described charge accumulation node FD.
Note that the formation of the second region 67b in the charge accumulation region 67n is not essential. However, a contact resistance reduction effect can be obtained by connecting the contact plug Cp1 to the second region 67b having a relatively high impurity concentration.
The above-described signal detection circuit 14 is formed at the semiconductor substrate 60. The signal detection circuit 14 in the pixel 10 is electrically separated from the signal detection circuits 14 in the other neighboring pixels 10 because the device isolation region 69a and the device isolation region 69b are disposed between the neighboring pixels 10.
In the signal detection circuit 14, the reset transistor 26 includes the n-type charge accumulation region 67n as one of its drain and source regions and includes the n-type impurity region 68an as the other one of the drain and source regions. The reset transistor 26 further includes a gate electrode 26e on the first insulating layer 71, and a part of the first insulating layer 71 that is located between the gate electrode 26e and the semiconductor substrate 60 functions as a gate insulating film for the reset transistor 26.
The impurity region 68an is formed in the p-type semiconductor layer 65p. A contact plug Cp2 is connected to the impurity region 68an via a contact hole h2. The contact plug Cp2 is electrically connected to the feedback line 53.
The p-type semiconductor layer 65p is further provided with the n-type impurity region 68bn, the impurity region 68cn, the impurity region 68dn, and the impurity region 68en. The impurity region 68bn is an example of the first impurity region. The impurity region 68an, the impurity region 68bn, the impurity region 68cn, the impurity region 68dn, and the impurity region 68en have higher impurity concentrations than the first region 67a of the charge accumulation region 67n.
The signal detection transistor 22 includes the impurity region 68bn, the impurity region 68cn, and a gate electrode 22e on the first insulating layer 71. The impurity region 68bn functions as, for example, the drain region of the signal detection transistor 22, and the impurity region 68cn functions as, for example, the source region of the signal detection transistor 22. In this example, in a layer where the address signal lines 34 and the reset signal lines 36 are located, the gate electrode 22e is connected to a part of the conductive structure 89 where the pixel electrode 12a and the contact plug Cp1 are connected to each other. In other words, the conductive structure 89 also has an electric connection to the gate electrode 22e. The gate electrode 22e is an example of the first gate electrically connected to the photoelectric converter 12.
A contact plug Cp3 is connected the impurity region 68bn via a contact hole h3. The above-described power source wiring 32 as a source-follower power source is electrically connected to the contact plug Cp3. Note that the power source wiring 32 is omitted and not shown in
The address transistor 24 is formed at the semiconductor substrate 60 as well. The address transistor 24 includes the impurity region 68en, the impurity region 68dn, and a gate electrode 24e on the first insulating layer 71. The n-type impurity region 68en functions as, for example the drain region of the address transistor 24, and the n-type impurity region 68dn functions as, for example, the source region of the address transistor 24. A part of the first insulating layer 71 that is located between the gate electrode 24e and the semiconductor substrate 60 functions as a gate insulating film for the address transistor 24.
The impurity region 68cn and the impurity region 68en are, as shown in
Next, the blocking structure 69 is described in detail using
As shown in
The device isolation region 69a is an example of the second impurity region containing an impurity of the first conductivity type. The device isolation region 69b is an example of the third impurity region containing an impurity of the first conductivity type. The device isolation region 69a and the device isolation region 69b are adjacently formed near the front surface of the semiconductor substrate 60. The device isolation region 69a and the device isolation region 69b are adjacent to each other in a plan view, and at least part of each of them is located at the front surface of the semiconductor substrate 60. Note that the device isolation region 69a and the device isolation region 69b do not have to be in contact with each other in a plan view and may be away from each other by a predetermined distance.
As shown in
Note that herein, what is meant by “A is located between B and C” is that at least one of line segments each connecting a given point in B and a given point in C passes through A. Also, what is meant by “A is provided closer to C than B” is that the distance between A and C is shorter than the distance between B and C. Thus, in the present embodiment, the distance between the device isolation region 69a and the charge accumulation region 67n is shorter than the distance between the device isolation region 69b and the charge accumulation region 67n. Note that “the distance between A and B” means the shortest distance between A and B, i.e., the distance between a portion of A closest to B and a portion of B closest to A.
As shown in
Specifically, in a plan view, the device isolation region 69a is in contact with neither of the charge accumulation region 67n and the impurity region 68an. For example, the device isolation region 69a is formed approximately 50 nm away from each of the charge accumulation region 67n and the impurity region 68an. Note that the gap between the device isolation region 69a and the charge accumulation region 67n and the gap between the device isolation region 69a and the impurity region 68an may be the same as or different from each other.
Also, the device isolation region 69b is in contact with neither of the impurity region 68bn, the impurity region 68cn, the impurity region 68dn, and the impurity region 68en. For example, the device isolation region 69b is formed approximately 50 nm away from each of the impurity region 68bn, the impurity region 68cn, the impurity region 68dn, and the impurity region 68en. Note that the gaps between the device isolation region 69b and each of the impurity region 68bn, the impurity region 68cn, the impurity region 68dn, and the impurity region 68en may be the same as or different from each other.
The device isolation region 69a and the device isolation region 69b have different impurity concentrations from each other. Specifically, the device isolation region 69a has a higher impurity concentration than the device isolation region 69b. Also, the device isolation region 69a and the device isolation region 69b have higher impurity concentrations than the p-type semiconductor layer 65p. For example, the impurity concentration of the device isolation region 69b is two or more times or five or more times as high as that of the p-type semiconductor layer 65p. Also, the impurity concentration of the device isolation region 69a is 1.2 or more times or 1.5 or more times as high as that of the device isolation region 69b. The impurity concentration of the device isolation region 69a is, for example, approximately 1.3×1018 cm−3. The impurity concentration of the device isolation region 69b is, for example, approximately 7×1017 cm−3. Here, “×” means multiplication.
As thus described, in the present embodiment, the device isolation region 69a and the device isolation region 69b having different impurity concentrations are disposed between the charge accumulation region 67n and the impurity region 68bn. Then, the device isolation region 69a disposed closer to the reset transistor 26 including the charge accumulation region 67n as one of its source and drain has a higher impurity concentration than the device isolation region 69b.
Now, the dark current reduction effect offered by the blocking structure 69 is described from the perspective of potential.
Note that as shown in
Between
The impurity region 68bn is the drain of the signal detection transistor 22 and receives the power source voltage VDD of approximately 3.3 V. Thus, due to a high electric field, collisional ionization occurs in the vicinities of the border between the impurity region 68bn and the blocking structure 69, generating minority carriers inside the blocking structure 69. A majority of the minority carriers flow to the impurity region 68bn due to the direction of the electric field. However, it has been found that when the power source voltage VDD exceeds 3 V and an increased amount of minority carriers are thereby generated, the minority carriers flow not only to the n-type semiconductor layer 62n disposed on the support substrate 61 side of the p-n junction, but also to the charge accumulation region 67n, thereby increasing dark current.
Now, the reason why the minority carriers flow into the charge accumulation region 67n is described using the potentials at the respective regions. When, for example, the device isolation region 69b closer to the charge accumulation region 67n has a lower impurity concentration than the device isolation region 69a like in the comparative example shown in
Meanwhile, when the device isolation region 69a closer to the charge accumulation region 67n has a higher impurity concentration than the device isolation region 69b like in the present embodiment, the device isolation region 69a plays the role as a barrier against diffusion of minority carriers, as shown in
Also, the structure shown in
As shown in
Note that in
There are cases where the device isolation region 69b with a low impurity concentration can be closer to the charge accumulation region 67n than the device isolation region 69a with a high impurity concentration, although such a mode is shown in
Next, Embodiment 2 is described.
Embodiment 2 differs from Embodiment 1 in the configuration of the first semiconductor layer. Specifically, in the present embodiment, the first semiconductor layer includes two semiconductor layers having different impurity concentrations. The following description focuses on the differences from Embodiment 1 and omits or simplifies a description of a common point.
The main difference between the pixel 10A shown in
The p-type semiconductor layer 65bp is an example of the second semiconductor layer containing an impurity of the first conductivity type. The p-type semiconductor layer 65bp is provided around the p-type semiconductor layer 65ap.
The p-type semiconductor layer 65ap is an example of the third semiconductor layer containing an impurity of the first conductivity type. The p-type semiconductor layer 65ap includes the charge accumulation region 67n. The p-type semiconductor layer 65ap is, in a plan view, adjacent to the p-type semiconductor layer 65bp. A border 65c shown in
The p-type semiconductor layer 65ap has an impurity concentration different from that of the p-type semiconductor layer 65bp. Specifically, the p-type semiconductor layer 65ap has a lower impurity concentration than the p-type semiconductor layer 65bp. Since the impurity concentration of the region surrounding the charge accumulation region 67n can thus be low, p-n junction leakage at the charge accumulation region 67n can be reduced. The p-type semiconductor layer 65ap has the same impurity concentration as, for example, the support substrate 61. Also, the p-type semiconductor layer 65bp has a lower impurity concentration than the device isolation region 69b. The p-type semiconductor layer 65bp may have the same impurity concentration as the p-type semiconductor layer 65p according to Embodiment 1. The impurity concentration of the p-type semiconductor layer 65ap is, for example, approximately 1016 cm−3. The impurity concentration of the p-type semiconductor layer 65bp is, for example, approximately 1017 cm−3.
The device isolation region 69a of the blocking structure 69 and the charge accumulation region 67n are, in a plan view, provided away from each other by a predetermined distance such as, for example, 50 nm. In the present embodiment, the charge accumulation region 67n is surrounded by the p-type semiconductor layer 65ap with a low impurity concentration and is not in contact with the blocking structure 69 with a high impurity concentration. When the impurity concentration of the p-type semiconductor layer 65ap is thus low, the electric field in the p-n junction between the p-type semiconductor layer 65ap and the charge accumulation region 67n can be mitigated, and thus, p-n junction leakage can be reduced.
Also, although the layers and the regions are shown with their thicknesses emphasized in
Note that the border 65c may overlap with the device isolation region 69b in a plan view. The border 65c may be located between the impurity region 68bn and the device isolation region 69b in a plan view. Specifically, the border 65c may be not overlapping with the blocking structure 69 in a plan view, and the blocking structure 69 may be surrounded in contact only with the p-type semiconductor layer 65ap.
In these cases as well, dark current can be reduced by the reduction of the p-n junction leakage at the charge accumulation region 67n and by the improvement in the release of minor carriers. Note that when the border 65c overlaps with the impurity region 68bn, p-n junction leakage may vary between pixels. Thus, variation in electric characteristics can be reduced when the border 65c is provided in such a manner as not to overlap with the impurity region 68bn.
Although the blocking structure 69 in the imaging device according to Embodiment 2 has the device isolation region 69a and the device isolation region 69b having different impurity concentrations from each other, the present disclosure is not limited to this. For example, the device isolation region 69a and the device isolation region 69b may have the same impurity concentration. The following describes, using
The blocking structure 69B is formed of a single impurity region having a substantially uniform impurity concentration. The blocking structure 69B has a higher impurity concentration than both of the p-type semiconductor layer 65ap and the p-type semiconductor layer 65bp. The blocking structure 69B may have the same impurity concentration as the device isolation region 69a or the device isolation region 69b according to Embodiments 1 and 2. Alternatively, the blocking structure 69B may have a higher impurity concentration than the device isolation region 69a and a lower impurity concentration than the device isolation region 69b. For example, the impurity concentration of the blocking structure 69B is greater than or equal to 7×1017 cm−3 and less than or equal to 1.3×1018 cm−3, but the present disclosure is not limited to this.
In a plan view, the blocking structure 69B and the charge accumulation region 67n are provided away from each other by a predetermined distance such as, for example, 50 nm. In the present modification, the charge accumulation region 67n is surrounded by the p-type semiconductor layer 65ap with a low impurity concentration and is not in contact with the blocking structure 69B with a high impurity concentration. When the p-type semiconductor layer 65ap thus has a low impurity concentration, the electric field in the p-n junction between the p-type semiconductor layer 65ap and the charge accumulation region 67n can be mitigated, and the p-n junction leakage can thereby be reduced.
Also, as shown in
The distance between the blocking structure 69B and the n-type semiconductor layer 62n is shorter than the distance between the blocking structure 69B and the charge accumulation region 67n. Thus, minority carriers generated in the vicinities of the impurity region 68bn are likely to be released to the n-type semiconductor layer 62n via the p-type semiconductor layer 65ap with a low impurity concentration. As a result, minority carriers flowing to the charge accumulation region 67n can be reduced, and dark current can be reduced further compared to a case where the p-type semiconductor layer 65p has a single structure like in Embodiment 1.
Note that the border 65c may be located between the blocking structure 69B and the impurity region 68bn in a plan view, like in Embodiment 2. Specifically, the border 65c may be not overlapping with the blocking structure 69B in a plan view, and the blocking structure 69B may be surrounded in contact only with the p-type semiconductor layer 65ap. In these cases as well, dark current can be reduced by the reduction of the p-n junction leakage at the charge accumulation region 67n and by the improvement in the release of minor carriers.
Although imaging devices according to one or more aspects have thus been described based on the embodiments, the present disclosure is not limited to these embodiments. Modes obtained by applying various modifications conceived of by those skilled in the art to the present embodiments and modes formed by combining constituents in different embodiments are also included in the scope of the present disclosure as long as they do not depart from the gist of the present disclosure.
Also, each of the signal detection transistor 22, the address transistor 24, and the reset transistor 26 described above may be an N-channel MOSFET or a P-channel MOSFET. When each transistor is a P-channel MOSFET, an impurity of the first conductivity type is a p-type impurity, and an impurity of the second conductivity type is an n-type impurity. These transistors do not have to be all N-channel MOSFETs or P-channel MOSFETs. When each transistor in a pixel is an N-channel MOSFET and electrons are used as signal charges, the positions of the source and the drain of each of these transistors may be interchanged.
Also, the embodiments described above may be subject to various kinds of modification, replacement, addition, omission, and the like within the scope of the claims or a scope equivalent thereof.
The present disclosure can be used as an imaging device capable of reducing dark current and, for example, can be applied to, e.g., an image sensor mounted in a camera, a surveillance camera, or a vehicle-mounted camera.
Number | Date | Country | Kind |
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2020-200065 | Dec 2020 | JP | national |
Number | Date | Country | |
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Parent | PCT/JP2021/041253 | Nov 2021 | US |
Child | 18317384 | US |