Claims
- 1. An impedance-matched write driver circuit comprising:
a current driver circuit for coupling to a voltage source, wherein said current driver circuit comprises a plurality of transistors coupled in an H-bridge; a signal input coupled to control an output of said current driver circuit; and an impedance matching circuit coupled to said current driver circuit, wherein said impedance matching circuit is enabled to damp output oscillations in said output of said write driver circuit.
- 2. The impedance-matched write driver circuit described in claim 1, wherein said impedance matching circuit is coupled to said output in parallel with said current driver circuit.
- 3. The impedance-matched write driver circuit described in claim 1, wherein the impedance of said impedance matching circuit is programmable.
- 4. The impedance-matched write driver circuit described in claim 3, wherein said impedance is programmable by component selection during hard disk read/write head development.
- 5. The impedance-matched write driver circuit described in claim 3, wherein said impedance is programmable by logic signals.
- 6. The impedance-matched write driver circuit described in claim 1, wherein said impedance matching circuit comprises pairs of transistors and resistors.
- 7. The impedance-matched write driver circuit described in claim 6, wherein base connections of a first pair of said transistors are coupled to each other and to collector connections of said transistors.
- 8. The impedance-matched write driver circuit described in claim 7, wherein emitter connection of each of said base-collector connected transistors is coupled to a resistor.
- 9. The impedance-matched write driver circuit described in claim 8, wherein each of said resistors is coupled to a pole of said output of said write driver circuit.
- 10. The impedance-matched write driver circuit described in claim 8, wherein collector connections of a second pair of said transistors are coupled to said output of said write driver circuit.
- 11. The impedance-matched write driver circuit described in claim 10, wherein base connections of said second pair of said transistors are coupled to base connections of a complimentary pair of transistors of said current driver circuit.
- 12. The impedance-matched write driver circuit described in claim 10, wherein emitter connections of said second pair of said transistors are coupled together and to a ground reference.
- 13. A selectable impedance write driver circuit comprising:
a plurality of current driver circuits, each enabled to provide a selected output impedance and each coupled to a voltage source; a selection input coupled to control the selection of one of said plurality of current driver circuits; a signal input coupled to control an output of each of said plurality of current driver circuits; and a current output, wherein an impedance of said output is selectable by reference to said selection input.
- 14. The selectable impedance write driver circuit described in claim 13, wherein said selection input is responsive to a resistor selection external to said write driver circuit.
- 15. The selectable impedance write driver circuit described in claim 13, wherein said selection input is the result of logic input to said write driver circuit.
- 16. The selectable impedance write driver circuit described in claim 13, wherein the impedance of each of said plurality of current driver circuits by resistor size in each of said plurality of current driver circuits.
- 17. The selectable impedance write driver circuit described in claim 13, wherein said current output is for connection to a read pre-amplifier.
- 18. A hard disk memory device, comprising:
a magnetically recordable medium affixed to a planar surface of a rotating disk; an arm positionable over said magnetically recordable medium; a write head affixed to said arm for magnetically recording to said magnetically recordable medium; a read head affixed to said arm for reading data magnetically recorded to said magnetically recordable medium; and a write driver for driving write current to said magnetic write head wherein said write driver is a programmable impedance write driver circuit.
- 19. The hard disk memory device described in claim 18, wherein said write driver comprises an impedance matching circuit and a current driver circuit wherein said impedance matching circuit is coupled to an output of said write driver circuit in parallel with said current driver circuit.
- 20. The hard disk memory device described in claim 18, wherein an impedance of said impedance matching circuit is programmable.
- 21. The hard disk memory device described in claim 20, wherein said impedance is programmable by component selection during hard disk read/write head development.
- 22. The hard disk memory device described in claim 18, wherein said impedance matching circuit comprises pairs of transistors and resistors.
- 23. The hard disk memory device described in claim 22, wherein base connections of a first pair of said transistors are coupled to each other and to collector connections of said transistors.
- 24. The hard disk memory device described in claim 23, wherein emitter connection of each of said base-collector connected transistors is coupled to a resistor.
- 25. The hard disk memory device described in claim 23, wherein each of said resistors is coupled to a pole of an output of said write driver circuit.
- 26. The hard disk memory device described in claim 23, wherein collector connections of a second pair of said transistors are coupled to an output of said write driver circuit.
- 27. The hard disk memory device described in claim 26, wherein the base connections of said second pair of said transistors are electronically coupled to the base connections of a pair of transistors of said current driver circuit.
- 28. The hard disk memory device described in claim 18, wherein emitter connections of said second pair of said transistors are coupled together and to a ground reference.
RELATED U.S. APPLICATIONS
[0001] This application claims priority to the commonly-owned co-pending provisional patent application, U.S. Ser. No. 60/434,868, entitled “IMPEDANCE-MATCHED WRITE DRIVER,” filed Dec. 19, 2002, and assigned to the assignee of the present invention and this application is hereby incorporated by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60434868 |
Dec 2002 |
US |