Implementation of iscan cell for self-resetting dynamic circuit

Abstract

A method and a circuit for testing an integrated circuit are disclosed. In one embodiment, a self-resetting dynamic circuit, also known as a fireball circuit, contains a scan circuit and at least one Set Dominant Latches (“SDL”) where each SDL includes a keeper node. When scan clock is active, the scan data propagates from the scan circuit to the self-resetting dynamic circuit through the keeper node.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of integrated circuits and, more specifically, the present invention relates to a mechanism for testing an integrated circuit.

2. Description of the Related Art

Integrated circuits are becoming more densely packed with increasing numbers of individual circuit elements. It is common for a single chip to have thousands of individual elements that include millions of transistors. With the increasing number of individual elements, testing each element becomes more difficult to achieve. A conventional test mechanism used in the past for testing the integrated circuit is a scan test.

A scan test is typically performed by a scan circuit, also known as a scan cell. The scan circuit usually propagates scan data with test patterns where the test patterns are, subsequently, applied to the inputs of the integrated circuit. Depending on the test pattern, the responses or results of the integrated circuit to the test pattern can provide an accurate indication of the existence or non-existence of defects.

However, with recently developed high-speed circuitry, the scan technology used in the past may be inadequate since a conventional scan circuit is typically too slow for scanning the data through the high-speed circuitry.

SUMMARY OF THE INVENTION

A device for testing an integrated circuit includes a self-resetting dynamic circuit having a keeper node and a testing circuit that is coupled to the keeper node. The testing circuit is configured to test the self-resetting dynamic circuit in response to at least one test clock.

Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.

DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.

FIG. 1 is a block diagram illustrating an embodiment of a scan circuit.

FIG. 2 is a circuit diagram illustrating an embodiment of a scan circuit for testing a self resetting dynamic circuit.

FIG. 3 is a circuit diagram illustrating an embodiment of a scan circuit having a keeper node.

FIG. 4 is a circuit diagram illustrating an embodiment for implementing a tri-state function.

FIG. 5 is a clock waveform illustrating an embodiment of scan clocks.

FIG. 6 is a block diagram illustrating an embodiment of scan process for scanning.

FIG. 7 is a flowchart illustrating one embodiment of scan process for scanning.

DETAILED DESCRIPTION

A method and a system for testing a self-resetting dynamic circuit, also known as a fireball circuit, including a scan circuit and a SDL having a keeper node are described.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the present invention.

It is understood that the present invention may be comprised of transistor circuits that are readily manufacturable using well-known CMOS (complementary metal-oxide semiconductor) technology, or other equivalent semiconductor manufacturing processes. In addition, the present invention may be implemented with other manufacturing processes for making digital devices.

While in the following discussion the present invention is presented with respect to implementation in a microprocessor, the present invention is not limited to that implementation. Implementations for generating clock signals for various digital devices such as discrete logic devices, memory devices, devices either on the same or separate chips, communications devices, etc., are within the scope of the present invention.

OVERVIEW

A mechanism for testing a self-resetting dynamic circuit (“SRDC”), also known as a fireball circuit, using a scan circuit is disclosed. In one embodiment, the SRDC, which is coupled to a scan circuit, contains at least a Set Dominant Latch (“SDL”). The SDL is a dynamic state device used for holding a logic state. The SDL further includes a keeper node, which, in one embodiment, is able to receive the scan data. For example, when the scan clock is active, the scan data propagates from the scan circuit to the SRDC through the keeper node. The scan data as discussed previously may contain a set of specific test patterns where each specific test pattern indicates a specific circuit defect. In an alternative embodiment, a tri-state device may be used to prevent data contention between the data from the scan circuit and the data from the SRDC.

FIG. 1 is a block diagram 100 illustrating an embodiment of a scan circuit for testing a SRDC. Referring back to FIG. 1 , a scan cell block 102 , a logic block 104 , a SDL block 108 , and two combinational logic blocks 106 , 110 are disclosed. Other logic blocks could be added in block diagram 100 .

In one embodiment, scan cell 102 receives scan input data S IN with test patterns, a scan clock A (“SCa”) and a scan clock B (“SCb”). While the output of scan cell 102 is fed to the input of logic 104 , the output of logic 104 is the scan output data S OUT . The scan data generated by scan cell 102 , in one embodiment, is also fed to SDL 108 .

In one embodiment, combinational logic block 106 receives the data input D IN and the clock Fclk which may also be a system clock. Combinational logic block 106 may perform various logical functions, such as, for example, multiplication and addition functions. The result of the combinational logic block 106 is latched at SDL 108 . The output of SDL 108 is coupled to the input of combinational logic block 110 . The output of combinational logic block 110 is output at D OUT . In one embodiment, Fclk is distributed to various functional blocks as well as latches, such as, for example, combinational logic blocks 106 , 110 and SDL 108 .

Fclk is turned off and SCa and SCb are turned on when the scan mode or testing mode is active. The scan data, which may contain test patterns, are scanned into SDL 108 . Once SDL 108 receives the scan data, scan clocks SCa, SCb are turned off and Fclk is turned back on. After scan mode is switched to the system mode, the functional blocks, such as, for example, combinational logic block 110 , perform logic functions using. the data stored in SDL 108 . Since SDL 108 contains the scan data, the results of the functional blocks, such as combinational logic clock 110 , can be predicted. When the functional blocks complete the implementation of the scan data, Fclk is again turned off and SCa, SCb are turned back on. When the results of the functional blocks are scanned out, the results are further compared with the expected (or predicted) answers with the outcome of the comparison indicating, at least in part, whether the functional blocks contain defects or not.

FIG. 2 is a circuit diagram 200 illustrating an embodiment of a scan circuit for testing a SRDC. Referring back to FIG. 2 , block 202 and block 204 are described. In one embodiment, block 202 is a scan circuit or scan cell while block 204 includes a SDL. In one embodiment, scan circuit is used to test the SRDC using scan data, such as, for example, test data with patterns. The SDL is a dynamic latch that is capable of storing a logic value. In one embodiment, a SDL can receive scan data from the scan circuit through its keeper node.

Block 202 contains two pass gates 210 , 214 , two inverters, 212 , 216 , and a tri-state device 218 . The function of a pass gate 210 or 214 is to allow a signal to pass on a first condition and to prevent a signal to pass on a second condition. For example, if SCa is active, pass gate 210 allows S IN to pass and if SCa is inactive, pass gate 210 prevents S IN from passing through pass gate 210 . In one embodiment, tri-state device 218 functions as an open circuit when SCa is in one condition and performs an inverter function when SCa is in another condition. For example, if SCb is active, tri-state device 218 functions as an inverter and if SCb is inactive, tri-state device 218 functions as an open circuit.

Pass gate 210 receives S IN and SCa and the output of the pass gate 210 is connected to the input of inventor 212 . The input of pass gate 214 is connected to the output of inverter 212 and the control input of pass gate 214 is connected to SCb. The output of pass gate 214 is connected to the input of inverter 216 and the output of the 216 is the scan output, S OUT , S OUT , is also fed back to the input of tri-state device 218 . Tri-state device 218 receives SCb, which controls tri-state device 218 . The output of the tri-state device 218 is connected to the input of inverted 216 .

In one embodiment, SDL 204 is a high-speed dynamic latch consisting of two PMOS transistors P 1 , P 2 , three NMOS transistors, N 1 , N 2 , N 3 , and a tri-state device 220 . The source terminal of P 1 is connected to a positive voltage supply and the drain terminal of P 1 is connected to node A, which is the output of the circuit. The gate terminal of P 1 receives the data input, D IN . The source terminal of N 2 is connected to a ground voltage supply and the drain terminal of N 2 is connected to the source terminal of N 1 . The gate terminal of N 2 receives Fclk. The drain terminal of N 1 is connected to the node A and the gate terminal of N 1 is connected to D IN .

The source terminal of N 3 is connected to the ground voltage supply and the drain terminal of N 3 is connected to the source terminal of N 1 . The gate terminal of N 3 is coupled to a keeper node. The source terminal of P 2 is connected to the positive voltage supply and the drain terminal of P 2 is coupled to the node A. The gate terminal of P 2 is connected to the keeper node. The input terminal of tri-state device 220 is connected to the node A and the output of tri-state device 220 is connected to the keeper node. Tri-state device 220 also receives SCa, which controls tri-state device 220 . The output of pass gate 210 is also connected to the keeper node.

In operation, when Fclk is active and D IN is logic 0, node A is logic 1because P 1 is on and N 1 is off. Since Fclk is active, SCa and SCb are inactive. Because SCa is off, tri-state device 220 functions as an inverter. Since node A is logic 1, the output of tri-state device 220 is logic 0, which drives the keeper node to logic 0. When the keeper node has a logic value 0, P 2 is turned on and N 3 is turned off. When P 2 is on and N 3 is off, the logic value 1 at D OUT is retained.

When Fclk is off, and SCa and SCb are on, tri-state device 220 functions as an open circuit and pass gate 210 is on. When pass gate 210 is on, S IN passes through pass gate 210 to the keeper node and SDL 204 is, subsequently, re-programmed to store S IN . It should be appreciated that the keeper node is sensitive to the loading because the keeper node is the storage element for SDL 204 . Consequently, the loading on the keeper node, in one embodiment, should be small but yet it is large enough to change the value of the keeper node.

FIG. 3 illustrates an embodiment of a circuit 300 having a SDL with a keeper node. Referring back to FIG. 3 , a scan cell 302 and an SDL 304 are disclosed. SDL 304 and block 204 of FIG. 2 are similar circuits. In one embodiment, scan cell 302 is a flip-flop scan circuit, which consists of two inverters I 1 , I 2 , four PMOS transistors, P 4 , P 5 , P 6 , P 7 , four NMOS transistors, N 4 , N 5 , N 6 , N 7 , and a tri-state device T 2 .

Transistors P 6 and N 6 , in one embodiment, form a pass gate 210 and transistors P 7 and N 7 form a pass gate 214 . Moreover, transistors P 4 and N 4 form an inverter 212 and transistors P 5 and N 5 form an inverter 216 . Other logic devices may be added to circuit 300 , but they are not necessary to understanding the invention.

In operation, when scan clocks, SCa and SCb are active and Fclk is inactive, pass gate 210 functions as a passing circuit and T 1 functions as an open circuit. Once T 1 is off and pass gate 210 is on, the logic stage at the keeper node may be programmed in response to S IN . Reprogram a SDL through a keeper node enhances the speed of reprogram. In other words, it takes less time to reprogram SDL using a keeper node.

When SCb is active, pass gate 214 is on which causes the output of inverter 212 to be connected to the input of inverter 216 . Because SCb is active, which causes T 2 to function as an inverter, the feedback loop from the output of inverter 216 to the input of inverter 216 through T 2 is formed. Other types of scan cell may also be used in the present invention.

FIG. 4 is a circuit diagram 400 illustrating an embodiment for implementing a tri-state function. Two PMOS transistors P 10 , P 11 and two NMOS transistors N 10 , N 11 , and an inverter 15 are shown in FIG. 4 . It should be appreciated that other types of transistor may be used in circuit diagram 400 to perform the same functions.

The source terminal of P 10 is coupled to a positive voltage supply and the drain terminal of P 10 is connected to the source terminal of P 11 . The gate terminal of P 10 is connected to a control input terminal 404 . The drain terminal of P 11 is connected to an output terminal 408 . The gate terminal of P 11 is connected to a data input terminal 406 . The drain terminal of N 10 is connected to the output terminal 404 and the source terminal of N 10 is connected to the drain terminal of N 11 . The gate terminal of N 10 is also connected to the data input terminal. The source terminal of N 11 is connected to a ground voltage supply and the gate terminal of N 11 is connected to the output of 15 . The input of 15 is connected to the control input terminal 404 .

In operation, when the control input terminal 404 is logic 0, both P 10 and N 11 are on, which causes circuit diagram 400 to function as an inverter. If the control input is logic 1, both P 10 and N 11 are off, which causes circuit diagram 400 to function as an open circuit. Other types of tri-state device may be used in this present invention to perform similar functions.

FIG. 5 is clock waveform 500 illustrating one embodiment of scan and system clocks. Waveforms of scan clocks, SCa, SCb, and waveforms of system clock Fclk are shown in FIG. 5 . As discussed previously, overlapping clock phase between the system clock and scan clocks is not permitted. Accordingly, when Fclk is active, SCa and SCb are inactive and similarly, when SCa and SCb are active, Fclk is inactive. In other words, when Fclk cycle is active, the scan clock cycles cannot be active. In an alternative embodiment, scan clocks SCa and SCb are non-overlapping scan clocks. For example, when SCa is 1, SCb cannot be 1 at the same time.

FIG. 6 is a block diagram 600 illustrating an embodiment of scan process for testing SRDC. Block 602 shows the suspension of the system clock Fclk. When Fclk is off and scan clocks are on, the logic state stored at the keeper node may be erased as shown in block 604 . At block 606 , the logic state at SDL is reset in response to the scan data via the keeper node. Other blocks may be added, but they are not necessary to understanding the present invention.

FIG. 7 is a flowchart 700 illustrating one embodiment of scan process for testing the SRDCs. The process starts at the start block and proceeds to block 702 where the process suspends a SRDC clock. The process turns on scan clocks SCa and SCb at block 706 . After SCa and SCb are active, the logic state stored at SDL is erased through the keeper node at block 707 . After block 707 , the process proceeds to block 708 . At block 708 , the process scans or flushes scan data having test patterns into the keeper node in response to SCa and Scb. After block 708 , the process, at block 710 , suspends scan clocks SCa, SCb and resumes the system clock Fclk. After block 710 , the process proceeds to block 712 .

At block 712 , the SRDC performs its logic functions in response to Fclk and the data stored at the keeper nodes. After block 712 , the process suspends Fclk at block 714 and subsequently, resumes scan clocks SCa, SCb. After block 714 , the process moves to block 716 . At block 716 , the result from the execution of the scan data is flushed out. The result is, subsequently, compared with the expected data. The outcome of the comparison is used to indicate whether the SRDC has any defects. After block 71 . 6 , the process moves to the end block where the process ends.

Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that the various embodiments shown and described by way of illustration are in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which in themselves recites only those features regarded as essential to the invention.

Thus, a method and a system for testing SRDCs using a scan circuit have been described.

Claims

1. A device comprising:a self-resetting dynamic circuit (“SRDC”) having a data output; and a testing circuit coupled to the data output and having a keeper node and a set-dominant latch to test the SRDC in response to at least one test clock.

2. The device of claim 1, wherein the testing circuit applies testing data to the keeper node.

3. The device of claim 1 further comprising a tri-state circuit coupled to the SRDC to prevent data contention.

4. The device of claim 1, wherein the testing circuit is a scan circuit including two scan clocks.

5. The device of claim 1, wherein the keeper node is located between a combination logic and a latch feedback.

6. The device of claim 1, wherein the keeper node stores logic states.

7. A method for testing a circuit comprising:suspending a self-resetting dynamic circuit (“SRDC”) clock; erasing logic state stored at a keeper node of a SRDC; and scanning testing data from a scan circuit to the SRDC through the keeper node.

8. The method of claim 7, wherein erasing the logic state stored at a keeper node further includes utilizing a tri-state device to suspend a feed back loop used to maintain a previous logic value.

9. The method of claim 7, wherein the scanning testing data further comprising:flushing scan data into a scan chain in response to a first and second scan clocks; suspending the first and second scan clocks; resuming the SRDC clock; executing the SRDC for a predefined number of cycles; suspending the SRDC clock and stopping execution; resuming the first and second scan clocks; and capturing a result of execution of the SRDC.

10. An apparatus for testing a circuit comprising:means for suspending a self-resetting dynamic circuit (“SRDC”) clock; means for erasing logic state stored at a keeper node of a SRDC; and means for scanning testing data from a scan circuit to the SRDC through the keeper node.

11. The apparatus of claim 10, wherein the means for erasing logic state further includes means for utilizing a tri-state device to suspend a feed back loop used to retain previous logic value.

12. The apparatus of claim 10, wherein the means for scanning testing data further comprising:means for flushing scan data into scan chain in response to a first and second scan clocks; means for suspending the first and second scan clocks; means for resuming the SRDC clock; means for executing the SRDC for a predefined number of cycles; means for suspending the SRDC clock and stopping execution; means for resuming the first and second scan clock; and means for capturing a result of execution of the SRDC.

13. A circuit for testing a logic circuit comprising:a first transistor having source, drain and gate terminals, the source terminal of the first transistor being coupled to a first power supply voltage, the drain terminal of the first transistor being coupled to a first node, the gate terminal of the first transistor receiving a data input; a second transistor having source, drain and gate terminals, the source terminal of the second transistor being coupled to a second node, the drain terminal of the second transistor being coupled to the first node, the gate terminal of the second transistor receiving the data input; a third transistor having source, drain and gate terminals, the source terminal of the third transistor being coupled to a second power supply voltage, the drain terminal of the third transistor being coupled to the second node, the gate terminal receiving a SRDC clock signal; a fourth transistor having source, drain and gate terminals, the source terminal of the fourth transistor being coupled to the first power supply voltage, the drain terminal of the fourth transistor being coupled to the first node, the gate terminal of the fourth transistor being coupled to a third node; a fifth transistor having source, drain and gate terminals, the source terminal of the fifth transistor being coupled to the second power supply voltage, the drain terminal of the fifth transistor being coupled to the second node, the gate terminal of the fifth transistor being coupled to the third node, a first tri-state device having an input, an output, a first clock input, and a second clock input, the input of the first tri-state device being coupled to the first node, the output of the first tri-state device being coupled to the third node, the first clock input of the first tri-state device being coupled to a first scan clock, the second clock input of the first tri-state device being coupled to a negative first scan clock; and a first scan pass gate having an input, output, and clock input, the input of the first scan pass gate being receiving a scan data, the output of the first scan pass gate being coupled to the third node, the clock input of the first scan pass gate receiving the first scan clock.

14. The circuit of claim 13 further comprising:a first inverter having an input and an output, the input of the first inverter being coupled to the third node; a second scan pass gate having an input, an output, and a clock input, the input of the second scan pass gate being coupled to the output of the first inverter, the clock input of the second scan pass gate receiving a second scan clock, a second inverter having an input and an output, the input of the second inverter being coupled to the output of the second scan pass gate; and a second tri-state device having an input, an output, a first clock input, and a second clock input, the input of the second tri-state device being coupled to the output of the second inverter, the output of the second tri-state device being coupled to the input of the second inverter, the first clock input of the second tri-state device being coupled to the second scan clock, the second clock input of the second tri-state device being coupled to a negative second scan clock.

15. A circuit comprising:a self-resetting dynamic circuit (“SRDC”) having at least one set dominant latch (“SDL”); and a scan circuit coupled to the SDL to scan data through the SRDC in response to at least one scan clock, when executed, the circuit causes the scan circuit to: suspend a system clock; erase logic state stored at the SDL; and scan the scan data from the scan circuit to the SDL.

16. The circuit of claim 15, further comprising a tri-state device coupled to the SRDC and configured to prevent store contention.

17. The circuit of claim 15, further comprising two non-overlapping scan clocks coupled to the scan circuit.

18. The circuit of claim 15, wherein the SDL further including a keeper node, the keeper node configured to receive the scan data.

19. The device of claim 1 further comprising a scan input circuit coupled to provide data to the testing circuit via the keeper node in response to at least one scan clock.

20. The device of claim 1 further comprising a scan input circuit coupled to receive data from the testing circuit via the keeper node in response to at least one scan clock.