Scanning methods, algorithms and patterns

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G01R31/318544

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318544Scanning methods, algorithms and patterns

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Scan chain analysis using predefined capture signature
- Patent number 12,216,161
- Issue date Feb 4, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Grant
Chip test circuit and circuit test method
- Patent number 12,181,519
- Issue date Dec 31, 2024
- Huawei Technologies Co., Ltd.
- Changming Cui
- G01 - MEASURING TESTING
Information Patent Grant
Fault detection method and related apparatus
- Patent number 12,174,254
- Issue date Dec 24, 2024
- Huawei Technologies Co., Ltd.
- Zhe Tao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan frame based test access mechanisms
- Patent number 12,117,490
- Issue date Oct 15, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit and test method
- Patent number 11,988,711
- Issue date May 21, 2024
- Realtek Semiconductor Corporation
- Po-Lin Chen
- G01 - MEASURING TESTING
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary scan test method and storage medium
- Patent number 11,933,845
- Issue date Mar 19, 2024
- SHENZHEN PANGO MICROSYSTEMS CO., LTD.
- Shiyjun Zhao
- G01 - MEASURING TESTING
Information Patent Grant
Shadow access port method and apparatus
- Patent number 11,906,582
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Single-pass diagnosis for multiple chain defects
- Patent number 11,789,077
- Issue date Oct 17, 2023
- Synopsys, Inc.
- Emil Gizdarski
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isolation circuit having test mechanism and test method thereof
- Patent number 11,774,497
- Issue date Oct 3, 2023
- Realtek Semiconductor Corporation
- Kuo-Kai Liu
- G01 - MEASURING TESTING
Information Patent Grant
Programmable scan chain debug technique
- Patent number 11,754,624
- Issue date Sep 12, 2023
- Seagate Technology LLC
- Bharat Londhe
- G01 - MEASURING TESTING
Information Patent Grant
Localization of multiple scan chain defects per scan chain
- Patent number 11,740,288
- Issue date Aug 29, 2023
- Synopsys, Inc.
- Emil I. Gizdarski
- G01 - MEASURING TESTING
Information Patent Grant
Computer-readable recording medium storing analysis program, analys...
- Patent number 11,693,054
- Issue date Jul 4, 2023
- Fujitsu Limited
- Daisuke Maruyama
- G01 - MEASURING TESTING
Information Patent Grant
Chip, chip testing method and electronic device
- Patent number 11,686,771
- Issue date Jun 27, 2023
- CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO., LTD.
- Yuqian Cedric Wong
- G01 - MEASURING TESTING
Information Patent Grant
Scalable scan architecture for multi-circuit block arrays
- Patent number 11,639,962
- Issue date May 2, 2023
- Xilinx, Inc.
- Niravkumar Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan frame based test access mechanisms
- Patent number 11,635,464
- Issue date Apr 25, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Method of updating firmware of chip stably and effectively, firmwar...
- Patent number 11,630,732
- Issue date Apr 18, 2023
- Fulian Precision Electronics (Tianjin) Co., LTD.
- Li-Yun Hao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced loopback diagnostic systems and methods
- Patent number 11,619,667
- Issue date Apr 4, 2023
- Advantest Corporation
- Mei-Mei Su
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-capture at-speed scan test based on a slow clock signal
- Patent number 11,614,487
- Issue date Mar 28, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Grant
Controller structural testing with automated test vectors
- Patent number 11,598,808
- Issue date Mar 7, 2023
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
Shadow access port integrated circuit
- Patent number 11,579,193
- Issue date Feb 14, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan apparatus capable of fault diagnosis and scan chain fault diag...
- Patent number 11,567,132
- Issue date Jan 31, 2023
- UIF (University Industry Foundation), Yonsei University
- Sungho Kang
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,561,258
- Issue date Jan 24, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase controlled codec block scan of a partitioned circuit device
- Patent number 11,519,964
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Extended JTAG controller and method for functional reset using the...
- Patent number 11,493,553
- Issue date Nov 8, 2022
- COMMSOLID GMBH
- Uwe Porst
- G01 - MEASURING TESTING
Information Patent Grant
Enabling isolated development mode in utility end points
- Patent number 11,448,698
- Issue date Sep 20, 2022
- Landis+Gyr Innovations, Inc.
- Pushpesh Kumar Deshmukh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and circuit for scan dump of latch array
- Patent number 11,443,823
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for row scannable latch array
- Patent number 11,443,822
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isometric control data generation for test compression
- Patent number 11,422,188
- Issue date Aug 23, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Yu Huang
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME
- Publication number 20250020719
- Publication date Jan 16, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mohammed Moiz Khan
- G01 - MEASURING TESTING
Information Patent Application
TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES
- Publication number 20240426907
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Shiv Kumar Vats
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Analysis Using Predefined Capture Signature
- Publication number 20240393394
- Publication date Nov 28, 2024
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY
- Publication number 20240339992
- Publication date Oct 10, 2024
- Samsung Electronics Co., Ltd.
- Mitesh GOYAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TESTING MULTI-CYCLE PATHS USING SCAN TEST
- Publication number 20240329135
- Publication date Oct 3, 2024
- ADVANCED MICRO DEVICES, INC.
- James A. Wingfield
- G01 - MEASURING TESTING
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE ACCESS PORT CIRCUITS
- Publication number 20240183903
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Automatic Test Pattern Generation-Based Circuit Verification Method...
- Publication number 20240125850
- Publication date Apr 18, 2024
- Huawei Technologies Co., Ltd
- Huiling Zhen
- G01 - MEASURING TESTING
Information Patent Application
PROCESSOR TEST PATTERN GENERATION AND APPLICATION FOR TESTER SYSTEMS
- Publication number 20240118340
- Publication date Apr 11, 2024
- Advantest Corporation
- Edmundo De La Puente
- G01 - MEASURING TESTING
Information Patent Application
INFIELD PERIODIC DEVICE TESTING WHILE MAINTAINING HOST CONNECTIVITY
- Publication number 20240103079
- Publication date Mar 28, 2024
- Intel Corporation
- Rakesh Kandula
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY
- Publication number 20230408581
- Publication date Dec 21, 2023
- Intel Corporation
- Rakesh Kandula
- G01 - MEASURING TESTING
Information Patent Application
TEST CIRCUIT AND TEST METHOD
- Publication number 20230288478
- Publication date Sep 14, 2023
- REALTEK SEMICONDUCTOR CORPORATION
- PO-LIN CHEN
- G01 - MEASURING TESTING
Information Patent Application
SCAN FRAME BASED TEST ACCESS MECHANISMS
- Publication number 20230258715
- Publication date Aug 17, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Fault Detection Method and Related Apparatus
- Publication number 20230258718
- Publication date Aug 17, 2023
- Huawei Technologies Co., Ltd
- Zhe Tao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP TEST CIRCUIT AND CIRCUIT TEST METHOD
- Publication number 20230204660
- Publication date Jun 29, 2023
- Huawei Technologies Co., Ltd
- Changming CUI
- G01 - MEASURING TESTING
Information Patent Application
TEST CIRCUIT IN CHIP AND CIRCUIT TEST METHOD
- Publication number 20230204661
- Publication date Jun 29, 2023
- Huawei Technologies Co., Ltd
- Yu HUANG
- G01 - MEASURING TESTING
Information Patent Application
SHADOW ACCESS PORT METHOD AND APPARATUS
- Publication number 20230194603
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY SCAN TEST METHOD AND STORAGE MEDIUM
- Publication number 20230120955
- Publication date Apr 20, 2023
- SHENZHEN PANGO MICROSYSTEMS CO.,LTD.
- Shiyjun ZHAO
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT, A METHOD FOR TESTING THE SEMICOND...
- Publication number 20230096746
- Publication date Mar 30, 2023
- Samsung Electronics Co., Ltd.
- Hyungil WOO
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF UPDATING FIRMWARE OF CHIP STABLY AND EFFECTIVELY, FIRMWAR...
- Publication number 20230063485
- Publication date Mar 2, 2023
- Fulian Precision Electronics (Tianjin) Co., LTD.
- LI-YUN HAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING ISOLATED DEVELOPMENT MODE IN UTILITY END POINTS
- Publication number 20220317187
- Publication date Oct 6, 2022
- Landis+Gyr Innovations, Inc.
- Pushpesh Kumar Deshmukh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SCAN FRAME BASED TEST ACCESS MECHANISMS
- Publication number 20220163585
- Publication date May 26, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SINGLE-PASS DIAGNOSIS FOR MULTIPLE CHAIN DEFECTS
- Publication number 20220128628
- Publication date Apr 28, 2022
- Synopsys, Inc.
- Emil Gizdarski
- G01 - MEASURING TESTING
Information Patent Application
Isolation circuit having test mechanism and test method thereof
- Publication number 20220120812
- Publication date Apr 21, 2022
- REALTEK SEMICONDUCTOR CORPORATION
- KUO-KAI LIU
- G01 - MEASURING TESTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20220113351
- Publication date Apr 14, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CAPTURE AT-SPEED SCAN TEST BASED ON A SLOW CLOCK SIGNAL
- Publication number 20220018902
- Publication date Jan 20, 2022
- Siemens Industry Software Inc.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
SHADOW ACCESS PORT METHOD AND APPARATUS
- Publication number 20210396807
- Publication date Dec 23, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
EXTENDED JTAG CONTROLLER AND METHOD FOR FUNCTIONAL RESET USING THE...
- Publication number 20210325461
- Publication date Oct 21, 2021
- COMMSOLID GMBH
- Uwe PORST
- G01 - MEASURING TESTING
Information Patent Application
PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE
- Publication number 20210311121
- Publication date Oct 7, 2021
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING

Scanning methods, algorithms and patterns

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Scan chain analysis using predefined capture signature

Chip test circuit and circuit test method

Fault detection method and related apparatus

Scan frame based test access mechanisms

Test circuit and test method

Single “A” latch with an array of “B” latches

Boundary scan test method and storage medium

Shadow access port method and apparatus

Single-pass diagnosis for multiple chain defects

Wafer scale testing using a 2 signal JTAG interface

Isolation circuit having test mechanism and test method thereof

Programmable scan chain debug technique

Localization of multiple scan chain defects per scan chain

Computer-readable recording medium storing analysis program, analys...

Chip, chip testing method and electronic device

Scalable scan architecture for multi-circuit block arrays

Scan frame based test access mechanisms

Method of updating firmware of chip stably and effectively, firmwar...

Enhanced loopback diagnostic systems and methods

Multi-capture at-speed scan test based on a slow clock signal

Controller structural testing with automated test vectors

Shadow access port integrated circuit

Scan apparatus capable of fault diagnosis and scan chain fault diag...

Wafer scale testing using a 2 signal JTAG interface

Phase controlled codec block scan of a partitioned circuit device

Extended JTAG controller and method for functional reset using the...

Enabling isolated development mode in utility end points

Method and circuit for scan dump of latch array

Method and circuit for row scannable latch array

Isometric control data generation for test compression

Patents Applicationslast 30 patents

SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME

TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES

Scan Chain Analysis Using Predefined Capture Signature

LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY

TESTING MULTI-CYCLE PATHS USING SCAN TEST

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

MULTIPLE ACCESS PORT CIRCUITS

Automatic Test Pattern Generation-Based Circuit Verification Method...

PROCESSOR TEST PATTERN GENERATION AND APPLICATION FOR TESTER SYSTEMS

INFIELD PERIODIC DEVICE TESTING WHILE MAINTAINING HOST CONNECTIVITY

INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY

TEST CIRCUIT AND TEST METHOD

SCAN FRAME BASED TEST ACCESS MECHANISMS

Fault Detection Method and Related Apparatus

CHIP TEST CIRCUIT AND CIRCUIT TEST METHOD

TEST CIRCUIT IN CHIP AND CIRCUIT TEST METHOD

SHADOW ACCESS PORT METHOD AND APPARATUS

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

BOUNDARY SCAN TEST METHOD AND STORAGE MEDIUM

SEMICONDUCTOR INTEGRATED CIRCUIT, A METHOD FOR TESTING THE SEMICOND...

METHOD OF UPDATING FIRMWARE OF CHIP STABLY AND EFFECTIVELY, FIRMWAR...

ENABLING ISOLATED DEVELOPMENT MODE IN UTILITY END POINTS

SCAN FRAME BASED TEST ACCESS MECHANISMS

SINGLE-PASS DIAGNOSIS FOR MULTIPLE CHAIN DEFECTS

Isolation circuit having test mechanism and test method thereof

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

MULTI-CAPTURE AT-SPEED SCAN TEST BASED ON A SLOW CLOCK SIGNAL

SHADOW ACCESS PORT METHOD AND APPARATUS

EXTENDED JTAG CONTROLLER AND METHOD FOR FUNCTIONAL RESET USING THE...

PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE