Patent Application
20230067357
The present invention relates generally to the field of semiconductor memory device technology and more particularly to resistive random-access memory devices.
Resistive random-access memory (ReRAM or RRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance or changing the resistance across a dielectric solid-state material, often referred to as a memristor. A conventional RRAM consists of a dielectric material sandwiched between two electrodes.
RRAM formation is based on the concept that a dielectric material, which is normally insulating, can be made to conduct through a filament or conduction path formed in the dielectric material after the application of a sufficiently high voltage. RRAM device operation typically uses the change of resistance that occurs under the application of the applied electric field for RRAM device switching. Resistance switching has been observed in a variety of oxides, but binary metal oxides are typically preferred as a switching material for non-volatile memory applications primarily due to their compatibility with the complementary metal-oxide-semiconductor (CMOS) processing.
Creating an RRAM device for resistive switching typically involves generating oxygen vacancies, typically created at oxide bond locations, where the oxygen has been removed. The oxygen vacancies charge and drift under applied electric fields. The motion of the oxygen ions and vacancies in the oxide can be analogous to the motion of electrons and holes in a semiconductor material. A conduction path or a filament can arise from different mechanisms, including vacancy or metal defect migration. Typically, once the filament in the dielectric material is formed, the filament may be reset or broken. The reset or breaking of the filament in the dielectric material results in high resistance. The filament can be set or re-formed by another voltage or applied electric field, resulting in a lower resistance in the dielectric material. In some cases, many current paths, rather than a single filament, can be involved in typical RRAM applications.
Embodiments of the present invention provide an array of individual memory cells forming a crossbar array. The crossbar array includes a plurality of individual memory cells that are on a first metal layer where each of the individual memory cells has a top electrode contact and a bottom electrode contact in a second metal layer. The crossbar array includes a word line above each of the individual memory cells connecting one or more adjacent top electrode contacts and a bit line above each of the individual memory cells connecting one or more of the adjacent bottom electrode contacts.
Embodiments of the present invention provide a method of forming a plurality of memory cell devices in a crossbar array of memory cell devices. The method includes forming a plurality of memory cell devices, where each memory cell device is formed on a portion of a first metal layer and has a bottom electrode contact and a top electrode contact formed in a second metal layer. The method includes performing a plasma process on each of the plurality of top electrode contacts and each of the plurality of bottom electrode contacts in each memory cell where the plasma process creates a conductive filament in a resistive switch device in each memory cell. The method includes using a dual damascene process to form a plurality of second vias in a deposited layer of an interlayer dielectric material and a plurality of word lines and a plurality of bit lines in a third metal layer.
The above and other aspects, features, and advantages of various embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.
Embodiments of the present invention recognize that typical forming voltages for resistive random-access memory (ReRAM, or RRAM) devices utilizing dielectric materials, such as a hafnium oxide can be in the three to three and a half voltage range which is above the required forming voltage for advanced RRAM device technologies with 14 nm or less feature size. In advanced RRAM devices, the desired forming voltages are in the two-volt range or less for the electroforming process to create a conductive filament in the RRAM device. Embodiments of the present invention recognize that an emerging method of forming the conductive filament in a typical crossbar array of connected RRAM devices employs a plasma process to induce a charging voltage to form the conductive bridge or conductive filament in the RRAM devices. Embodiments of the present invention recognize the plasma process produces an antenna effect on the RRAM device that has been shown to form conductive filaments or pre-form conductive filaments with less than two volts of forming voltage in RRAM devices with hafnium oxide dielectric materials.
Embodiments of the present invention recognize that when the plasma process is applied on electrodes of a conventional crossbar array of connected RRAM devices not all of the individual resistive switches or RRAM devices create a conductive filament at the same time. When one or more of the RRAM devices in a conventional crossbar array form a conductive filament ahead of the other RRAM devices in the crossbar array, the first formed conductive filaments can shunt the remaining forming voltage generated by the plasma process through the first forming conductive filaments in the one or more RRAM devices that that first form a conductive filament. Embodiments of the present invention recognize that in this case, conductive filaments may not be formed in some of the remaining RRAM devices.
Embodiments of the present invention recognize that an ability to form a conductive filament in each of the RRAM devices in a crossbar array of RRAM devices is desirable. Embodiments of the present invention recognize that a method and a semiconductor structure to form a crossbar array of RRAM devices using a plasma treatment to lower the forming voltage and that forms a conductive filament in each RRAM device in the crossbar array would be beneficial.
Embodiments of the present invention provide a structure and method of forming the structure for a crossbar array of individual memory unit cells that have a pre-formed conductive filament in each of the resistive switch devices in the individual memory unit cells before the individual memory unit cells are connected in the crossbar array. Embodiments of the present invention provide individual memory unit cells on a first metal layer with top electrode contacts and bottom electrode contacts in a second metal layer, where each of the individual memory unit cells are not connected during the plasma process that forms the conductive filaments in each of the individual memory unit cells. The crossbar array is formed after the individual memory unit cells are plasma treated to form the conductive filament in each of the resistive switch devices.
Embodiments of the present invention provide a crossbar array composed of word lines and bit lines that are formed in a third metal layer above the individual memory unit cells. The crossbar array of word lines and bit lines are formed in a third metal layer after the plasma process. The word lines and the bit lines connect adjacent memory unit cells with a pre-formed conductive filament.
Embodiments of the present invention provide individual memory unit cells where each individual memory unit cell includes a resistive switch device and a via on a portion of a first metal layer and a top electrode contact in a second metal layer that is above and connected to each resistive switch device in each of the individual memory cells and a bottom electrode contact in the second metal layer that is above and connected to a via on the first metal layer (e.g., the Mx metal layer). Each of the individual memory unit cells are connected by vias on one of a top electrode contact or a bottom electrode contact in the second metal layer (e.g., the Mx+1 metal layer) to lines in a third metal layer (e.g., the Mx+2 metal layer) above the memory unit cells.
Embodiments of the present invention provide a crossbar array composed of a plurality of lines in the Mx+2 metal above and connected to individual memory unit cells. Embodiments of the present invention provide bit lines in the Mx+2 metal layer that form a portion of the crossbar array over the individual memory unit cells. The bit lines are connected to more than one adjacent bottom electrode contacts in the Mx+1 metal layer by the via formed on each of the top electrode contacts. The word lines in the Mx+2 metal layer of the crossbar array connect by vias to more than one adjacent top electrode contacts in the Mx+1 metal layer. The bit lines run in one direction and the word lines run in a perpendicular direction to the bit lines in the crossbar array. The bit lines can run parallel to other bit lines connecting the bottom electrode contacts and the word lines can run parallel to other word lines in the crossbar array of RRAM devices.
Embodiments of the present invention provide a method of forming a crossbar array of a plurality of individual memory unit cells each memory unit cell includes a portion of the Mx metal layer with a resistive switch device and a via on the portion of the Mx metal layer and a top electrode contact and a bottom electrode in a second metal layer (e.g., Mx+1 metal layer) that are connected to the portion of the Mx metal layer by the via. A conductive filament is formed using a plasma process on the top and bottom electrode contacts of unconnected individual memory unit cells prior to forming the crossbar array of word and bit lines in the third metal layer (e.g., Mx+2 metal layer).
Embodiments of the present invention provide a method of creating a plurality of individual memory unit cells on a portion of a first or the Mx metal layer by forming a resistive switch device and a via on a portion of the Mx metal layer. In an embodiment, an interlayer dielectric is deposited and a top electrode contact is formed over the resistive switch device and bottom electrode contact is formed in the Mx+1 metal layer over the via on the first metal layer.
Embodiments of the present invention provide a method of forming top electrode contacts and bottom electrode contacts with a large metal surface area. The top electrode contacts and the bottom electrode contacts are exposed to the plasma process to induce an antenna effect. The plasma process, using the antenna effect, generates a forming voltage that forms or pre-forms the conductive filament in the resistive switch device in each memory unit cell. Embodiments of the present invention provide an exposed top surface area of the top electrode contact that is at least 1.2 times larger than the top surface area of the bottom electrode contact. Ideally, the surface area of the top electrode is maximized within the allowed area of the grid or array of the individual memory cells and the surface area of the bottom electrode is minimized in order to enhance the antenna effect of the plasma process. When the plasma process is applied, each of the memory unit cells are not connected and each of the top electrode contacts and bottom electrode contacts are not connected.
Embodiments of the present invention provide the method where the conductive filament is formed by a plasma process that is applied on the exposed top surfaces of the top and bottom electrode contacts of each memory unit cell in an array of many memory unit cells prior to creating the crossbar array of word lines and bit lines. In other words, the plasma process is applied to the top surfaces of the bottom electrode contacts and the top electrode contacts of each of the individual, unconnected memory unit cells.
Since each of the individual memory unit cells with a resistive switch device are not connected to each other during the plasma process then, if a conductive filament forms first in one of the individual memory unit cells during the plasma process, the plasma generated forming or charging voltage would not shunt through the first filament-forming resistive switch device (i.e., RRAM device). In this way, embodiments of the present invention provide a plurality of individual memory unit cells where after the plasma process, each of the individual memory units cells has a resistive switch device with a conductive filament that is formed during the plasma process.
Embodiments of the present invention provide a crossbar array that is formed after the plasma process forms the conductive filaments in the resistive switch devices in each of the individual memory unit cells. The crossbar array is by creating a plurality of word lines and bit lines in the Mx+2 metal layer. The plurality of word lines and bit lines forming the crossbar connect by a plurality of vias the bottom electrode contacts and the top electrode contacts in the second metal layer. Each via connects to one of the lines to one of the top electrode contacts or the bottom electrode contacts of an adjacent memory unit cell. Each of the lines contact at least two vias to join at least two adjacent top electrode contacts or at least two adjacent bottom electrodes in one or more adjacent memory unit cells.
Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits, such as semiconductor devices. The present embodiments can be practiced in conjunction with the integrated circuit fabrication techniques currently used in the art, for RRAM devices forming a crossbar array, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the described embodiments. The figures represent cross-section portions of a RRAM device after fabrication and are not drawn to scale, but instead are drawn to illustrate the features of the described embodiments. Specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
References in the specification to “one embodiment”, “other embodiment”, “another embodiment”, “an embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “over”, “on”, “positioned on”, or “positioned atop” mean that a first element is present on a second element wherein intervening elements, such as an interface structure, may be present between the first element and the second element. The term “direct contact” means that a first element and a second element are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In the interest of not obscuring the presentation of the embodiments of the present invention, in the following detailed description, some of the processing steps, materials, or operations that are known in the art may have been combined for presentation and for illustration purposes and in some instances may not have been described in detail. Additionally, for brevity and maintaining a focus on distinctive features of elements of the present invention, description of previously discussed materials, processes, and structures may not be repeated with regard to subsequent Figures. In other instances, some processing steps or operations that are known may not be described. It should be understood that the following description is rather focused on the distinctive features or elements of the various embodiments of the present invention.
Deposition processes as used herein include but are not limited to chemical vapor deposition (CVD), plasma vapor deposition (PVD), electroplating, ionized plasma vapor deposition (iPVD), atomic layer deposition (ALD), and plasma-enhanced chemical vapor deposition (PECVD).
As known to one skilled in the art, typical BEOL processes discussed herein include dual damascene, single damascene, and subtractive metal etching processes. Dual damascene process is most commonly used for BEOL patterning and metallization processes. A dual damascene process typically includes patterning via and trench in a dielectric material, such as an interlayer dielectric and filling the via holes and trenches with a layer of metal and planarizing the metal using a chemical mechanical (CMP) process to remove overburden or excess metal. The single damascene process includes patterning via holes in a first dielectric material, filling the via holes with a deposited metal layer, and then preforming a CMP to remove overburden or excess metal and then depositing a second dielectric material and then, performing a second etch process to form trenches, filling the trenches with metal layers and then performing a CMP to remove the overburden of metal layers. In some embodiments, a subtractive metallization process is used where a metal layer is deposited, patterned, etched, and a dielectric material is deposited over the top surface. A CMP exposes the top surface of the patterned metal.
Patterning processes discussed herein include but are not limited to one of lithography, photolithography, an extreme ultraviolet (EUV) lithography process, or any other known semiconductor patterning process that is followed by one or more of the following etching processes discussed below.
Etching processes discussed herein to remove portions of material as patterned or masked by the lithography process includes etching processes, such as dry etching process using a reactive ion etch (RIE), or ion beam etch (IBE), a wet chemical etch process, or a combination of these etching processes and is not limited to these etching processes.
Mx metal 10 may be a portion of any metal layer formed in the back end of the line (BEOL) of a semiconductor chip or in a portion of a metal layer formed in the middle of the line (MOL) of a semiconductor chip. After Mx metal 10 is formed with known metallization processes and CMP, in an embodiment, a SiN, a SiCN material, or a similar material (not depicted) may be deposited on Mx metal 10 as a cap. Mx metal 10 may be composed of, but is not limited to typical BEOL metals, which include Cu, Cu—Mn, W, Ru, or Co. The width of Mx metal 10 is greater than the width of RSD 11. The length of Mx metal 10 may be two to five times the width of RSD 11 but, is not limited to these lengths.
RSD 11 can be created using known RRAM device formation processes. In various embodiments, RSD 11 includes a bottom electrode on Mx metal 10, a switching layer, and top electrode metal. The bottom electrode, the switching layer, and the top electrode of RSD 11 are not depicted in
A width of RSD 11 may range from 10 to 1000 nanometers but is not limited to these widths. RSD 11 is patterned using known lithography processes, such as photolithography and etched, for example using a reactive ion etching (RIE) plasma process.
In various embodiments, via 12 is formed using conventional or damascene via formation processes that includes depositing a dielectric material, patterning the dielectric material using lithography, and etching the dielectric material (e.g., using RIE) to form a hole for via 12 followed by a via metal deposition and planarization using a CMP. Via 12 can be formed with any conductive material used for vias in memory devices. For example, via 12 may be composed of copper or tungsten but is not limited to these metals.
In another embodiment, via 12 is formed using a dual damascene process that creates via 12 together with top electrode contact (TEC) 21 and bottom electrode contact (BEC) 20 (not depicted in
In an embodiment, using a subtractive process after forming structure 100 depicted in
In other embodiments, using a single damascene process, a layer of ILD (e.g., ILD 25 in
In yet another embodiment, via 12, BEC 20, and TEC 21 are formed using the dual damascene process. In this embodiment, via 12 is not formed in
As depicted in
For the purposes of the present invention, hereinafter, structure 200 is called memory cell 200. Memory cell 200 is composed of Mx metal 10, RSD 11, via 12, TEC 21, and BEC 20. In various embodiments, memory cell 200 is a RRAM device with electrode contacts (e.g., BEC 20 and TEC 21). The RRAM device is modified from a conventional RRAM device to include the electrode contacts that are in the Mx+1 metal layer that is directly above Mx metal 10. The electrode contacts, such as BEC 20 and TEC 21 each contact one of via 12 or RSD 11 on Mx metal 10, respectively. Each of memory cells 200 have one via 12, one RSD 11, a TEC 21 with a top surface area that is at least 1.2 times greater than the top surface area of BEC 20 in the memory cell.
After forming memory cell 200, a plasma process is performed on exposed top surfaces of BEC 20 and TEC 21. In various embodiments, a conductive filament (not depicted) forms in the switching layer (not depicted) of RSD 11 during the plasma process. As previously discussed, the conductive filament may form in the dielectric material of the switching layer of RSD 11 during plasma processing due to the antenna effect when the plasma is applied to TEC 21 and BEC 20. When the plasma process occurs, TEC 21 and BEC 20 collect a charge creating the conductive filaments in RSD 11. For example, the plasma process uses a gas including, but not limited to, argon, nitrogen, hydrogen, helium, xenon, ammonia, or mixtures thereof with a pressure range from 1 mTorr to 3 Torr, and a duration of 5 seconds to 15 minutes but is not limited to these parameters. The plasma process can utilize an inductively coupled plasma (ICP) tool, a capacitively coupled plasma (CCP) tool, or a microwave generated plasma tool. In another embodiment of the present application, an e-beam treatment is performed. The e-beam treatment can include using an electron energy from 0.01 kV to 100 kV, and an electron beam dose of 100 μC/cm2 to 5000 μC/cm2 but is not limited to these parameters. The plasma process occurs before forming the crossbar array depicted in
If TEC 21 is formed using a subtractive metallization process as depicted in
If a damascene process is used to form TEC 21 and BEC 20 (not depicted in
If BEC 20 and TEC 21 are formed using a subtractive metallization process as depicted in
If a damascene process is used to form BEC 20 and TEC 21, the height of the deposited ILD 25 should be the same as the height as the exposed surfaces of TEC 21 and BEC 20 after using a CMP to remove the overburden or excess BEOL metal deposited in the trenches etched in ILD 25 to form BEC 20 and TEC 21.
Any number of memory cells 200 can be formed for the array of memory cells 200 depicted in
In
In various embodiments, the array of memory cells 200 are formed simultaneously. In other words, each of the processes to form each of RSD 11 occurs at once and each of the processes to form each of via 12 occur at the same time, etc. Similarly, the processes to form each of BEC 20 and TEC 21 in the metal layer above vias 12 and RSD 11 occur at the same time.
Once array 500 of the individual memory cells 200 depicted in
As previously discussed, when a conventionally formed crossbar array of connected memory cells is plasma treated to form conductive filaments in each of the resistive switch devices in a conventionally formed crossbar array, if one of the resistive switch devices are connected in the conventional crossbar array of memory cells forms a conductive filament before the other resistive switch devices, then the plasma generated antenna voltage to form conductive filaments may be shunted through this early conductive filament-forming resistive switch device. In this case, the desired conductive filaments may not form in the other remaining resistive switch devices in the conventionally formed crossbar array structure.
However, when applying the plasma process to each of the individual memory cells 200 in array 500 that are not connected, if one of RSD 11 forms a conductive filament ahead of the rest of RSDs 11 in array 500, then the plasma process in the other memory cells 200 continues to form the conductive filaments in the other memory cells 200 since they are not connected.
By performing the plasma processes on BEC 20 and TEC 21 of each of individual memory cells 200 that are not connected ensures that a conductive filament is formed in each RSD 11 in each memory cell 200 since the voltage generated by the plasma process cannot be shunted to one RSD 11 in array 500 since each RSD 11 in array 500 is not connected to another RSD 11 and therefore, the plasma process generated voltage is applied to each unconnected RSD 11 in array 500 to form a conductive filament in each RSD 11 of array 500.
In various embodiments, vias 62, connection links 60 and connection links 61 are formed using conventional dual damascene processes (e.g., ILD deposit, ILD pattern, ILD etch, BEOL metal deposit, and CMP) to form vias 62, connection links 60 and connection links 61. In this case, vias 12, connection links 60, and connection links 61 can be formed after the plasma process is performed on each of BEC 20 and TEC 21 (e.g., forms the conductive filament in each RSD 11 in each of memory cells 200). Vias 62 provide an electrical connection from one of BEC 20 or TEC 21 to one of connection links 60 or connection links 61, respectively to form crossbar array 600.
In various embodiments, connection link 60 provides a connection from one BEC 20 in one of memory cells 200 to a BEC 20 in an adjacent memory cell of memory cells 200. As depicted in
In various embodiments, one of connection links 61 provides a connection from one TEC 21 in one of memory cells 200 to another TEC 21 in an adjacent memory cell of memory cells 200 as depicted in
As depicted, connection links 60 using vias 62, BEC 20, and vias 12 (not visible in
Each of connection links 60 and connection links 61 may connect any number of memory cells 200. For example, connection link 60 may connect two memory cells 200 or may connect twenty or more memory cells 200. In various embodiments, connection links 60 and connection links 61 connect the same number of memory cells 200 to form crossbar array 600. In some embodiments, connection links 60 and connection links 61 each connect a different number of memory cells 200 in crossbar array 600. For example, connection links 60 connects twenty memory cells 200, and connection links 61 connects thirty memory cells 200.
As depicted,
In step 902, the method includes forming a resistive switch device on each portion of the Mx metal layer (e.g., Mx metal 10 in
In step 904, the method includes depositing an interlayer dielectric material (ILD). This can be the first deposited ILD (e.g., ILD 15 in
In step 906, the method includes forming via holes and trenches in the deposited ILD using a dual damascene process. The patterning and etching of the deposited ILD may occur using photolithography and RIE. An ILD patterning and etching, for example with RIE of the deposited ILD forms the via holes on each portion of the Mx metal layer and the trenches that will electrode contacts later in step 908.
In step 908, the method includes depositing a BEOL metal material. A layer of a BEOL metal material is deposited over the structure (e.g., over the exposed surface of the ILD and portions of the Mx metal layer). The BEOL metal material, such as Cu or W can be deposited in each of the via holes and trenches. A CMP of the deposited BEOL metal material completes the formation of one or more vias on the portion of the Mx metal layer and a plurality of top and bottom electrode contacts in the Mx+1 metal layer.
In step 910, the method includes performing a plasma process to form a conductive filament in the dielectric material in each of the resistive switch devices (e.g., RSD 11). The plasma process discussed in detail with respect to
In step 912, the method includes depositing another ILD over the structure (e.g., over the exposed portions of the previously deposited or first ILD and the remaining portions of the Mx+1 metal layer (e.g., over the exposed top surfaces of the top and bottom electrode contacts depicted as TEC 21 and BEC 20 in
In step 914, the method includes forming via holes and trenches in the most recently deposited or a second ILD using the dual damascene process. Via holes and trenches are patterned and etched in the second ILD.
In step 916, the method includes depositing a BEOL metal material for the Mx+2 metal layer over exposed surfaces of the second ILD and the exposed portions of the Mx+1 metal layer (e.g., BEC 20 and TEC 21 depicted in
The flowchart in the figures illustrates the operation of one possible implementation of the methods and device fabrication steps according to various embodiments of the present invention and is not intended to limit the methods to create the embodiments of the present invention. As known to one skilled in the art, the semiconductor structures illustrated in embodiments of the present invention may be created using different methods (e.g., subtractive metallization processes or damascene metallization processes). Furthermore, each block in the flowchart may represent a process or a portion of processes, which comprises one or more fabrication steps for manufacturing the specified device(s). In some alternative implementations, the processes noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
The methods as described herein can be used in the fabrication of integrated circuit chips or semiconductor chips. The resulting semiconductor chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the semiconductor chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both of surface interconnections and buried interconnections). In any case, the semiconductor chip is then integrated with other semiconductor chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes semiconductor chips, ranging from toys and other low-end applications to advanced computer products having a display, memory, a keyboard or other input device, and a central processor.
