Patent Grant
10468183
This application claims the benefit of priority to Korean Patent Application No. 10-2016-0003087, filed on Jan. 11, 2016 with the Korean Intellectual Property Office, the entirety of which is incorporated herein by reference.
The present disclosure relates to an inductor and a method of manufacturing the same.
Laminated inductors generally have a structure in which a plurality of insulating layers, including conductive patterns, are stacked. Such conductive patterns are commonly sequentially connected by conductive vias formed in the insulating layers and overlapped in a stacking direction, thereby forming a coil having a spiral structure. In addition, both ends of the coil may extend outwards from surfaces of the laminated structure, to be connected to an external terminal.
Inductors are mainly surface mounted devices (SMD) mounted on a circuit board. In particular, high-frequency inductors, used for signals within a high frequency band, equal to or higher than 100 MHz, have recently been increasingly used in the telecommunications market. One important issue related to the use of high-frequency inductors is to ensure sufficient quality-factor (Q-factor) characteristics, representing the efficiency of a chip inductor, therein. Here, the symbol Q, as expressed mathematically, Q=wL/R, is a ratio of inductance L to resistance R in a given frequency band.
Since an inductor is manufactured in accordance with a specific nominal inductance value L, resistance R needs to be lowered in order to enhance Q-characteristics at the same inductance value L. In order to lower resistance R, a thickness of a coil pattern may be increased. A coil pattern may be formed using a screen printing method, a method in which limitations exist in increasing the thickness of the coil pattern. In addition, when a relatively thick coil pattern is formed on a ceramic layer, failures such as cracking and delamination may occur during a process of stacking a plurality of sheets including the coil patterns, due to a difference in thickness between a portion of a sheet on which a coil pattern is formed and a portion of a sheet on which a coil pattern is not formed.
Furthermore, vias connecting the coil patterns may be formed by electroplating a metal or by printing a conductive paste (a metal paste). When the vias are formed by the electroplating method, interlayer insulating distances may not be uniform, since hardness of the metal increases during the process of stacking the plurality of sheets. When the vias are formed using the conductive paste, however, Q-characteristics may be degraded, since the resistance of the coil may be increased.
Accordingly, research has been conducted into a structure of an inductor ensuring a uniform insulating distance while also reducing the resistance of the coil.
An exemplary embodiment in the present disclosure provides an inductor including a via having first and second conductive layers, thereby reducing the resistance of the coil and improving Q-characteristics thereof.
According to an exemplary embodiment in the present disclosure, an inductor includes a body including a coil, the coil including a plurality of coil patterns connected by a via. The via includes a first conductive layer and a second conductive layer formed on the first conductive layer, and the second conductive layer includes a conductive powder and an organic material. Resistance of the coil may be lowered and Q-characteristics may be improved.
According to another exemplary embodiment in the present disclosure, a method of forming an inductor includes forming a coil pattern on a substrate, forming an insulating layer to cover the coil pattern on the substrate, forming a through-hole in the insulating layer, forming a first conductive layer in the through-hole, forming a second conductive layer by printing a conductive paste on the first conductive layer, separating the substrate from the insulating layer including the coil pattern and the first and second conductive layers, and forming a body by stacking a plurality of the separated insulating layers.
The above and other aspects, features, and advantages will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
Hereinafter, embodiments will be described as follows with reference to the attached drawings. In the drawings, shapes and sizes of components may be exaggerated or minimized for clarity.
The present disclosure may, however, be exemplified in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Throughout the specification, it will be understood that when an element, such as a layer, region or wafer (substrate), is referred to as being “on,” “connected to,” or “coupled to” another element, it can be directly “on,” “connected to,” or “coupled to” the other element or other elements intervening therebetween may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element, there may be no other elements or layers intervening therebetween. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be apparent that though the terms first, second, third, etc. may be used herein to describe various members, components, regions, layers and/or sections, these members, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, component, region, layer or section from another region, layer or section. Thus, a first member, component, region, layer or section discussed below could be termed a second member, component, region, layer or section without departing from the teachings of the exemplary embodiments.
Spatially relative terms, such as “above,” “upper,” “below,” and “lower” and the like, may be used herein for ease of description to describe one element's relationship relative to another element(s) as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “above,” or “upper” relative to other elements would then be oriented “below,” or “lower” relative to the other elements or features. Thus, the term “above” can encompass both the above and below orientations depending on a particular direction of the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.
The terminology used herein describes particular embodiments only, and the present disclosure is not limited thereby. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” and/or “comprising” when used in this specification, specify the presence of stated features, integers, steps, operations, members, elements, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, members, elements, and/or groups thereof.
Hereinafter, embodiments of the present disclosure will be described with reference to schematic views illustrating embodiments of the present disclosure. In the drawings, for example, due to manufacturing techniques and/or tolerances, modifications of the shape shown may be estimated. Thus, embodiments of the present disclosure should not be construed as being limited to the particular shapes of regions shown herein, for example, to include a change in shape results in manufacturing. The following embodiments may also be constituted by one or a combination thereof.
The contents of the present disclosure described below may have a variety of configurations and propose only a required configuration herein, but are not limited thereto.
Hereinafter, an inductor 100 according to an exemplary embodiment in the present disclosure will be described.
Referring to
Although not illustrated in the drawings, the body 110 may include a first main surface, a second main surface, and a side surface connecting the first main surface to the second main surface. The side surface may be a surface in a direction perpendicular to a direction in which insulating layers are stacked.
Normally, a body of an inductor is formed by stacking and sintering a plurality of ceramic layers in which coil patterns are formed. In this case, cracking or delamination between the ceramic layers may occur due to a difference in thickness between a portion of a ceramic layer on which the coil pattern is formed and a portion of a ceramic layer on which the coil pattern is not formed.
The body 110 of the inductor 100, according to the present exemplary embodiment, may be formed of an insulating material. Since the body 110 is formed of the insulating material, there is no difference in levels caused by the coil patterns. Accordingly, defects such as cracks may be prevented. In addition, since the inductor 100, according to the present exemplary embodiment, has a low dielectric constant compared to a normal inductor formed of a ceramic material, parasitic capacitance may be reduced, and thereby Q-characteristics of the inductor may be ensured.
The body 110 may be formed by stacking insulating layers 111.
The insulating material may include at least one of a photosensitive material, an epoxy-based material, an acryl-based material, a polyimide-based material, a phenol-based material, and a sulfone-based material.
After the insulating layers 111 are stacked and cured, interfaces between the insulating layers 111 may be blurred and hardly distinguished. A shape and size of the body 110 and the number of stacks of the insulating layers 111 are not specifically limited to those illustrated in the exemplary embodiment of the present disclosure.
The body 110 may include the coil 120.
The coil 120 may include a material containing silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.
End portions of the coil 120 may extend outwards from both side surfaces of the body 110 and be electrically connected to an external electrode.
The coil 120 may have a spiral structure in which the plurality of coil patterns are sequentially connected through the vias 130 and overlapped in a stacking direction thereof.
The vias 130 may be disposed to be spaced apart from each other, between the insulating layers 111.
Here, a cover layer (not shown) may be formed on at least one of a top surface and a bottom surface of the body 110, in order to protect the coil 120 disposed in the body 110.
The cover layer may be formed by printing a paste formed of the same material as the insulating layers 111 in a predetermined thickness.
Commonly, inductors include vias connecting coil patterns formed by electroplating or by using a conductive paste. When an inductor includes a via formed using the conductive paste, resistance of a coil of the inductor may increase and Q-characteristics of the inductor may be lowered, since the conductive paste has a high volume resistivity. When an inductor includes a via formed by electroplating, however, interlayer insulating distances may not be uniform since the via is formed only of a metal and thus has a high level of hardness.
Referring to
The first conductive layer 130a may be formed of at least one of Ag, Cu, nickel (Ni), and tin (Sn). The first conductive layer 130a may be formed of Cu, but is not limited thereto.
The second conductive layer 130b may include a conductive powder and an organic material, and the conductive powder may include at least one of Ag, Cu, Sn, bismuth (Bi), and alloys thereof.
The conductive powder may include two or more types of powder particles, having different sizes. For example, the conductive powder may include Sn or Bi, having a diameter of 3 μm, or Ag, having a diameter of 1 μm, but is not limited thereto.
The organic material may include at least one of a polymer and a flux. For example, the organic material may include one selected from an epoxy, acrylate, and a phenolic resin, but is not limited thereto.
The via 130 may have various cross-sectional shapes, such as a tetragonal shape, an inverted trapezoidal shape, or a trapezoidal shape, depending on the manufacturing methods used, thereof. For example, the via 130 may have an inverted trapezoidal shape having an upper surface longer than a lower surface, but is not limited thereto.
External electrodes 115a and 115b may be disposed on first and second side surfaces of the body 110.
The external electrodes 115a and 115b may be formed of a material having excellent electrical conductivity. For example, the external electrodes 115a and 115b may be formed of a conductive material such as Ag, Cu, or alloys thereof, but is not limited thereto.
In addition, an electroplating layer may further be formed by electroplating Ni or Sn on surfaces of the external electrodes 115a and 115b.
Hereinafter, a method of fabricating an inductor, according to an exemplary embodiment in the present disclosure, will be described in detail.
The method of fabricating the inductor, according to an exemplary embodiment in the present disclosure, may include forming a coil pattern 320 on a substrate 10, forming an insulating layer 111 to cover the coil pattern 320 on the substrate 10, forming a through-hole 135 in the insulating layer 111, forming a first conductive layer 130a in the through-hole 135, forming a second conductive layer 130b by printing a conductive paste 131 on the first conductive layer 130a, separating the substrate 10 from the insulating layer 111 including the coil pattern 320 and the first and second conductive layers 130a and 130b, and forming a body 110 by stacking a plurality of the insulating layers 111, separated from the substrate 10.
The insulating layer 111 may include at least one of a photosensitive material, an epoxy-based material, an acryl-based material, a polyimide-based material, a phenol-based material, and a sulfone-based material.
When the insulating layer 111 is formed of the photosensitive material, the through-hole 135 may be formed in a photoresist (PR) process, and when the insulating layer 111 is formed of at least one of the group consisting of the epoxy-based material, the acryl-based material, the polyimide-based material, the phenol-based material, and the sulfone-based material, the through-hole 135 may be formed by laser drilling.
The through-hole 135 may have various cross-sectional shapes, such as a tetragonal shape, an inverted trapezoidal shape, or a trapezoidal shape, depending on manufacturing methods thereof. For example, the through-hole 135 may have an inverted trapezoidal shape, but is not limited thereto.
The first conductive layer 130a may be formed by plating, and may be formed of a conductive metal. The conductive metal may include at least one of Ag, Cu, Ni, and Sn. The conductive metal may be Cu, but is not limited thereto.
The second conductive layer 130b may be formed by printing the conductive paste 131, including a conductive powder and an organic material.
The conductive paste 131 may be either a thermosetting type conductive paste or a low-temperature, sintering type conductive paste, sintered at 230° C. or less.
The conductive paste 131 may include the conductive powder and the organic material.
The conductive powder may include at least one of Ag, Cu, Sn, and Bi, and may include two or more types of powder particles having different sizes. For example, the conductive powder may include Sn or Bi having a diameter of 3 μm and Ag having a diameter of 1 μm, but is not limited thereto.
The organic material may include at least one of a polymer and a flux. For example, the organic material may include one selected from an epoxy, acrylate, and a phenolic resin, but is not limited thereto.
Referring to
The substrate 10 may be a copper clad laminate (CCL). The CCL may be a laminate for a printed circuit board (PCB), in which a copper foil is applied on one side or both sides of a base substrate, and the base substrate may be a phenol resin, an epoxy resin, or the like.
The coil pattern 320 may be formed on the CCL by an exposure and development process.
The coil pattern may include Ag, Cu, or alloys thereof. For example, the coil pattern 320 may include Cu, but is not limited thereto.
Referring to
The insulating layer 111 may be a photosensitive resin. When the insulating layer 111 is the photosensitive resin, the through-hole 135 may be formed in a PR process.
The through-hole 135 may pass through the insulating layer 111, to be in contact with the coil pattern 320.
When the insulating layer 111 is a negative-type photoresist, a cross-section of the through-hole 135 may have a trapezoidal shape, and when the insulating layer 111 is a positive-type photoresist, the cross-section of the through-hole 135 may have an inverted trapezoidal shape having a top surface longer than a bottom surface.
Referring to
The first conductive layer 130a may be formed of Cu using an electroplating method, but is not limited thereto.
The first conductive layer 130a may be formed in a portion of the through-hole 135.
Referring to
A via 130 may include the first and second conductive layers 130a and 130b formed in the through-hole 135.
The second conductive layer 130b may be formed by disposing the conductive paste 131 on a metal mask 140, in which a predetermined pattern is formed, and filling the through-hole 135 with the conductive paste 131, using a squeezer 141.
The second conductive layer 130b may include a conductive powder and an organic material.
The conductive powder may include at least one of Ag, Cu, Sn, and Bi, and may include two or more types of powder particles having different sizes.
The organic material may include at least one of a polymer and a flux.
Referring to
The convex portion of the second conductive layer 130b may be formed to a predetermined height above the surface of the insulating layer 111. The height of the convex portion of the second conductive layer 130b may be lowered by 1% to 20% in a subsequent stacking and compressing process, and an internal density of the convex portion may be increased.
The via 130 may include the second conductive layer 130b formed of the conductive paste 131. The convex portion of the second conductive layer 130b formed of the conductive paste 131 may function as a buffer, dissipating interlayer stress during the stacking and compressing process of a plurality of the insulating layers 111.
Referring to
The substrate 10 may be removed in an etching process.
The plurality of separated insulating layers 111 may be stacked in bulk and compressed at a high temperature to form the body 110.
The formation of the body 110 may not include a sintering process performed at a high temperature, but may be performed at a temperature at which the insulating layers 111 and the second conductive layer 130b are cured.
In addition, since the body 110 is formed by stacking the insulating layers 111 in a multilayer, and thermally pressing the stacked insulating layers 111, interlayer insulating distances may be uniform. Accordingly, the resistance of a coil 120 may be lowered, and Q-characteristics of the inductor may be improved.
In general, a sintered metal body is used as a via to connect coil patterns 320 indifferent layers. Since the sintered metal body is a material sintered at a high temperature, in a range from 800° C. to 900° C., an organic material therein may be burnt out during the sintering process. Therefore, the sintered metal body may not include the organic material.
In addition, since the stacking and compressing process is performed before the sintering process, a phenomenon in which the coil pattern 320 and the via 130 are compressed and laterally spread may occur. Accordingly, capacitance of the inductor may be reduced and an interlayer short circuit may occur.
When a curable conductive paste is used to form the via used to connect coil patterns disposed in different levels in a manufacturing process of the inductor, resistance of a coil may be increased, since the curable conductive paste has higher electrical resistance than a sintering-type paste. Accordingly, Q-characteristics of the inductor may be degraded.
In addition, when an electroplating method alone is used to form the via, the via may have a high level of hardness since it is formed only of a metal. Even when a via formed by the electroplating method has a convex portion, interlayer insulating distances may not be uniform, due to the fluidity of the insulating layers, since pressure is weighted to an area, except for the convex portion, during the stacking and compressing process of the insulating layers. In addition, when the convex portion is formed by the electroplating method, it is difficult to form the convex portion to have a uniform size due to variations in electroplating, and interlayer insulating distances may not be uniform, due to differences in height of the convex portion.
The inductor 100, according to the present exemplary embodiment, includes the via 130 including the first and second conductive layers 130a and 130b. More specifically, the via 130 may include the first conductive layer 130a, formed by an electroplating method, and the second conductive layer 130b, formed of the conductive paste 131 and including the organic material. Accordingly, electrical resistance of the coil 120 may be lowered, and thereby Q-characteristics of the inductor 100 may be improved.
A plurality of the vias 130 may be disposed to be spaced apart from each other between the insulating layers 111.
The via 130 may connect the coil patterns 320 arranged up and down in parallel to form the coil 120.
End portions of the coil 120 may be exposed on both side surfaces of the body 110, and electrically connected to an external device by external electrodes formed on both side surfaces of the body 110.
The body 110 may be compressed and cured in a process, such as compressing or vacuum-pressing, to maximize a packing rate of the body 110.
When the body 110 is fabricated to have a bar shape, a plurality of bodies 110 may be fabricated by being cut into chip units. Therefore, manufacturing costs of the inductor 100 may be lowered and high productivity may be ensured.
Among components illustrated in
Referring to
Referring to
The insulating layer 211 may be formed of at least one of an epoxy-based material, an acryl-based material, a polyimide-based material, a phenol-based material, and a sulfone-based material.
The insulating layer 211 may be formed together with a carrier film 213 on the substrate 20.
The carrier film 213 has one adhesive surface so as to be attached on the insulating layer 211. The carrier film 213 may be a polyethylene terephthalate (PET), but is not limited thereto.
When the insulating layer 211 is formed of at least one of the epoxy-based material, the acryl-based material, the polyimide-based material, the phenol-based material, and the sulfone-based material, the through-hole may be formed by laser drilling.
The through-hole may pass through the carrier film 213 and the insulating layer 211 to be in contact with the coil pattern 220.
Referring to
The first conductive layer 230a may be formed by an electroplating method. The first conductive layer 230a may be formed of Cu, but is not limited thereto.
The first conductive layer 230a may be formed in a portion of the through-hole.
Referring to
A via 230 may include the first and second conductive layers 230a and 230b formed in the through-hole.
The second conductive layer 230b may be formed by disposing the conductive paste 231 on the carrier film 213 attached on the insulating layer 211 and filling the through-hole with the conductive paste 231, using a squeezer 241.
Next, the carrier film 213 may be removed.
Referring to
A convex portion of the second conductive layer 230b may be formed to a predetermined height above the surface of the insulating layer 211. The height of the convex portion of the second conductive layer 230b may be lowered by 1% to 20% in a subsequent stacking and compressing process, and thereby an internal density of the convex portion may increase.
The via 230, according to the exemplary embodiment, may include the second conductive layer 230b formed of the conductive paste 231. The convex portion of the second conductive layer 230b may function as a buffer, dissipating interlayer stresses during the stacking and compressing process of a plurality of the insulating layers 211. Accordingly, a uniform distance between the insulating layers 211 may be maintained.
Referring to
The substrate 20 may be removed by an etching process.
The plurality of separated insulating layers 211 may be stacked in bulk and compressed at a high temperature to form the body.
Next, although not shown in the drawings, external electrodes may be formed on both side surfaces of the body 210.
The external electrodes may be formed by dipping the body 210 in a paste for forming an external electrode.
The paste for forming the external electrode may include a conductive powder. The conductive powder may include a material from at least one of Ag or Cu, or alloys thereof, but is not limited thereto.
As set forth above, inductors, according to exemplary embodiments of the present disclosure, may include a coil formed by connecting coil patterns through a via which includes first and second conductive layers. Accordingly, resistance of the coil may be lowered and Q-characteristics of the inductor may be improved.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the invention, as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2016-0003087 | Jan 2016 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5243142 | Ishikawa | Sep 1993 | A |
| 5515022 | Tashiro | May 1996 | A |
| 20060081397 | Enchi | Apr 2006 | A1 |
| 20080231402 | Jow | Sep 2008 | A1 |
| 20130068513 | Hirai | Mar 2013 | A1 |
| 20140097927 | Yamamoto | Apr 2014 | A1 |
| 20150077209 | Fujii | Mar 2015 | A1 |
| 20150092314 | Kim | Apr 2015 | A1 |
| Number | Date | Country |
|---|---|---|
| 03116702 | May 1991 | JP |
| 2001-217550 | Aug 2001 | JP |
| 2007-67427 | Mar 2007 | JP |
| 2007067427 | Mar 2007 | JP |
| 2009152347 | Jul 2009 | JP |
| 2012-15291 | Jan 2012 | JP |
| 2012015291 | Jan 2012 | JP |
| 10-2010-0127936 | Dec 2010 | KR |
| Entry |
|---|
| Notice of Office Action dated Apr. 19, 2017, in corresponding Korean Patent Application No. 10-2016-0003087, with English language translation. |
| Number | Date | Country | |
|---|---|---|---|
| 20170200551 A1 | Jul 2017 | US |
