Patent Application
20150263082
Transceiver circuits are generally designed to transmit and receive high speed signals. To enable high speed transmissions, transceiver circuitry may include a high frequency and low noise voltage-controlled oscillator (VCO) circuit. Although the VCO circuit design is capable of supporting high speed transmissions, it is generally limited to 10 Gigahertz (GHz). One of the reasons for such limitation is because the ring oscillator (RO) circuit, which is a circuit in the VCO circuit, has a poor phase noise performance.
Another type of VCO circuit design is the inductor-capacitor VCO (LC-VCO) circuit. The LC-VCO circuit enables data transmissions at speeds greater than 10 GHz. Furthermore, it generally has low phase noise characteristics. However, the LC tank in the LC-VCO circuit generally includes a low quality factor (i.e., Q factor) inductor. For example, the quality factor for LC tank may be less than 25 at 16 GHz.
An inductor structure may exhibit a low Q factor because of the relatively large eddy current induced on the semiconductor substrate when an electrical current is transmitted through the inductor structure. There are ways to reduce eddy current such as forming a pattern ground shield (PGS) between the substrate and the metal layer where the inductor structure is formed. The PGS structure can help reduce the eddy current formed on the substrate. However, the PGS structure may not be an efficient way to reduce power loss from eddy current. In fact, eddy currents may be generated on the PGS structure instead of the substrate.
Embodiments described herein include a high Q factor inductor structure and a method to manufacture the inductor structure. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method. Several embodiments are described below.
In one embodiment, an inductor structure is provided. The inductor structure includes a first elongated segment and a second elongated segment. The first elongated segment runs parallel to a longitudinal axis of the inductor structure. The second elongated segment also runs parallel to the longitudinal axis. The first elongated segment conveys a current in a first direction and the second elongated segment conveys the current in a second direction that is different than the first direction.
In another embodiment, an integrated circuit is described. The integrated circuit includes a substrate, an interconnect stack and an inductor. The interconnect stack is formed on the substrate. The inductor is formed in the interconnect stack. The inductor includes a first and second elongated member. The first elongated member conveys a current in a first direction. The second elongated member conveys the current in a second direction that is opposite from the first direction.
Alternatively, a method of manufacturing an integrated circuit having a substrate and a dielectric stack on the substrate is described. The method includes forming of a first elongated segment in the dielectric stack. Next, a second elongated segment is formed in the dielectric stack. The first and second elongated segments form a part of an inductor and that the first and second elongated segments convey currents in opposing directions.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
The following embodiments describe a high Q factor inductor structure and a method to manufacture the inductor structure. It will be obvious, to one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.
Throughout this specification, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or electrically connected or coupled to the other element with yet another element interposed between them.
As shown in the embodiment of
LCVCO circuit 100 may be utilized to generate a periodic signal at a specific frequency. As an example, LCVCO circuit 100 may generate a periodic signal with a frequency greater than 10 gigahertz (GHz). In one embodiment, the generated signal may be utilized by circuits in transceiver circuitry, for example, a physical media attachment (PMA) circuit, a physical coding sublayer (PCS) circuit, serializer/deserializer (SerDes) circuitry and/or a phase locked loop (PLL) circuit.
It should be appreciated that an integrated circuit that includes LCVCO circuit 100 may be a programmable logic device (PLD), for example, a field programmable gate array (FPGA) device. Alternatively, the integrated circuit may be an application specific integrated circuit (ASIC) device or application specific standard products (ASSP) device, such as, a memory device or a microprocessor device.
LCVCO circuit 100 may also be tuned to generate periodic signals at different operating frequencies. As shown in the embodiment of
Additionally, LCVCO circuit 100 may also have a low phase noise characteristic. The low phase noise characteristic may help to generate a low jitter high frequency periodic signal, which may increase the sensitivity of the transceiver circuitry to detect an incoming high speed data.
Furthermore, LC tank 180 formed in LCVCO circuit 100 has a high Q factor. It should be appreciated that a Q factor is a dimensionless parameter that describes under-damp characteristics of LC tank 180. For example, a high Q factor suggests the amount energy that is lost from the LC tank 180 is lower than the amount of energy that is stored in LC tank 180. In one embodiment, inductor 150 within LC tank 180 may have a Q factor that is greater than 8.
It should be noted that the cross section shown in the embodiment of
As shown in the embodiment of
Integrated circuit 200 may further include a metal shielding (not shown) just above inductor structure 227. The metal shielding may shield inductor structure 227 from crosstalk. In one embodiment, the metal shielding may shield crosstalk generated by transistors 220 and 225 from segments 232 and 231, respectively, of inductor structure 227.
Segments 231 and 232 transmit an electrical in opposite directions. In one embodiment, transmitting electrical current in opposite directions between the respective segments 231 and 232 may reduce the total amount of induced eddy current on the surface of semiconductor substrate 210. Therefore, inductor structure 227 may have a high Q factor and relatively low phase noise. In one exemplary embodiment, inductor structure 227 may have a Q factor of 11 and a phase noise improvement of approximately 0.4 decibels relative to carrier (dBc). Furthermore, the Q factor may also be relatively high (e.g., Q factor of 8) at significantly high frequencies (e.g., frequency of 50 GHz).
It should be appreciated that eddy current is generated when magnetic fields (from the electrical current transmitting through segments 231 and 232 of inductor structure 227) induce electric current on semiconductor substrate 210. The amount of induced eddy current may depend on three factors: (i) the resistivity of semiconductor substrate 210, (ii) the distance between segments 231 and 232, and (iii) the distance between inductor 227 and semiconductor substrate 210.
For example, a low resistivity semiconductor substrate 210 (e.g., substrate resistivity lower than 10 Ohms per cm) may induce a high amount of eddy current. In contrast, a high resistivity semiconductor substrate 210 may induce a lower amount of eddy current. However, semiconductor substrate 210 with a low resistivity may be preferred for optimized transistor performance. Low resistivity semiconductor substrate 210 may be utilized to form a transistor ground plane that makes latch-up less likely. In the embodiment of
Additionally, segments 231 and 232 transmitting electrical current in opposite directions may not induce as much eddy current when the distance between segments 231 and 232 is relatively small. The reduction in eddy current may be due to the fact that the magnetic fields generated by segments 231 and 232 may partially cancel out each other. A person skilled in the art appreciates the right-hand rule (or corkscrew-rule) with respect to the electric current and the magnetic field. In one embodiment, the distance to achieve the eddy current cancellation effect is less than 15 microns (μm).
It should be appreciated that the Q factor value inversely related to the amount of induced eddy current on the surface of semiconductor substrate 210. When a large amount of eddy current is induced, a large amount of energy may be lost that leading to a low Q factor value. In contrast, when a small amount of eddy current is induced, a small amount of energy may be lost that leads to a high Q factor value. The embodiment of
As shown in the embodiment of
A signal may be received by inductor structure 400 through terminal IN1 and is transmitted out from inductor structure 400 through terminal OUT1. The electrical current I1 propagates according to the direction shown by the arrows in
Referring still to
In one exemplary embodiment, inductor structure 400 that has an inductance valued at a 0.2 nanohenry (nH) may have segments 413 and 415 at a length of 24 μm and segments 414 and segments 411 and 412 (taken together) at a length of 300 μm. In total, inductor structure 400 may encompass an area of 7200 μm2. Inductor structure 400 may also have a maximum Q factor of 11.6 at 25 Ghz.
Signals may be transmitted into inductor structure 500 through terminal IN2 and transmitted out through terminal OUT2.
Segments 511 and 512 form a large part of inductor structure 500. Segment 511 is parallel to segment 512. The distance (Y) between the two segments, i.e., segments 511 and 512, may be less than 15 μm. Electrical current I2 travels in opposite directions through the respective segments 511 and 512. Therefore, similar to inductor structure 400 of
For inductor structure 500 that has an inductance valued at 0.2 nH, segments 511 and 512 may have a length of 285 μm and segment 513 may have a length of 26 μm. Therefore, inductor structure 500 may encompass an area of 7410 μm2, (which is larger than 0.2 nH inductor structure 400 of
It should be appreciated that inductor structure 500 may be preferred over inductor structure 400 of
Electrical current I3 is transmitted into inductor structure 600 through terminal IN3 and is transmitted out of inductor structure 600 through terminal OUT3. As shown in the embodiment of
For inductor structure 600 formed to have an inductance that is valued at 0.2 nH, segments 611-614 may have a length of 142 μm and segments 615 and 616 may have a length of 26 μm, respectively. Therefore, inductor structure 600 may encompass an area of 7384 μm2, (which is relatively similar in size to 0.2 nH inductor structure 500 of
It should be appreciated that there may be more than two-turn U-shaped inductor structure unlike two-turn U-shaped inductor structure 600 as shown in
Electrical current I4 may be transmitted into inductor structure 700 through terminal IN4 and may be transmitted out through terminal OUT4. In the embodiment of
Therefore, inductor structure 700 may induce a low eddy current and a high Q factor across a large bandwidth.
For inductor structure 700 formed for an inductance that is valued at 0.2 nH, segments 711 and 712 or collectively segment 713 and 714 may have a length of 371 μm and segments 715 and 716 may have a length of 56 μm, respectively. Therefore, inductor structure 700 may encompass an area of 20776 μm2, (which is significantly larger compared to 0.2 nH inductor structure 400, 500 or 600 of respective
It should be appreciated that inductor structures 400, 500, 600 or 700 of respective
Inductor structures 400, 500, 600 or 700 of respective
At step 830, a second elongated segment is formed in the dielectric stack. The second elongated segment also forms a part of the inductor structure. The second elongated segment is in close proximity to the first elongated segment (e.g., at a distance less than 15 μm). The second elongated segment may transfer electrical current in an opposite direction compared to the first elongated segment. In one embodiment, the second elongated segment may be inductor segment 232 of
The method may also include other steps, for example, forming of additional segments to manufacture an inductor structure similar to inductor structure 400, 500, 600 or 700 of respective
The embodiments thus far have been described with respect to integrated circuits. The structures and techniques described herein may be incorporated into other suitable circuits, in addition to the ones described above. For example, they may be incorporated into numerous types of devices such as programmable logic devices, application specific standard products (ASSPs), and application specific integrated circuits (ASICs). Examples of programmable logic devices include programmable arrays logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPGAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), just to name a few.
The programmable logic device described in one or more embodiments herein may be part of a data processing system that includes one or more of the following components: a processor; memory; IO circuitry; and peripheral devices. The data processing can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable logic device can be used to perform a variety of different logic functions. For example, the programmable logic device can be configured as a processor or controller that works in cooperation with a system processor. The programmable logic device may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable logic device may be one of the family of devices owned by ALTERA Corporation.
Although the methods of operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.
Although the foregoing invention has been described in some detail for the purposes of clarity, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
