Patent Application
20200185138
The technical field relates to an inductor structure with a large wire width and low occupied area.
With current planar inductors, the higher the required inductance value, the more inductive turns of the component, and therefore the larger the area it occupies on a wafer. In order to prevent interference between the inductor components and other components, the region below the inductor component is set as a component-free area, i.e. no components or metal layers are disposed therein. Also, within a certain distance from the inductor component, it must be a component-free area. The above limitations cause the wafer to have a very poor use of space.
Current planar inductors use a single metal layer, and the underlying metal layer acts as a connection wire to allow it to connect to other components. Limited by the processing factors, it must be designed to meet the requirements of minimum metal spacing, and a wider metal wire with more inductive turns is required in order to increase the inductance value. However, due to those processing and design requirements, there are always insurmountable difficulties in the use of the area of the wafer.
Therefore, development of an inductor structure with a large wire width and low occupied area is desirable.
In accordance with one embodiment of the invention, an inductor structure is provided. The inductor structure includes a substrate, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, at least one intermediate dielectric layer, at least one intermediate metal layer, and a plurality of vias. The first dielectric layer is formed on the substrate. The first metal layer is formed in the first dielectric layer. The second dielectric layer is formed on the first dielectric layer. The second metal layer is formed in the second dielectric layer. The first and second metal layers are continuous metal layers. The intermediate dielectric layer is formed between the first and second dielectric layers. The intermediate metal layer is formed in the intermediate dielectric layer. The intermediate metal layer is a patterned metal layer. The vias are connected to the first metal layer and the intermediate metal layer and connected to the second metal layer and the intermediate metal layer. The first metal layer, the via, the intermediate metal layer, the via, the second metal layer, the via, and the intermediate metal layer form an extension path which extends in a counterclockwise spiral mode. The starting point of the extension path is the first metal layer.
In some embodiments, the length of the first metal layer, the second metal layer and the intermediate metal layer is in a range from about 1 μm to about 100 μm. In some embodiments, the thickness of the first metal layer, the second metal layer and the intermediate metal layer is in a range from about 0.01 μm to about 4 μm. In some embodiments, the width of the first metal layer, the second metal layer and the intermediate metal layer is in a range from about 0.01 μm to about 100 μm. In some embodiments, the spacing of the patterned metal layer of the intermediate metal layer is in a range from about 0.01 μm to about 10 μm.
In some embodiments, the intermediate dielectric layer includes a single-layer intermediate dielectric layer, and the intermediate metal layer includes a single-layer intermediate metal layer. In some embodiments, the intermediate dielectric layer includes dual-layer intermediate dielectric layers, and the intermediate metal layer includes dual-layer intermediate metal layers. In some embodiments, when the intermediate metal layer includes dual-layer intermediate metal layers, the inductor structure further includes a plurality of vias connected to the intermediate metal layers which are located at different layers. In some embodiments, the intermediate dielectric layer includes triple-layer intermediate dielectric layers, and the intermediate metal layer includes triple-layer intermediate metal layers. In some embodiments, when the intermediate metal layer includes triple-layer intermediate metal layers, the inductor structure further includes a plurality of vias connected to the intermediate metal layers which are located at different layers.
In accordance with one embodiment of the invention, an inductor structure is provided. The inductor structure includes a substrate, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, at least one intermediate dielectric layer, at least one intermediate metal layer, and a plurality of vias. The first dielectric layer is formed on the substrate. The first metal layer is formed in the first dielectric layer. The second dielectric layer is formed on the first dielectric layer. The second metal layer is formed in the second dielectric layer. The first and second metal layers are continuous metal layers. The intermediate dielectric layer is formed between the first and second dielectric layers. The intermediate metal layer is formed in the intermediate dielectric layer. The intermediate metal layer is a patterned metal layer. The vias are connected to the first metal layer and the intermediate metal layer and connected to the second metal layer and the intermediate metal layer. The first metal layer, the via, the intermediate metal layer, the via, the second metal layer, the via, and the intermediate metal layer form an extension path which extends in a clockwise spiral mode. The starting point of the extension path is the first metal layer.
The present invention provides a specific connection manner to connect metal layers and vias along a vertical direction to fabricate an inductor component. To increase the number of inductive turns of the inductor component, it is only necessary to increase the number of layers of the metal layer along the vertical direction. That is, the increase in the number of inductive turns of the inductor component does not cause an increase in the area occupied on the plane (i.e. along the horizontal direction). Also, the fabrication process of the present invention is not difficult, and it can be combined with general semiconductor processes to fabricate the component easily. In addition, the present invention does possess a considerable process window when various wire widths of metal wires are designed to be fabricated. That is, there is no need to worry that arbitrarily increasing the wire width of the metal wires will cause a loading of the area occupied by the component, so an inductor component having any appropriate wire width can be easily fabricated. Furthermore, due to the reduced area occupied on the plane (i.e. along the horizontal direction), the effects of the inductor component of the present invention on adjacent component regions are substantially reduced, particularly the restrictions on the area used by adjacent components. That is, the present invention provides more convenient options for the placement of various other components.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
Referring to
As shown in
In addition, the vias (26 and 28) are connected to the first metal layer 16 and the intermediate metal layer 24 and connected to the second metal layer 20 and the intermediate metal layer 24. For example, the via 26 is connected to the first metal layer 16 and the intermediate metal layer 24. The via 28 is connected to the second metal layer 20 and the intermediate metal layer 24. Specifically, the first metal layer 16, the via 26, the intermediate metal layer 24, the via 28, the second metal layer 20, the via 28 and the intermediate metal layer 24 form an extension path 32 which extends in a counterclockwise spiral mode. The extension path 32 takes the starting point 34 of the first metal layer 16 as an extension starting point, as shown in
In some embodiments, the substrate 12 includes a silicon substrate or other suitable substrate materials. In some embodiments, the first dielectric layer 14, the second dielectric layer 18 and the intermediate dielectric layer 22 include silicon nitride, silicon oxide, silicon oxynitride or other suitable low-dielectric-constant dielectric materials. In some embodiments, the first metal layer 16, the second metal layer 20 and the intermediate metal layer 24 include copper, aluminum or other suitable metal conductive materials. In some embodiments, the vias (26 and 28) are filled with copper, tungsten or other suitable metal conductive materials.
In some embodiments, the length “L” of the first metal layer 16, the second metal layer 20 and the intermediate metal layer 24 is in a range from about 1 μm to about 100 μm. In some embodiments, the thickness “T” of the first metal layer 16, the second metal layer 20 and the intermediate metal layer 24 is in a range from about 0.01 μm to about 4 μm. In some embodiments, the width “W” of the first metal layer 16, the second metal layer 20 and the intermediate metal layer 24 is in a range from about 0.01 μm to about 100 μm, as shown in
Referring to
As shown in
The vias (260, 280 and 300) are connected to the first metal layer 160 and the first intermediate metal layer 240, connected to the first intermediate metal layer 240 and the second intermediate metal layer 250, and connected to the second metal layer 200 and the second intermediate metal layer 250. For example, the via 260 is connected to the first metal layer 160 and the first intermediate metal layer 240. The via 280 is connected to the first intermediate metal layer 240 and the second intermediate metal layer 250. The via 300 is connected to the second metal layer 200 and the second intermediate metal layer 250. Specifically, the first metal layer 160, the via 260, the first intermediate metal layer 240, the via 280, the second intermediate metal layer 250, the via 300, the second metal layer 200, the via 300, the second intermediate metal layer 250, the via 280, the first intermediate metal layer 240, the via 280, and the second intermediate metal layer 250 form an extension path 320 which extends in a counterclockwise spiral mode. The extension path 320 takes the starting point 340 of the first metal layer 160 as an extension starting point, as shown in
In some embodiments, the substrate 120 includes a silicon substrate or other suitable substrate materials. In some embodiments, the first dielectric layer 140, the second dielectric layer 180, the first intermediate dielectric layer 220 and the second intermediate dielectric layer 230 include silicon nitride, silicon oxide, silicon oxynitride or other suitable low-dielectric-constant dielectric materials. In some embodiments, the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240 and the second intermediate metal layer 250 include copper, aluminum or other suitable metal conductive materials. In some embodiments, the vias (260, 280 and 300) are filled with copper, tungsten or other suitable metal conductive materials.
In some embodiments, the length “L” of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240 and the second intermediate metal layer 250 is in a range from about 1 μm to about 100 μm. In some embodiments, the thickness “T” of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240 and the second intermediate metal layer 250 is in a range from about 0.01 μm to about 4 μm. In some embodiments, the width “W” of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240 and the second intermediate metal layer 250 is in a range from about 0.01 μm to about 100 μm, as shown in
Referring to
As shown in
The vias (2600, 2800, 3000 and 3100) are connected to the first metal layer 1600 and the first intermediate metal layer 2400, connected to the first intermediate metal layer 2400 and the second intermediate metal layer 2500, connected to the second intermediate metal layer 2500 and the third intermediate metal layer 2550, and connected to the second metal layer 2000 and the third intermediate metal layer 2550. For example, the via 2600 is connected to the first metal layer 1600 and the first intermediate metal layer 2400. The via 2800 is connected to the first intermediate metal layer 2400 and the second intermediate metal layer 2500. The via 3000 is connected to the second intermediate metal layer 2500 and the third intermediate metal layer 2550. The via 3100 is connected to the second metal layer 2000 and the third intermediate metal layer 2550. Specifically, the first metal layer 1600, the via 2600, the first intermediate metal layer 2400, the via 2800, the second intermediate metal layer 2500, the via 3000, the third intermediate metal layer 2550, the via 3100, the second metal layer 2000, the via 3100, the third intermediate metal layer 2550, the via 3000, the second intermediate metal layer 2500, the via 2800, the first intermediate metal layer 2400, the via 2800, the second intermediate metal layer 2500, the via 3000, the third intermediate metal layer 2550, the via 3000, and the second intermediate metal layer 2500 form an extension path 3200 which extends in a counterclockwise spiral mode. Similarly, the extension path 3200 takes the starting point 3400 of the first metal layer 1600 as an extension starting point, as shown in
In some embodiments, the substrate 1200 includes a silicon substrate or other suitable substrate materials. In some embodiments, the first dielectric layer 1400, the second dielectric layer 1800, the first intermediate dielectric layer 2200, the second intermediate dielectric layer 2300 and the third intermediate dielectric layer 2350 include silicon nitride, silicon oxide, silicon oxynitride or other suitable low-dielectric-constant dielectric materials. In some embodiments, the first metal layer 1600, the second metal layer 2000, the first intermediate metal layer 2400, the second intermediate metal layer 2500 and the third intermediate metal layer 2550 include copper, aluminum or other suitable metal conductive materials. In some embodiments, the vias (2600, 2800, 3000 and 3100) are filled with, for example, copper, tungsten or other suitable metal conductive materials.
In some embodiments, the length “L” of the first metal layer 1600, the second metal layer 2000, the first intermediate metal layer 2400, the second intermediate metal layer 2500 and the third intermediate metal layer 2550 is in a range from about 1 μm to about 100 μm. In some embodiments, the thickness “T” of the first metal layer 1600, the second metal layer 2000, the first intermediate metal layer 2400, the second intermediate metal layer 2500 and the third intermediate metal layer 2550 is in a range from about 0.01 μm to about 4 μm. In some embodiments, the width “W” of the first metal layer 1600, the second metal layer 2000, the first intermediate metal layer 2400, the second intermediate metal layer 2500 and the third intermediate metal layer 2550 is in a range from about 0.01 μm to about 100 μm, as shown in
Referring to
As shown in
In addition, the vias (26 and 28) are connected to the first metal layer 16 and the intermediate metal layer 24 and connected to the second metal layer 20 and the intermediate metal layer 24. For example, the via 26 is connected to the first metal layer 16 and the intermediate metal layer 24. The via 28 is connected to the second metal layer 20 and the intermediate metal layer 24. Specifically, the first metal layer 16, the via 26, the intermediate metal layer 24, the via 28, the second metal layer 20, the via 28 and the intermediate metal layer 24 form an extension path 32 which extends in a clockwise spiral mode. The extension path 32 takes the starting point 34 of the first metal layer 16 as an extension starting point, as shown in
In some embodiments, the substrate 12 includes a silicon substrate or other suitable substrate materials. In some embodiments, the first dielectric layer 14, the second dielectric layer 18 and the intermediate dielectric layer 22 include silicon nitride, silicon oxide, silicon oxynitride or other suitable low-dielectric-constant dielectric materials. In some embodiments, the first metal layer 16, the second metal layer 20 and the intermediate metal layer 24 include copper, aluminum or other suitable metal conductive materials. In some embodiments, the vias (26 and 28) are filled with copper, tungsten or other suitable metal conductive materials.
In some embodiments, the length “L” of the first metal layer 16, the second metal layer 20 and the intermediate metal layer 24 is in a range from about 1 μm to about 100 μm. In some embodiments, the thickness “T” of the first metal layer 16, the second metal layer 20 and the intermediate metal layer 24 is in a range from about 0.01 μm to about 4 μm. In some embodiments, the width “W” of the first metal layer 16, the second metal layer 20 and the intermediate metal layer 24 is in a range from about 0.01 μm to about 100 μm, as shown in
Referring to
As shown in
The vias (260, 280 and 300) are connected to the first metal layer 160 and the first intermediate metal layer 240, connected to the first intermediate metal layer 240 and the second intermediate metal layer 250, and connected to the second metal layer 200 and the second intermediate metal layer 250. For example, the via 260 is connected to the first metal layer 160 and the first intermediate metal layer 240. The via 280 is connected to the first intermediate metal layer 240 and the second intermediate metal layer 250. The via 300 is connected to the second metal layer 200 and the second intermediate metal layer 250. Specifically, the first metal layer 160, the via 260, the first intermediate metal layer 240, the via 280, the second intermediate metal layer 250, the via 300, the second metal layer 200, the via 300, the second intermediate metal layer 250, the via 280, the first intermediate metal layer 240, the via 280, and the second intermediate metal layer 250 form an extension path 320 which extends in a clockwise spiral mode. The extension path 320 takes the starting point 340 of the first metal layer 160 as an extension starting point, as shown in
In some embodiments, the substrate 120 includes a silicon substrate or other suitable substrate materials. In some embodiments, the first dielectric layer 140, the second dielectric layer 180, the first intermediate dielectric layer 220 and the second intermediate dielectric layer 230 include silicon nitride, silicon oxide, silicon oxynitride or other suitable low-dielectric-constant dielectric materials. In some embodiments, the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240 and the second intermediate metal layer 250 include copper, aluminum or other suitable metal conductive materials. In some embodiments, the vias (260, 280 and 300) are filled with copper, tungsten or other suitable metal conductive materials.
In some embodiments, the length “L” of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240 and the second intermediate metal layer 250 is in a range from about 1 μm to about 100 μm. In some embodiments, the thickness “T” of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240 and the second intermediate metal layer 250 is in a range from about 0.01 μm to about 4 μm. In some embodiments, the width “W” of the first metal layer 160, the second metal layer 200, the first intermediate metal layer 240 and the second intermediate metal layer 250 is in a range from about 0.01 μm to about 100 μm, as shown in
Referring to
As shown in
The vias (2600, 2800, 3000 and 3100) are connected to the first metal layer 1600 and the first intermediate metal layer 2400, connected to the first intermediate metal layer 2400 and the second intermediate metal layer 2500, connected to the second intermediate metal layer 2500 and the third intermediate metal layer 2550, and connected to the second metal layer 2000 and the third intermediate metal layer 2550. For example, the via 2600 is connected to the first metal layer 1600 and the first intermediate metal layer 2400. The via 2800 is connected to the first intermediate metal layer 2400 and the second intermediate metal layer 2500. The via 3000 is connected to the second intermediate metal layer 2500 and the third intermediate metal layer 2550. The via 3100 is connected to the second metal layer 2000 and the third intermediate metal layer 2550. Specifically, the first metal layer 1600, the via 2600, the first intermediate metal layer 2400, the via 2800, the second intermediate metal layer 2500, the via 3000, the third intermediate metal layer 2550, the via 3100, the second metal layer 2000, the via 3100, the third intermediate metal layer 2550, the via 3000, the second intermediate metal layer 2500, the via 2800, the first intermediate metal layer 2400, the via 2800, the second intermediate metal layer 2500, the via 3000, the third intermediate metal layer 2550, the via 3000, and the second intermediate metal layer 2500 form an extension path 3200 which extends in a clockwise spiral mode. Similarly, the extension path 3200 takes the starting point 3400 of the first metal layer 1600 as an extension starting point, as shown in the cross-sectional view of
In some embodiments, the substrate 1200 includes a silicon substrate or other suitable substrate materials. In some embodiments, the first dielectric layer 1400, the second dielectric layer 1800, the first intermediate dielectric layer 2200, the second intermediate dielectric layer 2300 and the third intermediate dielectric layer 2350 include silicon nitride, silicon oxide, silicon oxynitride or other suitable low-dielectric-constant dielectric materials. In some embodiments, the first metal layer 1600, the second metal layer 2000, the first intermediate metal layer 2400, the second intermediate metal layer 2500 and the third intermediate metal layer 2550 include copper, aluminum or other suitable metal conductive materials. In some embodiments, the vias (2600, 2800, 3000 and 3100) are filled with, for example, copper, tungsten or other suitable metal conductive materials.
In some embodiments, the length “L” of the first metal layer 1600, the second metal layer 2000, the first intermediate metal layer 2400, the second intermediate metal layer 2500 and the third intermediate metal layer 2550 is in a range from about 1 μm to about 100 μm. In some embodiments, the thickness “T” of the first metal layer 1600, the second metal layer 2000, the first intermediate metal layer 2400, the second intermediate metal layer 2500 and the third intermediate metal layer 2550 is in a range from about 0.01 μm to about 4 μm. In some embodiments, the width “W” of the first metal layer 1600, the second metal layer 2000, the first intermediate metal layer 2400, the second intermediate metal layer 2500 and the third intermediate metal layer 2550 is in a range from about 0.01 μm to about 100 μm, as shown in
The present invention provides a specific connection manner to connect metal layers and vias along a vertical direction to fabricate an inductor component. To increase the number of inductive turns of the inductor component, it is only necessary to increase the number of layers of the metal layer along the vertical direction. That is, the increase in the number of inductive turns of the inductor component does not cause an increase in the area occupied on the plane (i.e. along the horizontal direction). Also, the fabrication process of the present invention is not difficult, and it can be combined with general semiconductor processes to fabricate the component easily. In addition, the present invention does possess a considerable process window when various wire widths of metal wires are designed to be fabricated. That is, there is no need to worry that arbitrarily increasing the wire width of the metal wires will cause a loading of the area occupied by the component, so an inductor component having any appropriate wire width can be easily fabricated. Furthermore, due to the reduced area occupied on the plane (i.e. along the horizontal direction), the effects of the inductor component of the present invention on adjacent component regions are substantially reduced, particularly the restrictions on the area used by adjacent components. That is, the present invention provides more convenient options for the placement of various other components.
While the invention has been described by way of example and in terms of preferred embodiment, it should be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
