Claims
- 1. An information processing system in which computational processing is performed on input data in accordance with a processing sequence, for outputting data, said information processing system comprising:
a plurality of arithmetic units, each computing to an arithmetic precision of 2m bits (where m is a natural number), based on said processing sequence; and a plurality of cascade connection terminals for cascading said arithmetic units each other, wherein, when the maximum arithmetic precision that is required during computational processing is 2n bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) said arithmetic units are cascaded in a manner such that the inequality x≧2n/2m is satisfied.
- 2. The information processing system as defined in claim 1, wherein,
when an arithmetic precision of 2n1 bits (where n1≦n, and n1 is variable) is required during computational processing, x1 numbers of said arithmetic units are cascaded in a manner such that the inequality x1≧2n1/2m (where x1 is a natural number and is variable) is satisfied.
- 3. The information processing system as defined in claim 2, further comprising:
a clock generation circuit for generating a reference clock signal to be input to said plurality of arithmetic units, wherein said clock generation circuit generates 2n1 numbers of reference clock pulses during computational processing.
- 4. The information processing system as defined in any one of claims 1 to 3,
wherein optical signals are transmitted between said plurality of arithmetic units.
- 5. The information processing system as defined in any one of claims 1 to 3,
wherein each of said plurality of arithmetic units comprises y numbers of arithmetic modules (where y is a natural number and is fixed), each computing at an arithmetic precision of 2m/y when y numbers of said arithmetic modules are cascaded.
- 6. The information processing system as defined in claim 1, wherein:
at least one of said plurality of arithmetic units comprises y numbers of arithmetic modules (where y is a natural number and is fixed), each capable of computing at an arithmetic precision of 2m/y; and when an arithmetic precision of 2n1 bits (where n1≦n, and n1 is variable) is required during computational processing, said y numbers of arithmetic modules are cascaded in a manner such that the inequality y1≧2n1/2m/y (where y1 is a natural number and is variable) is satisfied.
- 7. The information processing system as defined in claim 1, wherein:
computations are executed by (x1−1) numbers of cascaded arithmetic units at an arithmetic precision of 2n2 (where n2<n1) for performing computations at a 2n1-bit precision; and y1 numbers of arithmetic modules in one other arithmetic unit, which is cascaded from said (x1−1) numbers of arithmetic units, are cascaded in a manner such that the inequality y1≧(2n1−2n2)/2m/y (where y1≦y, and y1 is variable) is satisfied.
- 8. The information processing system as defined in claim 6 or 7, further comprising:
a clock generation circuit for generating a reference clock signal to be input to said arithmetic units, wherein said clock generation circuit generates 2n1 numbers of reference clock pulses during computational processing.
- 9. The information processing system as defined in any one of claims 5 to 8,
wherein optical signals are transmitted between said y numbers of arithmetic modules.
- 10. The information processing system as defined in any one of claims 1 to 9, further comprising:
a first storage section for storing said processing sequence.
- 11. The information processing system as defined in claim 10, further comprising:
computation control means for controlling said plurality of arithmetic units based on said processing sequence.
- 12. The information processing system as defined in claim 11,
wherein optical signals are transmitted between said plurality of arithmetic units and said computation control means.
- 13. The information processing system as defined in any one of claims 1 to 11, further comprising:
a second storage section for temporarily storing an arithmetic result produced by said plurality of arithmetic units, wherein optical signals are transmitted between said second storage section and said plurality of arithmetic units.
- 14. The information processing system as defined in any one of claims 1 to 13,
wherein, when said input data is X and N and output data is Y, at least one of said arithmetic units executes computational processing to compute: Y=X2 mod N.
- 15. The information processing system as defined in any one of claims 1 to 14,
wherein, when the yield of said plurality of arithmetic units is A and the total number of arithmetic units that are available is K, a maximum number x (where x≧K/A) of said arithmetic units that are operative are cascaded.
- 16. The information processing system as defined in any one of claims 5 to 7,
wherein, when the yield of said arithmetic modules is A′ and the total number of arithmetic modules provided in each of said plurality of arithmetic units is L, a maximum number y (where y≧L/A′) of said arithmetic modules that are operative are cascaded.
- 17. An information processing system in which computational processing is performed on input data in accordance with a processing sequence, for outputting data, said information processing system comprising:
a plurality of internal arithmetic units, each computing to an arithmetic precision of 2m1 bits (where m1 is a natural number and is fixed), based on said processing sequence; a plurality of external arithmetic units for computing to an arithmetic precision of 2m2 bits (where m2 is a natural number and is fixed); and cascade connection terminals for cascading said plurality of internal arithmetic units and said plurality of external arithmetic units, wherein, when the maximum arithmetic precision required during computational processing is 2n bits (where n is a natural number and is variable), z numbers of said external arithmetic units are cascaded in a manner such that the inequality z≧(2n−2m1)/2m2 (where z is a natural number and is fixed) is satisfied.
- 18. The information processing system as defined in claim 17, wherein,
when an arithmetic precision of 2n1 bits (where n1≦n, and n1 is variable) is required during computational processing, z1 numbers of said external arithmetic units are cascaded in a manner such that the inequality z1≧(2n1−2m1)/2m (where z1 is a natural number and is variable) is satisfied.
- 19. The information processing system as defined in claim 17 or i8,
wherein optical signals are transmitted between said plurality of internal arithmetic units and said plurality of external arithmetic units.
- 20. The information processing system as defined in any one of claims 17 to 19,
wherein each of said plurality of external arithmetic units comprises y numbers of (where y is a natural number and is fixed) arithmetic modules performing operations at an arithmetic precision of 2m2/y when said y numbers of arithmetic modules are cascaded.
- 21. The information processing system as defined in claim 20,
wherein optical signals are transmitted between said y numbers of arithmetic modules.
- 22. The information processing system as defined in any one of claims 17 to 21, further comprising:
a storage section for storing said processing sequence.
- 23. The information processing system as defined in claim 22, further comprising:
computation control means for controlling said plurality of internal arithmetic units and said plurality of external arithmetic units based on said processing sequence.
- 24. The information processing system as defined in any one of claims 17 to 23, wherein,
when said input data is X and N and output data is Y, said plurality of internal arithmetic units and said plurality of external arithmetic units execute computational processing to compute: Y=X2 mod N.
- 25. The information processing system as defined in any one of claims 17 to 24,
wherein, when the yield of said plurality of external arithmetic units is A and the total number of external arithmetic units is K, a maximum number z (where z≧K/A) of said arithmetic units that are operative are cascaded.
- 26. The information processing system as defined in claim 20 or 21, wherein,
when the yield of said arithmetic modules is A′ and the total number of arithmetic modules provided in each of said plurality of internal arithmetic units and at least one of said external arithmetic units is L, a maximum number y (where y≧L/A′) of said arithmetic modules that are operative are cascaded.
- 27. An encryption/decryption system comprising:
a plurality of power residue arithmetic units; and a plurality of cascade connection terminals for cascading said plurality of power residue arithmetic units, wherein each of said plurality of power residue arithmetic units comprises:
a multiplication unit for performing a multiplication at a multiplication precision of 2m bits (where m is a natural number and is fixed); and a division unit for performing a division at a division precision of 22×m bits, wherein, when the maximum arithmetic precision of a power residue computation executed by said plurality of power residue arithmetic units is 2n (where n is a natural number and is fixed), x numbers of said plurality of power residue arithmetic units are connected together for encryption and decryption, in a manner such that the following inequality is satisfied: x≧2n/2m (where x is a natural number and is fixed).
- 28. The information processing system as defined in claim 27,
wherein, when an arithmetic precision of 2n1 bits (where n1≦n, and n1 is variable) is required during computational processing, x1 numbers of said plurality of power residue arithmetic units are cascaded in a manner such that the inequality x1≧2n1/2m (where x1≦x and is variable) is satisfied.
- 29. The encryption/decryption system as defined in claim 27 or 28,
wherein optical signals are transmitted between said plurality of power residue arithmetic units.
- 30. The encryption/decryption system as defined in any one of claims 27 to 29, wherein:
said multiplication unit comprises:
y numbers of multiplication modules for performing multiplications at a multiplication precision of 2m/y (where y is a natural number and is fixed); and cascade connection terminals for connecting said y numbers of multiplication modules; and said division unit comprises:
y numbers of division modules for performing divisions at a division precision of 22×(m/y); and cascade connection terminals for connecting said y numbers of division modules.
- 31. The encryption/decryption system as defined in claim 30,
wherein optical signals are transmitted between said y numbers of multiplication modules and between said y numbers of multiplication modules.
- 32. An encryption/decryption system comprising:
a plurality of internal power residue arithmetic units for performing power residue computation at a multiplication precision of 2m1 bits (where m1 is a natural number and is fixed) and a division precision of 22×m1 bits; a plurality of external power residue arithmetic units for performing power residue computation at a multiplication precision of 2m2 bits (where m2 is a natural number and is fixed) and a division precision of 22×m2 bits; and cascade connection terminals for cascading said pluralities of internal and external power residue arithmetic units, wherein, when encryption and decryption is performed at a maximum bit precision of 2n (where n is a natural number and is fixed), z numbers of said external power residue arithmetic units are cascaded in a manner such that the following inequality is satisfied: z≧(2n−2m1)/2m2 (where z is a natural number and is fixed).
- 33. The encryption/decryption system as defined in claim 32,
wherein, when an arithmetic precision of 2n1 bits (where n1≦n, and ni is variable) is required during computational processing, z1 numbers of external power residue arithmetic units are cascaded in a manner such that the inequality z1≧(2n−2m1)/2m2 (where z1≦z and is variable) is satisfied.
- 34. The encryption/decryption system as defined in claim 32 or 33,
wherein optical signals are transmitted between said plurality of internal power residue arithmetic units and said plurality of external power residue arithmetic units.
- 35. The encryption/decryption system as defined in any one of claims 32 to 34,
wherein each of said plurality of external power residue arithmetic units comprises y numbers of external power residue arithmetic modules for performing power residue computations at a multiplication precision of 2m/y (where y is a natural number and is fixed) and a division precision of 22×(m/y) when said y numbers of external power residue arithmetic modules are cascaded.
- 36. The encryption/decryption system as defined in claim 35,
wherein optical signals are transmitted between said y numbers of external power residue multiplication modules.
- 37. The encryption/decryption system as defined in any one of claims 32 to 36, wherein,
when the yield of said plurality of external power residue arithmetic units is A and the total number of arithmetic units that are available is K, a maximum number z (where z≧K/A) of said arithmetic units that are operative are cascaded.
- 38. The encryption/decryption system as defined in claim 35,
wherein, when the yield of said external power residue arithmetic modules is A′ and the total number of external power residue arithmetic modules provided for each of said plurality of external power residue arithmetic units is L, a maximum number y (where y≧L/A′) of said arithmetic modules that are operative are cascaded.
- 39. An information processing system comprising a plurality of functional units, each operating based on multi-channel electrical signals, and a bus line for transmitting signals therebetween, wherein:
each of said plurality of functional units comprises a signal output section and/or a signal input section; said signal output section comprises electrical-optical signal conversion circuit for converting multi-channel electrical signals into multi-channel optical signals of different wavelengths, and outputting the same; said signal input section comprises optical-electrical signal conversion cirucit for converting said multi-channel optical signals of different wavelengths into said multi-channel electrical signals; and said bus line is formed by an optical transmission medium.
- 40. The information processing system as defined in claim 39,
wherein one of said plurality of functional units is a central processing unit (CPU), and said bus line comprises a data bus line and an address bus line.
- 41. The information processing system as defined in claim 40,
wherein one optical transmission medium is used in common for said data bus line and said address bus line.
- 42. The information processing system as defined in claim 40 or 41,
wherein an optical input-output section for providing optical communications with peripheral equipment is connected to said bus line.
- 43. The information processing system as defined in claim 42,
wherein said optical input-output section enables optical communications to and from said peripheral equipment, by a chip select signal transmitted from said central processing unit through said bus line.
- 44. Electronic equipment comprising the information processing system as defined in any one of claims 39 to 43.
- 45. A system LSI formed of a first semiconductor device and a second semiconductor device connected together by an external bus line, wherein:
said first semiconductor device comprises a first signal output section and a first signal output section, and a central processing unit (CPU) operating based on multi-channel electrical signals is formed on a first substrate; said second semiconductor device comprises a second signal output section and a second signal input section, and a controlled unit that is controlled by signals from said central processing unit and operates based on multi-channel electrical signals is formed on a second substrate; each of said first and second signal output sections comprises electrical-optical signal conversion circuit for converting multi-channel electrical signals into multi-channel optical signals having different wavelengths, and outputting the same; each of said first and second signal input sections comprises optical-electrical signal conversion circuit for converting multi-channel optical signals having different wavelengths into multi-channel electrical signals; and said external bus line is formed by an optical transmission medium.
- 46. The system LSI as defined in claim 45, wherein said controlled unit is cache memory.
- 47. Electronic equipment comprising the system LSI as defined in claim 45 or 46.
- 48. A system LSI incorporating a plurality of functional blocks developed by different manufacturers, wherein:
at least one of said plurality of functional blocks comprises a four-arithmetical-operations function area; and said four-arithmetical-operations function area executes computations for decryption when a predetermined decryption key has been input thereto, and a four-arithmetical-operations function other than said decryption is enabled after said decryption is established.
- 49. The system LSI as defined in claim 48, wherein:
said four-arithmetical-operations function area comprises:
a plurality of arithmetic units, each computing to an arithmetic precision of 2m bits (where m is a natural number and is fixed), based on a processing sequence; and a plurality of cascade connection terminals for cascading said arithmetic units, wherein, when the maximum arithmetic precision that is. required during computational processing is 2n bits (where n is a natural number and is fixed), x numbers of said arithmetic units are cascaded (where x is a natural number and is fixed) in a manner such that the inequality x≧2n/2m is satisfied.
- 50. The system LSI as defined in claim 49, wherein:
when an arithmetic precision of 2n1 bits (where n1≦n, and n1 is variable) is required during computational processing, x1 numbers of said arithmetic units are cascaded in a manner such that the inequality x1≧2n1/2m (where x1 is a natural number and is variable) is satisfied.
- 51. The system LSI as defined in claim 49,
wherein optical signals are transmitted between said plurality of arithmetic units.
- 52. The system LSI as defined in claim 49, wherein:
a portion of said plurality of arithmetic units comprises a plurality of power residue arithmetic units that are cascaded; each of said plurality of power residue arithmetic units comprises: a multiplication unit for performing a multiplication at a multiplication precision of 2m bits (where m is a natural number and is fixed); and a division unit for performing a division at a division precision of 22×m bits; and when the maximum arithmetic precision of a power residue computation executed by said plurality of power residue arithmetic units is 2n (where n is a natural number and is fixed); x numbers of said plurality of power residue arithmetic units are connected together for decryption in a manner such that the following inequality is satisfied: x≧2n/2m (where x is a natural number and is fixed).
- 53. The system LSI as defined in claim 52,
wherein, when an arithmetic precision of 2n1 bits (where n1≦n, and ni is variable) is required during computational processing, x1 numbers of said plurality of power residue arithmetic units are cascaded in a manner such that the inequality x1≧2n1/2m (where x1≦x and is variable) is satisfied.
- 54. The system LSI as defined in claim 52,
wherein optical signals are transmitted between said plurality of power residue arithmetic units.
- 55. Electronic equipment comprising a system LSI as defined in claim 48.
Priority Claims (2)
Number |
Date |
Country |
Kind |
9-340439 |
Dec 1997 |
JP |
|
10-259283 |
Aug 1998 |
JP |
|
CONTINUING APPLICATION DATA
[0001] This application is a divisional of U.S. patent application Ser. No. 09/367,234, filed Oct. 13, 1999, which is a 371 of PCT/JP98/05586, filed Dec. 10, 1998, each of which is incorporated herein in its entirety by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09367234 |
Oct 1999 |
US |
Child |
10375995 |
Feb 2003 |
US |