Claims
- 1. A converter circuit for providing an output signal of a first polarity responsive to a periodic low frequency input signal varying between two voltage limit values of a second polarity different from the first polarity, comprising:
- a) a first capacitor having a first of two terminals connected to receive the input signal;
- b) an inverting amplifier receiving the input signal and providing a signal varying between the voltage limit values, and inverted with respect to the input signal;
- c) a second capacitor having a first of two terminals connected to receive the inverting amplifier output;
- d) first and second resistors connecting second terminals of the first and second capacitors respectively to ground;
- e) first and second diodes having first terminals connected together, with the second terminals connected respectively to the second terminals of the first and second capacitors, said diodes oriented for back biasing by the input signal and the inverted signal;
- f) a third resistor having a first of two terminals connected to the first and second diodes, first terminals;
- g) a third capacitor connected between ground and a second terminal of the third resistor and providing the signal at the third resistor's second terminal; and
- h) a resistive path connected to discharge the third capacitor.
- 2. The circuit of claim 1, wherein the inverting amplifier comprises an operational amplifier having first and second input terminals and receiving a fixed voltage level falling between the voltage limit values on the first terminal, and the input signal on the second terminal.
- 3. The circuit of claim 1, wherein the first and second capacitors have equal values.
- 4. The circuit of claim 3, wherein the first and second capacitor value is smaller than the value of the third capacitor.
- 5. The circuit of claim 3, wherein the first and second resistors have equal values.
- 6. The circuit of claim 1, wherein the first and second resistors have equal values.
- 7. The circuit of claim 6, including a fourth resistor having a first terminal connected to the second terminal of the third resistor and providing the output signal on a second terminal.
- 8. The circuit of claim 1, including a voltage source, an infrared-sensitive cell having a first of two terminals connected to a first terminal of the voltage source, a fourth resistor connecting the second of the cell's terminals to a second terminal of the voltage source, a level shift detector sensing the voltage across the fourth resistor, and providing an output signal voltage which has the first polarity responsive to a steady state voltage across the fourth resistor and the second polarity otherwise, and a second diode circuit comprising a diode and a resistor in series connection conducting the output signal from the level shift detector to the third resistor's second terminal, said second diode circuit's diode oriented to be back biased by an output signal voltage of the first polarity from the level shift detector.
- 9. The circuit of claim 1, wherein the diodes, first terminals are anodes, and wherein the voltage limit values polarity is positive.
- 10. The circuit of claim 9, wherein the first and second capacitors have equal values.
- 11. The circuit of claim 10, wherein the first and second capacitor value is smaller than the value of the third capacitor.
- 12. The circuit of claim 11, wherein the first and second resistors have equal values.
- 13. The circuit of claim 11, wherein the value of the third resistor is approximately two order of magnitude less than the values of the first and second resistors.
- 14. A circuit for providing an output signal of a first polarity responsive to a low frequency input signal varying between first and second voltage limit values both having polarity differing from that of the output signal, comprising:
- a) a first capacitor having a first of two terminals connected to receive the input signal;
- b) a first resistor connecting a second of the first capacitor's two terminals to ground;
- c) a diode circuit comprising a diode and a second resistor in series connection, said diode circuit having a first of two terminals connected to the second terminal of the first capacitor, said diode oriented in the diode circuit for back biasing by the input signal;
- d) a second capacitor connected between ground and a second terminal of the diode circuit; and
- e) a resistive path connected to discharge the second capacitor,
- wherein the output signal arises from current drawn from the second capacitor.
- 15. The circuit of claim 14, wherein the output signal polarity is negative and the voltage limit values are positive, and wherein the diode circuit's first terminal is connected to the diode's cathode.
- 16. The circuit of claim 14, wherein the resistance in the resistive path has a magnitude approximately that of the first resistor.
- 17. The circuit of claim 14, wherein the resistive path comprises a third resistor connected in parallel with the second capacitor.
- 18. The circuit of claim 17, wherein the value of the third resistor is approximately two orders of magnitude less than the value of the first resistor.
- 19. The circuit of claim 18, wherein the resistive path comprises a third resistor connected in parallel with the diode.
- 20. The circuit of claim 14, wherein the value of the third resistor is approximately two orders of magnitude less than the value of the first resistor.
Parent Case Info
This application is a continuation of application Ser. No. 07/808,382, filed Dec. 16, 1991 now abandoned.
US Referenced Citations (8)
Continuations (1)
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Number |
Date |
Country |
Parent |
808382 |
Dec 1991 |
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