Patent Application
20250239297
This application claims priority to and the benefit both of Korean Patent Application No. 2024-0008959 filed on Jan. 19, 2024, and No. 2024-0198387 filed on Dec. 27, 2024, the disclosures of which are incorporated herein by reference in their entirety.
The present invention relates to an input/output sense amplifier circuit and a semiconductor memory device including the same.
The content described in this section simply provides background information for embodiments of the present invention and does not constitute the related art.
An input/output sense amplifier (IOSA) circuit is one sense amplifier circuit and is used to sense and correct an input offset voltage that may occur during a dynamic random access memory (DRAM) data reading process. An IOSA circuit is particularly important in application fields that require precise measurement and control.
An IOSA circuit senses small mismatches or imbalances between two input terminals of an operational amplifier circuit and automatically adjusts the sensed mismatches or imbalances to improve the overall performance of the operational amplifier circuit.
Conventional IOSA circuits have several major problems. First, a sensing yield tends to decrease as an offset of the IOSA circuit increases due to process, voltage, and temperature (PVT) variations. This means a decrease in sensing efficiency. Second, in order to improve a sensing yield, a strength required to drive a long global input/output (GIO) line should be large. This leads to an increase in power consumption of a GIO line and power consumption of the IOSA circuit itself.
Previous studies have proposed two methods to solve these problems. A first proposed method is a self-timed method IOSA circuit, in which an IOSA circuit transmits sensed data to a set-reset (SR) latch, and when the data is stored in the SR latch, a turn-off signal is generated to turn off the IOSA circuit. A second proposed method is a hybrid IOSA circuit, in which a pre-amplifier determines a voltage input of a main amplifier and determines an N-type metal-oxide-semiconductor (NMOS) (N-channel metal-oxide semiconductor field-effect transistor (MOSFET)) operation of the main amplifier. This reduces current consumption and improves speed, but these IOSA circuits require large voltage swings in a GIO line for robust detection, which causes a GIO line driving power problem as a GIO line driving strength increases.
The present invention is directed to providing an input/output sense amplifier circuit that is capable of eliminating input attenuation, reducing an area of a circuit, reducing a time required for offset cancellation (OC), and reducing a sensing time by connecting an input directly to the source of a P-type metal oxide-semiconductor (PMOS) and connecting one small metal-oxide-semiconductor capacitor (MOSCAP) between two gates of the PMOS to which inputs are connected, and a semiconductor memory device including the same.
Other unspecified objects of the present invention may be additionally considered within a scope that can be easily inferred from the following detailed description and its effects.
According to an aspect of the present invention, there is provided an input/output sense amplifier circuit in a sense amplifier circuit, which includes a 1-1 transistor having a source connected to a first global input/output line, a 1-2 transistor having a source connected to a second global input/output line, and a metal-oxide-semiconductor capacitor (MOSCAP) configured to connect a gate of the 1-1 transistor to a gate of the 1-2 transistor.
Here, the input/output sense amplifier circuit may further include a 2-1 transistor configured to connect the MOSCAP to the 1-1 transistor through a 1-1 node connected to the gate of the 1-1 transistor, and a 2-2 transistor configured to connect the MOSCAP to the 1-2 transistor through a 1-2 node connected to the gate of the 1-2 transistor.
Here, the input/output sense amplifier circuit may further include a 1-1 switch configured to connect or disconnect a 2-1 node connected to a drain of the 1-1 transistor to or from the 1-1 node, and a 1-2 switch configured to connect or disconnect a 2-2 node connected to a drain of the 1-2 transistor to or from the 1-2 node.
Here, the input/output sense amplifier circuit may further include a 2-1 switch configured to connect or disconnect a 3-2 node located between the 1-2 node and the 1-2 switch to or from the 2-1 node, and a 2-2 switch configured to connect or disconnect a 3-1 node located between the 1-1 node and the 1-1 switch to or from the 2-2 node.
Here, the input/output sense amplifier circuit may further include a 3-1 transistor having a gate connected to the 2-2 node and a source connected to the 2-1 node, and a 3-2 transistor having a gate connected to the 2-1 node and a source connected to the 2-2 node.
Here, a drain of the 3-1 transistor and a drain of the 3-2 transistor may be connected through a fourth node, the fourth node may be connected to a source of the fifth transistor, and a drain of the fifth transistor may be connected to a ground.
Here, the input/output sense amplifier circuit may further include a 4-1 transistor having a source connected to the 2-1 node and a drain connected to the ground, and a 4-2 transistor having a source connected to the 2-2 node and a drain connected to the ground.
Here, the 1-1 transistor may be connected to the first global input/output line through a 5-1 transistor connected to the source of the 1-1 transistor, and the 1-2 transistor may be connected to the second global input/output line through a 5-2 transistor connected to the source of the 1-2 transistor.
Here, the 4-1 transistor may be a transistor having a different channel type from the 5-1 transistor, and the 4-2 transistor may be a transistor having a different channel type from the 5-2 transistor.
Here, a gate of the 4-1 transistor, a gate of the 4-2 transistor, a gate of the 5-1 transistor, and a gate of the 5-2 transistor may receive the same signal.
The input/output sense amplifier circuit may further include a controller that controls the input/output sense amplifier circuit, wherein the controller may turn off the 5-1 transistor and the 5-2 transistor, turn on the 1-1 switch and the 1-2 switch, turn on the 4-1 transistor and the 4-2 transistor, and turn on the 2-1 transistor and the 2-2 transistor.
The controller may turn on the 1-1 switch and the 1-2 switch, turn on the 2-1 transistor and the 2-2 transistor, turn on the 5-1 transistor and the 5-2 transistor, and turn off the 4-1 transistor and the 4-2 transistor.
The controller may turn on the 2-1 transistor and the 2-2 transistor, turn off the 1-1 switch and the 1-2 switch, turn off the 5-1 transistor and the 5-2 transistor, and turn on the 4-1 transistor and the 4-2 transistor.
The controller may turn on the 2-1 transistor and the 2-2 transistor, turn off the 1-1 switch and the 1-2 switch, turn off the 5-1 transistor and the 5-2 transistor, and turn on the 4-1 transistor and the 4-2 transistor.
The controller may turn off the 2-1 transistor and the 2-2 transistor, turn off the 1-1 switch and the 1-2 switch, turn on the 5-1 transistor and the 5-2 transistor, turn off the 4-1 transistor and the 4-2 transistor, turn on the 2-1 switch and the 2-2 switch, turn on the 3-1 transistor and the 3-2 transistor, and turn on the fifth transistor.
According to another aspect of the present invention, there is provided a semiconductor memory device which includes a bit line sense amplifier circuit configured to amplify memory cell data, a local sense amplifier circuit configured to receive the memory cell data amplified by the bit line sense amplifier circuit through a local input/output line, sense data of the local input/output line, and provide the sensed data to a global input/output line, and an input/output sense amplifier circuit configured to receive data from the local sense amplifier circuit through the global input/output line, operate using a MOSCAP, sense data of the global input/output line, and provide the sensed data to the outside of the semiconductor memory device.
The semiconductor memory device may further include a 1-1 transistor having a source connected to a first global input/output line, a 1-2 transistor having a source connected to a second global input/output line, and a MOSCAP that connects a gate of the 1-1 transistor to a gate of the 1-2 transistor.
Here, the semiconductor memory device may further include a 1-1 switch configured to connect or disconnect a 2-1 node connected to a drain of the 1-1 transistor to or from the 1-1 node, and a 1-2 switch configured to connect or disconnect a 2-2 node connected to a drain of the 1-2 transistor to or from the 1-2 node.
As described above, according to an embodiment of the present invention, by applying an input/output sense amplifier circuit and a semiconductor memory device including the same, the input is directly connected to a PMOS source, and a small MOSCAP (Metal-Oxide-Semiconductor Capacitor) is connected between the two PMOS gates where the input is connected, thereby eliminating input attenuation and reducing the circuit area.
Furthermore, according to an embodiment of the present invention, by applying an input/output sense amplifier circuit and a semiconductor memory device including the same, the time required for offset cancellation (OC) can be reduced, and the sensing time can be shortened.
Even effects not explicitly mentioned here are treated as the effects described in the following specification, along with their potential effects, as expected due to the technical features of the present invention.
Advantages and features of the present invention and methods of achieving the same will be clearly understood with reference to the accompanying drawings and embodiments described in detail below. However, the present invention is not limited to the embodiments described herein but may be implemented in various different forms. merely,
These embodiments are provided to explain in detail the technical idea of the present invention to those skilled in the art to which the present invention pertains so that the technical idea of the present invention may be easily practiced.
In the drawings, the embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Further, portions indicated by the same reference numerals throughout the specification represent the same components.
The term “and/or” is used herein to mean at least one of components listed before and after. Further, the meaning of the expression “connected/coupled” includes direct connection to another component and indirect connection through another component. In this specification, the singular forms include the plural forms unless the context clearly indicates otherwise. Further, it will be understood that the terms “comprise” or “comprising” when used herein specify some stated components, steps, operations, and elements but do not preclude the presence or addition of one or more other components, steps, operations, and elements.
Hereinafter, various embodiments of an input/output sense amplifier (IOSA) circuit and a semiconductor memory device including the same according to the present invention will be described in detail with reference to the accompanying drawings.
The IOSA circuit according to the present invention may be a dynamic random access memory (DRAM) IOSA circuit using power efficient pre-sense (PS) using gate boosting.
Referring to
A source of the 1-1 transistor 111 may be connected to a first global input/output (GIO) line GIOB. The 1-1 transistor 111 may be connected to the first GIO line GIOB through a 5-1 transistor 143 connected to the source of the 1-1 transistor 111.
A source of the 1-2 transistor 112 may be connected to a second GIO line GIO. The 1-2 transistor 112 may be connected to the second GIO line GIO through a 5-2 transistor 144 connected to the source of the 1-2 transistor 112.
The MOSCAP 120 may connect a gate of the 1-1 transistor 111 to a gate of the 1-2 transistor 112.
The IOSA circuit 100 according to one embodiment of the present invention may further include a 2-1 transistor 151 and a 2-2 transistor 152.
The 2-1 transistor 151 may connect the MOSCAP 120 to the 1-1 transistor 111 through a 1-1 node 131 connected to the gate of the 1-1 transistor 111.
The 2-2 transistor 152 may connect the MOSCAP 120 to the 1-2 transistor 112 through a 1-2 node 132 connected to the gate of the 1-2 transistor 112.
The IOSA circuit 100 according to one embodiment of the present invention may further include a 1-1 switch 161 and a 1-2 switch 162.
The 1-1 switch 161 may connect or disconnect a 2-1 node 133 connected to a drain of the 1-1 transistor 111 to or from the 1-1 node 131.
The 1-2 switch 162 may connect or disconnect a 2-2 node 134 connected to a drain of the 1-2 transistor 112 to or from the 1-2 node 132.
The IOSA circuit 100 according to one embodiment of the present invention may further include a 2-1 switch 163 and a 2-2 switch 164.
The 2-1 switch 163 may connect or disconnect a 3-2 node 136 located between the 1-2 node 132 and the 1-2 switch 162 to or from the 2-1 node 133.
The 2-2 switch 164 may connect or disconnect a 3-1 node 135 located between the 1-1 node 131 and the 1-1 switch 161 to or from the 2-2 node 134.
The 1-1 switch 161, the 1-2 switch 162, the 2-1 switch 163, and the 2-2 switch 164 may be complementary metal-oxide semiconductor (CMOS) transmission gates, but the present invention is not necessarily limited thereto.
The IOSA circuit 100 according to one embodiment of the present invention may further include a 3-1 transistor 115 and a 3-2 transistor 116.
The 3-1 transistor 115 may have a gate connected to the 2-2 node 134 and a source connected to the 2-1 node 133.
The 3-2 transistor 116 may have a gate connected to the 2-1 node 133 and a source connected to the 2-2 node 134.
A drain of the 3-1 transistor 115 and a drain of the 3-2 transistor 116 may be connected through a fourth node 137. The fourth node 137 may be connected to a source of a fifth transistor 153. A drain of the fifth transistor 153 may be connected to a ground GND.
The IOSA circuit 100 according to one embodiment of the present invention may further include a 4-1 transistor 141 and a 4-2 transistor 142.
The 4-1 transistor 141 may have a source connected to the 2-1 node 133 and a drain connected to the ground.
The 4-2 transistor 142 may have a source connected to the 2-2 node 134 and a drain connected to the ground.
The 4-1 transistor 141 may be a transistor having a different channel type from the 5-1 transistor 143. For example, when the 4-1 transistor 141 is a P-type metal-oxide semiconductor (PMOS), the 5-1 transistor 143 may be an N-type metal-oxide-semiconductor (NMOS).
The 4-2 transistor 142 may be a transistor having a different channel type from the 5-2 transistor 144. For example, when the 4-2 transistor 142 is a PMOS, the 5-2 transistor 144 may be an NMOS.
A gate of the 4-1 transistor 141, a gate of the 4-2 transistor 142, a gate of the 5-1 transistor 143, and a gate of the 5-2 transistor 144 may receive the same signal.
Several major features of the “DRAM IOSA circuit using power efficient PS,” which is the present invention, are provided. Referring to
Second, by simultaneously performing an input phase using the small MOSCAP in a pull down (PD) phase and a PS phase, a time consumed for offset cancellation (OC) may be reduced, and a sensing time may be reduced because no overhead occurs despite the addition of the phase.
Lastly, by using power efficient PS, the influence of an offset of the non-OC transistor (TR) may be reduced, and the problems of the related art may be solved in the same way with the PS where static current does not flow.
Referring to
The IOSA circuit may remain in the state of the pre-charge operation until a read operation is performed.
Referring to
Accordingly, a voltage VDD-VTHL may be stored in the gate of the 1-1 transistor 111.
Here, a voltage VTHL may be a voltage VTH of the 1-1 transistor 111. Further, accordingly, a voltage VDD-VTHR may be stored in the gate of the 1-2 transistor 112. Here, a voltage VTHR may be a voltage VTH of the 1-2 transistor 112.
Accordingly, a voltage VTH difference (i.e., a difference between the voltage VTHL and the voltage VTHR) between the 1-1 transistor 111 and the 1-2 transistor 112 may be stored in a MOSCAP 120.
In the PD operation, first, the 1-1 switch 161 and the 1-2 switch 162 that were in the ON state during the pre-charge operation and offset cancel operation may turn OFF.
Accordingly, the gates of the 1-1 transistor 111 and 1-2 transistor 112 may be floated.
Next, as in the pre-charge operation, the 5-1 transistor 143 and the 5-2 transistor 144 may turn OFF again, and the 4-1 transistor 141 and the 4-2 transistor 142 may turn ON. Accordingly, a 2-1 node 133 and a 2-2 node 134, which were each stored with a voltage VDD-VTH, may be connected to the ground and discharged.
In the PD operation, coupling occurs due to parasitic capacitance between the gate and drain of each of the 1-1 transistor 111 and 1-2 transistor 112. As the coupling occurs, the voltage stored in the gate of the 1-1 transistor 111 may be lowered from VDD-VTHL to VDD-VTHL-α, and the voltage stored in the gate of the 1-2 transistor 112 may be lowered from VDD-VTHR to VDD-VTHR-α.
The 5-1 transistor 143 and the 5-2 transistor 144 may turn OFF, and input voltages VDD and VDD-ΔGIO may be formed on the first GIO line GIOB and the second GIO line GIO, respectively. ΔGIO may denote a voltage difference between the first GIO line GIOB and the second GIO line GIO.
In the PS operation, the 5-1 transistor 143 and the 5-2 transistor 144 that were in the OFF state during the PD operation may turn ON again, and the 4-1 transistor 141 and the 4-2 transistor 142 that were in the ON state during the PD operation may turn OFF.
Accordingly, the 2-1 node 133 (Dout) may be charged by a voltage difference between the source and gate of the 1-1 transistor 111, and the 2-2 node 134 (DoutB) may be charged by a voltage difference between the source and gate of the 1-2 transistor 112. The voltage charged to the 2-2 node 134 (DoutB) may be smaller than the voltage charged to the 2-1 node 133 (Dout).
In the MS operation, the 2-1 transistor 151 and the 2-2 transistor 152 that were in the ON state during all the previous operations may turn OFF.
Further, in the MS operation, a 2-1 switch 163, a 2-2 switch 164, a 3-1 transistor 115, a 3-2 transistor 116, and a fifth transistor 153 that were in an OFF state during all the previous operations may turn ON.
Accordingly, the voltage charged to the first GIO line GIOB may be input to a gate of the 3-2 transistor 116, and the voltage charged to the second GIO line GIO may be input to a gate of the 3-1 transistor 115.
In previous technologies, a large capacitor (CAP) was used to reduce input attenuation, but in the present invention, an input and the storage of a threshold voltage VTH are separated and the input is directly transmitted to a PMOS source. This may eliminate the need for a large CAP, resulting in eliminating input attenuation and reducing an area.
The IOSA circuit of the present invention uses a small CAP, which shortens a time required for OC. The IOSA circuit of the present invention may provide inputs in PD and PS phases and thus a sensing time may be reduced. Accordingly, the IOSA circuit of the present invention may be combined with a small MOSCAP overall and thus the efficiency and speed of a sensing process may be improved.
In
In the IOSA circuit of the present invention, a gate voltage of an NMOS may be developed through a power efficient PS function to reduce the influence of variation of a threshold voltage VTH of a non-OC TR. Two inputs may be used in an MS phase. The voltage developed in the PS phase may be provided as a gate input, and another input may be provided as a PMOS source. By providing these two inputs simultaneously in the MS phase, an offset may be reduced.
Unlike the previous PS structures (e.g., an inverter (see
The IOSA circuit of the present invention has several major features compared to a conventional OC-IOSA circuit. First, in terms of offset reduction, in the OC-IOSA circuit, an offset of a non-OC TR is not considered, but in the IOSA circuit of the present invention, the influence of the offset may be reduced through PS.
Further, in the OC-IOSA circuit, input attenuation occurs during an input coupling process, whereas in the IOSA circuit of the present invention, such a problem does not occur because an input is directly transmitted to the source of a PMOS.
Second, in terms of area reduction, in the OC-IOSA circuit, a large MOSCAP is used for input coupling, whereas in the IOSA circuit of the present invention, a small MOSCAP is used while directly transmitting the input. Accordingly, an overall area of a circuit is reduced.
Third, in terms of power consumption, in the conventional OC-IOSA circuit, there was a problem in that static current was generated because a gate voltage was not fully driven while MOSCAP coupling was used in an MS process. However, in the IOSA circuit of the present invention, such a problem is solved by disconnecting a MOSCAP connection so that a gate voltage may be fully driven during an MS process. Further, static current does not flow during a PS process, and thus a power overhead is reduced.
Lastly, in terms of sensing time, in the OC-IOSA circuit, a long time is required for OC because a large MOSCAP is used, but in the IOSA circuit of the present invention, a time required for OC may be reduced because a small MOSCAP is used. Further, instead of performing an input phase separately, the input phase may be performed simultaneously with the PD and PS phases, thereby reducing a sensing time overhead.
According to the present invention, the semiconductor memory device may include a BLSA circuit, a local sense amplifier (LSA) circuit, and an IOSA circuit.
The BLSA circuit may amplify memory cell data.
The LSA circuit may receive the memory cell data amplified by the BLSA circuit through a local input/output (LIO) line LIOB/LIO, sense data of the LIO line, and provide the sensed data to a GIO line GIOB/GIO.
The IOSA circuit may receive data from the LSA circuit through the GIO line, operate using a MOSCAP, sense data of the GIO line, and provide the sensed data to the outside of the semiconductor memory device. The IOSA circuit may be as described with reference to
A read operation of the semiconductor memory device to which the present technology is applied may include the following overall process. First, data of a DRAM cell may be amplified using a BLSA. The amplified data may be transmitted to the LIO line through a column select line (CSL).
Thereafter, the LSA may sense data of the LIO line and transmit the sensed data to the GIO line.
Finally, the IOSA circuit may sense data of the GIO line and transmit the sensed data to the outside of the DRAM.
In the operation of the IOSA circuit, a line GIO/B is in a pre-charge state with a voltage VDD.
The LSA drives a long GIO line to transmit an input. Since the capacitance of the GIO line is large, a small voltage swing may be used. The IOSA is required to amplify this small voltage swing and transmit data to the outside of the DRAM. This process allows efficient transmission and amplification of data.
As described above, according to one embodiment of the present invention, by applying an IOSA circuit and a semiconductor memory device including the same, it is possible to eliminate input attenuation and reduce an area of a circuit by connecting an input directly to the source of a PMOS and connecting one small MOSCAP between two gates of the PMOS to which an input is connected.
Further, according to one embodiment of the present invention, by applying the IOSA circuit and the semiconductor memory device including the same, it is possible to reduce a time required for OC and reduce a sensing time.
Even effects that are not explicitly described herein and provisional effects expected from the technical features of the present invention are treated as described in the specification of the present invention.
Other similar or dissimilar changes are possible within the scope that does not depart from the technical idea of the present invention. Therefore, the technical idea of the present invention may be claimed in other ways as well as the appended claims.
The above description is only an example describing the technical spirit of the present invention. Various changes, modifications, and replacements may be made without departing from the spirit and scope of the present invention by those skilled in the field of medical devices. Therefore, the embodiments disclosed in the present invention and the accompanying drawings should be considered in a descriptive sense only and not for limiting the technological scope. The technical spirit of the present invention is not limited by these embodiments and the accompanying drawings. It should be understood that the scope of the present invention is interpreted according to the appended claims and encompasses all equivalent technological scopes.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2024-0008959 | Jan 2024 | KR | national |
| 10-2024-0198387 | Dec 2024 | KR | national |
