A flash solid state memory device (“SSD”) typically achieves significantly higher write-only and read-only bandwidth when compared to the bandwidth observed for mixed read-write workloads.
Conventional input-output (“IO”) scheduling schemes typically issue write commands to an SSD memory immediately upon receiving the request from an application layer. Further, writes tend to be randomly distributed over time. For example, an application writing at 200 MB/s with 128 KB block size would typically issue write IOs approximately separated by about 0.64 ms on average.
Described is a write scheduling scheme for a SSD that significantly increases read performance, in certain embodiments by about 50% compared to a conventional standard write scheduling schemes, for mixed read-write workloads while maintaining the write bandwidth.
These and other aspects and features will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures, wherein
As mentioned above, flash SSDs typically achieve significantly higher write-only and read-only bandwidth when compared to the bandwidth observed for mixed read-write workloads. Within the context of a mixed read-write workload, write commands and read commands are issued at different points in time. As illustrated in
With respect to SSD memory 116-2, reads and write commands are typically issued by an application (in user-mode) or by the operating system's kernel on behalf of the application. In contrast to conventional IO scheduling schemes that typically issue write commands to an SSD memory such as 116-2 immediately upon receiving the request from the application layer, the write scheduling scheme described herein does not perform writes at and when they are received from the application layer. Instead, the write scheduling scheme accumulates write requests for a period of time, such as between ˜1 ms to ˜30 ms, with a preferable period of time being about ˜10-20 ms, such as reading each request into a DRAM buffer memory 116-1, and then issues them back to back into the SSD memory 116-2 in a burst, by writing them out of the DRAM buffer memory 116-1 in a back to back manner. Using the same example of a storage application writing at ˜200 MB/s with 128 KB block size provided in the background, the proposed scheduling scheme accumulates a maximum of 32 writes for ˜20 ms and issues them back to back, such that with a back to back write the 32 writes are typically executed within a burst of about 2-4 ms.
The advantage of scheduling writes in this manner shows up in the observed maximum sustained read bandwidth. In particular, an increase in available read bandwidth from flash based SSDs by ˜50% simultaneously sustaining the write bandwidth at the same level. 50% increase in read bandwidth significantly improves storage application performance.
The plot provided in
In addition, the features described herein can be used with the features that are described in U.S. patent application Ser. No. 15/159,654 entitled “Endurance Aware Raid Scheme For Flash Based SSDs With FPGA Optimized Implementation” filed on the same day as this application, which is expressly incorporated by reference herein.
Although the present invention has been particularly described with reference to embodiments thereof, it should be readily apparent to those of ordinary skill in the art that various changes, modifications and substitutes are intended within the form and details thereof, without departing from the spirit and scope of the invention. Accordingly, it will be appreciated that in numerous instances some features of the invention will be employed without a corresponding use of other features. Further, those skilled in the art will understand that variations can be made in the number and arrangement of components illustrated in the above figures.
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