Input/output circuit having an inductor

Abstract

An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. The circuitry comprises at least one pre-driver stage having at least one output node, and the at least one output node of the at least one pre-driver stage is electrically coupled with at least one input node of a driver stage.

Description

TECHNICAL FIELD

The present disclosure relates generally to the field of semiconductor devices, and more particularly, to input/output (I/O) circuits with inductors.

BACKGROUND

As semiconductor technology develops, integrated circuits often contain devices operating at a high voltage level, and other devices operating at a low voltage level. The low voltage devices cannot tolerate a high voltage signal. Device failures happen frequently, when the low voltage devices operate with the high voltage signal. In order to protect the low voltage devices from the high voltage signals, the integrated circuit often includes an input/output (I/O) circuit as an interface between the low voltage devices and the high voltage devices. The I/O circuit allows the low voltage devices to communicate with the high voltage devices, while protecting the low voltage devices from being damaged by the high voltage signals.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure may be understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic drawing of an input/output (I/O) circuit according to some embodiments.

FIG. 2 is a schematic drawing illustrating an exemplary I/O circuit including at least one pre-driver stage according to some embodiments.

FIG. 3 is a schematic drawing illustrating an exemplary I/O circuit including at least one level shifter according to some embodiments.

DETAILED DESCRIPTION

An input/output (I/O) design has a bandwidth of about 8 gigahertz (GHz) or less. The bandwidth of this I/O design is compromised by high parasitic capacitances of electrostatic discharge (ESD) protection circuits that are added to output nodes of the I/O. In some instances, the parasitic capacitances of the ESD protection circuits are reduced. However, the parasitic capacitances cannot be reduced in designing some high bandwidth I/Os.

During designing an I/O accommodating a bandwidth of about 10 GHz or more, an inductive peaking technique uses a pair of inductors, each of which is electrically coupled between a loading resistor and a supply voltage VDD. In some instances, the inductance of the inductor may be around 0.3 nanoheneries (nH) for a design with a 40-nm technology node or smaller.

As the technology node of integrated circuits shrinks, an area available for an I/O design becomes smaller. In some embodiments, the design of the 0.3-nH inductors for inductive peaking may be too large to fit into a single I/O pitch. The large inductors and the small I/O pitch make the I/O design challenging for the small technology node.

It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG. 1 is a schematic drawing of an input/output (I/O) circuit. In FIG. 1, an I/O circuit 100 includes a driver stage 110 that is electrically coupled with a circuitry 130. The driver stage 110 includes at least one input node, e.g., input nodes N₁ and N₂, and at least one output node, e.g., output nodes N₃ and N₄. The input nodes N₁ and N₂ are electrically coupled with gates of transistors M₁ and M₂ of the driver stage 110, respectively. Drains of the transistors M₁ and M₂ each are electrically coupled with the respective output nodes N₃ and N₄. In FIG. 1, the output nodes N₃ and N₄ of the driver stage 110 are the output nodes of the I/O circuit 100.

In some embodiments, the driver stage 110 includes at least one electrostatic discharge (ESD) protection circuit, e.g., ESD protection circuits 120a and 120b, which are electrically coupled with the respective output nodes N₃ and N₄ of the I/O circuit 100. The ESD protection circuits 120a and 120b are configured to protect the I/O circuit 100 from being damaged by a momentary electrostatic discharge event that happens to the output nodes N₃ and N₄. In some embodiments, the ESD protection circuits 120a and 120b each have a parasitic capacitance of about 400 femtofarads (fF) or more.

Referring to FIG. 1, the I/O circuit 100 includes at least one inductor, e.g., inductors L₁ and L₂, which are electrically coupled with respective loadings, e.g., resistors R₁ and R₂ in a series fashion. The inductor L₁ and the resistor R₁ are electrically coupled between the output node N₃ and a power line that is configured to provide a supply voltage VDD. The inductor L₂ and the resistor R₂ are electrically coupled between the output node N₄ and the power line that is configured to provide a supply voltage VDD. In some embodiments, the supply voltage VDD is about 1.8 V, the inductance of each inductor is about 0.1 nanohenry (nH) or less, and the resistance of each resistor is about 50 ohm (Ω). As the inductance of each inductor is low, the area used by the inductor design is small such that the inductors 120a and 120b can be designed in a single I/O pitch. In some embodiments, the I/O pitch is about 30 μm or less.

It is noted that the inductance, parasitic capacitance, supply voltage and/or resistance described above in conjunction with FIG. 1 are merely exemplary. The scope of this application is not limited thereto. In some embodiments, the inductance, parasitic capacitance, supply voltage and/or resistance may be modified in response to a change of the technology node, the bandwidth design of the I/O circuit and/or other design changes.

Referring again to FIG. 1, the circuitry 130 is operable to increase a current I_T flowing through the inductor L₁ or L₂ during a signal transition. For example, a pair of signals having opposite voltage states are applied to the input nodes N₁ and N₂. The signals turn off and on the respective transistors M₁ and M₂, such that a current is flowing through the inductor L₂.

During the signal transition, the signal applied to the input node N₁ turns on the transistor M₁ and another signal that applied to the input node N₂ turns off the transistor M₂. As the current I_T flowing through the inductor L₁ is increased and/or induced by the circuitry 130, a portion of the current I_T flows through the resistor R₁ and the remaining portion of the current I_T flows through the circuitry 130. Even if the inductance of the inductor L₁ is small, e.g., about 0.1 nH or less, the voltage differential across the inductor L₁ is increased due to the increase of the current I_T. The pull-up of the voltage level on the node N₃ becomes fast. By increasing the current I_T, not only can the bandwidth of the I/O circuit 100 be increased, but also the small inductor L₁ can be designed in a single I/O pitch.

FIG. 2 is a schematic drawing illustrating an exemplary I/O circuit including at least one pre-driver stage. The at least one pre-driver stage is operable to generate pre-driver signals applied to the input nodes N₁ and N₂ of the driver stage 110. The at least one pre-driver stage is also operable to increase and/or induce the current I_T flowing through the inductors L₁ and L₂.

In some embodiments, the circuitry 130 includes at least one pre-driver stage, e.g., pre-driver stages 230a and 230b. The pre-driver stages 230a and 230b each include respective input nodes N₇-N₈ and N₁₃-N₁₄, and respective output nodes N₉-N₁₀ and N₁₅-N₁₆. The pre-driver stages 230a and 230b each also include respective transistor pairs M₃-M₄ and M₅-M₆. Gates of the transistors M₃-M₆ each are electrically coupled with the respective input nodes N₇, N₈, N₁₃ and N₁₄. The output nodes N₉, N₁₀, N₁₅ and N₁₆ are electrically coupled with the respective input nodes N₂, N₁, N₈ and N₇.

Referring again to FIG. 2, the pre-driver stages 230a and 230b include respective resistor pairs R₃-R₄ and R₅-R₆. In some embodiments, the pre-driver stages 230a and 230b are electrically coupled with the node N₅ between the inductor L₁ and the resistor R₁ and the node N₆ between the inductor L₂ and the resistor R₂. For example, nodes N₁₁ and N₁₇ of the pre-driver stages 230a and 230b, respectively, are electrically coupled with the node N₅. Nodes N₁₂ and N₁₈ of the pre-driver stages 230a and 230b, respectively, are electrically coupled with the node N₆.

As noted, during the signal transition the current I_T flowing through the inductor L₁ of the driver stage 110 is increased. If the nodes N₁₁ and N₁₇, and N₁₂ and N₁₈ were not electrically coupled with the respective nodes N₅ and N₆, the current I_T would have been substantially equal to a current I₁ flowing through the resistor R₁. In FIG. 2, as the nodes N₁₁ and N₁₇, and N₁₂ and N₁₈ are electrically coupled with the respective nodes N₅ and N₆, the current I_T is substantially equal to the sum of currents I₁, I₂ and I₃ that flow through the resistors R₁, R₃ and R₅ of the driver stage 110 and pre-driver stages 230a and 230b, respectively. In some embodiments, the currents I₁, I₂ and I₃ are substantially equal to each other. In some embodiments, the term “equal” here means that the currents I₁, I₂ and I₃ have the same frequency, phase and/or amplitude.

It is noted that the number of the pre-driver stages 230a and 230b described above in conjunction with FIG. 2 is merely exemplary. The scope of this application is not limited thereto. In some embodiments, a single pre-driver stage or more than two pre-driver stages are applied to increase and/or induce the current I_T. The number of the pre-driver stages may be changed in response to the design of the inductors, the differences of current phase and/or frequency of the currents flowing through the respective driver stages, and/or other design of the I/O circuit.

FIG. 3 is a schematic drawing illustrating an exemplary I/O circuit including at least one level shifter. The at least one level shifter is operable to shift voltage stages of signals applied to the input nodes N₁ and N₂ of the driver stage 110. The at least one level shifter is also operable to increase and/or induce the current I_T flowing through the inductors L₁ and L₂.

In some embodiments, the circuitry 130 includes at least one level shifter, e.g., level shifters 330a and 330b. The level shifters 330a and 330b each include respective input nodes N₁₉-N₂₀ and N₂₅-N₂₆, and respective output nodes N₂₁-N₂₂ and N₂₇-N₂₈. The level shifters 330a and 330b each also include respective transistors M₇-M₁₀ and M₁₁-M₁₄. In some embodiments, the transistors M₇-M₈ and M₁₁-M₁₂ are N-type transistors and the transistors M₉-M₁₀ and M₁₃-M₁₄ are P-type transistors. Gates of the transistors M₇-M₈ each are electrically coupled with the respective input nodes N₁₉ and N₂₀. The output nodes N₂₁-N₂₂ and N₂₇-N₂₈ are electrically coupled with the respective input nodes N₂, N₁, N₂₀ and N₁₉.

Referring to again FIG. 3, the output nodes N₂₁ and N₂₂ are disposed between the transistors M₇ and M₉ and between the transistors M₈ and M₁₀, respectively. The output nodes N₂₇ and N₂₈ are disposed between the transistors M₁₁ and M₁₃ and between the transistors M₁₂ and M₁₄, respectively. In some embodiments, the level shifters 330a and 330b are electrically coupled with the node N₅ between the inductor L₁ and the resistor R₁ and the node N₆ between the inductor L₂ and the resistor R₂. For example, nodes N₂₃ and N₂₉ are electrically coupled with the node N₅, and nodes N₂₄ and N₃₀ are electrically coupled with the node N₆.

As noted, during the signal transition the current I_T flowing through in the inductor L₁ is increased. If the nodes N₂₃ and N₂₉ and N₂₄ and N₃₀ were not electrically coupled with the respective nodes N₅ and N₆, the current I_T would have been equal to a current I₁ flowing through the resistor R₁. In FIG. 3, as the nodes N₂₃ and N₂₉, and N₂₄ and N₃₀ are electrically coupled with the respective nodes N₅ and N₆, the current I_T is substantially equal to the sum of currents I₁, I₄ and I₅ flowing through the resistor R₁ and the transistors M₉ and M₁₃ of the driver stage 110 and level shifters 330a and 330b, respectively. In some embodiments, the currents I₁, I₄ and I₅ are substantially equal to each other. In some embodiments, the term “equal” here means that the currents I₁, I₄ and I₅ have the same frequency, phase and/or amplitude.

During the signal steady state, the currents flowing through the level shifters 330a and 330b are substantially equal to zero. The current I_T flowing through in the inductor L₁ is substantially equal to the current I₁ that flows through the resistor R₁. Because no substantive current is flowing through the level shifters 330a and 330b during the signal steady state, the power consumed by the I/O circuit 100 is small.

It is noted that the number of the level shifters 330a and 330b described above in conjunction with FIG. 3 is merely exemplary. The scope of this application is not limited thereto. In some embodiments, a single level shifter or more than two level shifters are applied to increase and/or induce the current I_T. The number of the level shifters may be changed in response to the design of the inductors, the differences of current phase and/or frequency of the currents flowing in the respective level shifters, and/or other design of the I/O circuit.

In some embodiments, the level shifter 330a or 330b is replaced with the pre-driver stage 230a or 230b. In other embodiments, an additional driver stage is electrically coupled with the level shifters 330a and 330b in a parallel fashion to increase and/or induce the current I_T.

One aspect of this description relates to an I/O circuit that comprises an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. The I/O circuit also comprises at least one inductor and at least one loading electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. The I/O circuit further comprises a circuitry electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. The circuitry comprises at least one pre-driver stage having at least one output node, and the at least one output node of the at least one pre-driver stage is electrically coupled with at least one input node of a driver stage.

Another aspect of this description relates to an input/output (I/O) circuit that comprises a driver stage that comprises a first electrostatic discharge (ESD) protection circuit electrically coupled with a first output node of the driver stage. The driver stage also comprises a second ESD protection circuit electrically coupled with a second output node of the driver stage. The driver stage further comprises a first inductor and a first resistor electrically coupled in a series fashion and between the first output node of the driver stage and a power line. The driver stage additionally comprises a second inductor and a second resistor electrically coupled in a series fashion and between the second output node of the driver stage and the power line. The I/O circuit also comprises a first circuit electrically coupled with a first node between the first inductor and the first resistor, and a second node between the second inductor and the second resistor. A first output node of the first circuit and a second output node of the first circuit are electrically coupled with a first input node of the driver stage and a second input node of the driver stage, respectively. The first circuit comprises a pre-driver stage or a level shifter.

Still another aspect of this description relates to an input/output (I/O) circuit comprising a driver stage comprising a first electrostatic discharge (ESD) protection circuit. The driver stage also comprises a second ESD protection circuit. The driver stage further comprises a first inductor and a first resistor electrically coupled between a first output node of the driver stage and a power line. The driver stage additionally comprises a second inductor and a second resistor electrically coupled between a second output node of the driver stage and the power line. The I/O circuit also comprises a first level shifter electrically coupled with a first node between the first inductor and the first resistor and a second node between the second inductor and the second resistor. A first output node of the first level shifter is electrically coupled with a first input node of the driver stage and a second output node of the first level shifter is electrically coupled with a second input node of the driver stage.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An input/output (I/O) circuit comprising: an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit;at least one inductor and at least one loading electrically coupled in a series fashion and between the output node of the I/O circuit and a power line; anda circuitry electrically coupled with a node between the at least one inductor and the at least one loading, the circuitry being operable to increase a current flowing through the at least one inductor during a signal transition,wherein the circuitry comprises at least one pre-driver stage having at least one output node, and the at least one output node of the at least one pre-driver stage is electrically coupled with at least one input node of a driver stage, and the at least one pre-driver stage comprises:a first pre-driver stage that is electrically coupled with the node between the at least one loading and the at least one inductor, and electrically coupled with the driver stage; anda second pre-driver stage that is electrically coupled with the node between the at least one loading and the at least one inductor, and electrically coupled with the first pre-driver stage.

2. The I/O circuit of claim 1, wherein during the signal transition, a first current flows through the driver stage, a second current flows through the first pre-driver stage, a third current flows through the second pre-driver stage, and the first, second and third currents are substantially equal to each other.

3. The I/O circuit of claim 1, wherein the circuitry further comprises at least one level shifter having at least one output node, and the at least one output node of the at least one level shifter is electrically coupled with at least one input node of the driver stage.

4. The I/O circuit of claim 3, wherein the at least one level shifter comprises: a first level shifter that is electrically coupled with the node between the at least one inductor and the at least one loading, and electrically coupled with the driver stage; anda second level shifter that is electrically coupled with the node between the at least one inductor and the at least one loading, and electrically coupled with the first level shifter.

5. The I/O circuit of claim 4, wherein during the signal transition, a first current flows through the driver stage, a second current flows through the first level shifter, a third current flows through the second level shifter, and the first, second and third currents are substantially equal to each other.

6. The I/O circuit of claim 4, wherein during a steady state, a current flowing through the first and second level shifters is substantially zero.

7. The I/O circuit of claim 6, wherein the ESD protection circuit has a parasitic capacitance of about 400 femtofarads (fF) or more, and the at least one inductor has an inductance of about 0.1 nanohenry (nH) or less.

8. An input/output (I/O) circuit comprising: a driver stage comprising: a first electrostatic discharge (ESD) protection circuit electrically coupled with a first output node of the driver stage;a second ESD protection circuit electrically coupled with a second output node of the driver stage;a first inductor and a first resistor electrically coupled in a series fashion and between the first output node of the driver stage and a power line; anda second inductor and a second resistor electrically coupled in a series fashion and between the second output node of the driver stage and the power line; anda first circuit electrically coupled with a first node between the first inductor and the first resistor, and a second node between the second inductor and the second resistor, wherein a first output node of the first circuit is electrically coupled with a first input node of the driver stage and a second output node of the first circuit is electrically coupled with a second input node of the driver stage,wherein the first circuit comprises a pre-driver stage or a level shifter.

9. The I/O circuit of claim 8, further comprising: a second circuit electrically coupled with the first node between the first inductor and the first resistor and the second node between the second inductor and the second resistor, a first output node of the second circuit is electrically coupled with a first input node of the first circuit and a second output node of the second circuit is electrically coupled with a second input node of the first circuit,wherein the second circuit comprises a first pre-driver stage, a second pre-driver stage, a first level shifter, or a second level shifter.

10. The I/O circuit of claim 9, wherein the first circuit and the second circuit each are operable to increase a current flowing through the first inductor or the second inductor during a signal transition.

11. The I/O circuit of claim 10, wherein during the signal transition a first current flows through the driver stage, a second current flows through the first circuit, a third current flows through the second circuit, and the first, second and third currents are substantially equal to each other.

12. The I/O circuit of claim 9, wherein during a steady state a current flowing through the first and second circuits is substantially zero.

13. The I/O circuit of claim 8, wherein the first and second ESD protection circuits each have a parasitic capacitance of about 400 femtofarads (fF) or more, and the first and second inductors each have an inductance of about 0.1 nanohenry (nH) or less.

14. An input/output (I/O) circuit comprising: a driver stage comprising: a first electrostatic discharge (ESD) protection circuit;a second ESD protection circuit;a first inductor and a first resistor electrically coupled between a first output node of the driver stage and a power line; anda second inductor and a second resistor electrically coupled between a second output node of the driver stage and the power line; anda first level shifter electrically coupled with a first node between the first inductor and the first resistor and a second node between the second inductor and the second resistor,wherein a first output node of the first level shifter is electrically coupled with a first input node of the driver stage and a second output node of the first level shifter is electrically coupled with a second input node of the driver stage.

15. The I/O circuit of claim 14, wherein during a signal transition the first level shifter is operable to increase a current flowing through the first or second inductor.

16. The I/O circuit of claim 15, further comprising: a second level shifter electrically coupled with the first node between the first inductor and the first resistor and the second node between the second inductor and the second resistor,wherein a first output node of the second level shifter is electrically coupled with a first input node of the first level shifter and a second output node of the second level shifter is electrically coupled with a second input node of the first level shifter, and during the signal transition the second level shifter is operable to increase a current flowing through the first or second inductor.

17. The I/O circuit of claim 16, wherein during the signal transition a first current flows through the driver stage, a second current flows through the first level shifter, a third current flows through the second level shifter, and the first, second and third currents are substantially equal to each other.

18. The I/O circuit of claim 16, wherein during a steady state a current flowing through the first level shifter and the second level shifter is substantially zero.

19. The I/O circuit of claim 14, wherein the first and second ESD protection circuits each have a parasitic capacitance of about 400 femtofarads (fF) or more, and the first and second inductors each have an inductance of about 0.1 nanohenry (nH) or less.

20. The I/O circuit of claim 1, wherein the at least one pre-driver stage is operable to increase or induce a current flow through the at least one inductor.