Patent Application
20250149077
This application claims priority under 35 USC § 119 to Korean Patent Application Nos. 10-2023-0153033, filed on Nov. 7, 2023, and 10-2024-0022952, filed on Feb. 16, 2024, in the Korean Intellectual Property Office, the disclosures of which are herein incorporated by reference in their entirety.
Example embodiments relate to an input/output interface circuit and a memory system including the same.
Mobile communication devices are becoming increasingly commonplace and are evolving to provide enhanced user experiences. Applications and data for numerous functions of mobile communication devices are stored in a memory. Accordingly, there is an increasing demand for memory that consumes less power. In general, clock signals for memory operation are separately provided for each sub-channel. For this reason, interface elements for transmission and reception of clock signals are also provided for each sub-channel.
Example embodiments provide an input/output interface circuit for dividing a common clock signal for each sub-channel and a memory system including the same.
Provided herein is an input/output interface circuit including: a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal; and a pair of sub-channels connected to the common receiving driver, wherein: each sub-channel of the pair of sub-channels is configured to receive the first clock signal, a chip select signal, a second clock signal, a logical AND operation, a single clock signal, one or more divided clock signals, and a command address signal are separately defined for each sub-channel, each sub-channel is configured to receive the chip select signal, each sub-channel is configured to output the second clock signal through the logical AND operation of the first clock signal and the chip select signal to provide the single clock signal, wherein the single clock signal is provided from among: i) the second clock signal and ii) the one or more divided clock signals, wherein the one or more divided clock signals are divided from the second clock signal, and the single clock signal is configured to sample the command address signal.
Also provided herein is an input/output interface circuit including: a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal; and a first sub-channel and a second sub-channel connected to the common receiving driver, wherein: the first sub-channel is configured to receive the first clock signal and a first chip select signal, output a 2-1-th clock signal through a first logical AND operation of the first clock signal and the first chip select signal, output a first single clock signal provided from among: I) the 2-1-th block signal and ii) one or more first divided clock signals, wherein the one or more first divided clock signals are divided from the 2-1-th clock signal, and sample a first command address signal using the first single clock signal, and the second sub-channel is configured to receive the first clock signal and a second chip select signal, output a 2-2-th clock signal through a second logical AND operation of the first clock signal and the second chip select signal, and output a second single clock signal provided from among: I) the 2-2-th block signal and ii) one or more second divided clock signals, wherein the one or more first divided clock signals are divided from the 2-2-th block signal, and sample a second command address signal using the second single clock signal.
Also provided herein is a memory system including: a system-on-chip (SoC) including a first input/output interface circuit; and a memory device including a second input/output interface circuit communicating with the first input/output interface circuit, wherein the second input/output interface circuit includes: a common receiving driver configured to receive a differential clock signal through the first input/output interface circuit and output a first clock signal corresponding to the differential clock signal; and a pair of sub-channels connected to the common receiving driver, and each sub-channel of the pair of sub-channels is configured to receive the first clock signal through the common receiving driver, a chip select signal, a second clock signal, a logical AND operation, a single clock signal, one or more divided clock signals, and a command address signal are separately defined for each sub-channel, each sub-channel is configured to receive the chip select signal, each sub-channel is configured to output the second clock signal through the logical AND operation of the first clock signal and the chip select signal to provide the single clock signal, wherein the single clock signal is provided from among: i) the second clock signal and ii) the one or more divided clock signals, wherein the one or more divided clock signals are divided from the second clock signal, and the single clock signal is configured to sample the command address signal.
Hereinafter, example embodiments will be described with reference to the accompanying drawings.
Referring to
The processor 112 is a processing unit of a computing system for executing operating systems, applications, or the like, and may be regarded as a host in terms of the memory device 104. For example, the processor 112 may be implemented as a general-purpose processor, a specific-purpose processor, an AP, or the like. For example, the processor 112 may be implemented as an operation processor (for example, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), or the like) including a specific-purpose logic circuit (for example, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like), but example embodiments are not limited thereto.
The memory controller 114 may generate an access command for the memory device 104 in response to operations executed by the processor 112. The memory controller 114 may access the memory device 104 through the access command. The memory controller 114 may be connected to the memory device 104 through a plurality of channels including buses or signal lines. According to example embodiments, the memory controller 114 may be connected to the memory device 104 through a plurality of channels including a pair of sub-channels, and may transmit and receive data, commands, and addresses through the channels. A control operation of the memory controller 114 on the memory device 104 may be performed independently for each channel.
According to example embodiments, the memory controller 114 may manage both the pair of sub-channels as illustrated in the drawing, or a unit memory controller may be provided for a single sub-channel. For example, the memory controller 114 may be provided as a portion of the processor 112, and a logic for generating an access command of the memory controller 114 may be implemented on the same die or package space as the processor 112.
According to example embodiments, the memory controller 114 may include a first input/output interface circuit 116. The memory device 104 may include a second input/output interface circuit 118 corresponding to the first input/output interface circuit 116. The first input/output interface circuit 116 may include a pair of sub-channels and a clock interface circuit. The term “sub-channel” may be defined as a sub-channel included in each interface circuit and a sub-channel connected between input/output interface circuits. For ease of description, a sub-channel connected between input/output interface circuits will be defined as a sub-channel A, a pair of sub-channels included in the first input/output interface circuit 116 will be defined as a sub-channel B, and a pair of sub-channels included in the second input/output interface circuit 118 will be defined as a sub-channel C.
The input/output interface circuits 116 and 118 may include hardware or combinations thereof for connecting pins, pads, connectors, signal lines, wires, or other devices. The input/output interface circuits 116 and 118 may include one or more transmission drivers and receiving drivers (or transceivers) for each signal line.
According to example embodiments, the input/output interface circuits 116 and 118 may connect the memory controller 114 and the memory device 104 through signal lines. For example, the signal lines may include lines through which differential clock signals CK_T and CK_C are transmitted, lines through which command and address signals CA0 and CA1 are transmitted, lines through which write data DQ0 and read data DQ1 are transmitted, lines through which chip select signals CS0 and CS1 are transmitted, and other signal lines. Each of the lines may also be referred to as a bus. Among the signal lines, the lines through which the first data signal DQ0, the first write clock signal WCK0, the first command address signal CA0, and the first chip select signal CS0 are transmitted may be defined as a first sub-channel A SC0_A. The lines through which the second data signal DQ1, the second write clock signal WCK1, the second command address signal CA1, and the second chip select signal CS1 are transmitted may be defined as a second sub-channel A SC1_A.
Through each sub-channel A, data signals may be transmitted or received between the first input/output interface circuit 116 and the second input/output interface circuit 118, or the write clock signals WCK0 and WCK1, the command address signals CA0 and CA1, and the chip select signals CS0 and CS1 may be transmitted from the first input/output interface circuit 116 to the second input/output interface circuit 118.
The first input/output interface circuit 116 may include a pair of sub-channels (a first sub-channel B (SC0_B) and a second sub-channel B (SC1_B)) and a first clock interface circuit CKIC_A. The first sub-channel B (SC0_B) and the second sub-channel B (SC1_B) may be connected to a sub-channel on the side of the memory device 104 to transmit or receive the above-mentioned signals. The first clock interface circuit CKIC_A may be connected to the second clock interface circuit CKIC_B on the side of the memory device 104 to transmit the differential clock signals CK_T and CK_C to be commonly applied to the first sub-channel C (SC0_C) and the second sub-channel C (SC1_C) included in the memory device 104. According to example embodiments, the second clock interface circuit CKIC_B may include a common receiving driver and the first clock interface circuit CKIC_A may include a transmission driver corresponding to the common receiving driver.
The memory device 104 may be connected to the SoC 102 through a pair of sub-channels A and a differential clock signal line. The memory device 104 may be compatible with a general-purpose DRAM technology or standard such as a double data rate synchronous dynamic random access memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, or DDR5 SDRAM, a DRAM technology or standard for mobile application, such as a low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5 SDRAM, or LPDDR6 SDRAM, a DRAM technology or standard for providing high bandwidth, such as a graphics double data rate (GDDR) synchronous graphics random access memory (SGRAM), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, GDDR6 SGRAM, a high-bandwidth memory (HBM), HBM2, HBM3, or WideIO, or combinations of at least a portion thereof, or may be implemented based on the above-mentioned technologies or standards.
The memory device 104 may include a second input/output interface circuit 118, a plurality of memory cell arrays 120, a control logic circuit 122, and a plurality of registers 124.
The second input/output interface circuit 118 may be connected to the first input/output interface circuit 116 through the sub-channels A (SC0_A and SC1_A) and may include a pair of sub-channels (the first sub-channel C (SC0_C) and the second sub-channel C (SC1_C)) and a second clock interface circuit CKIC_B. The second clock interface circuit CKIC_B may convert the differential clock signals CK_T and CK_C, received from the memory controller 114, into common clock signals and transmit the common clock signals to the first sub-channel C (SC0_C) and the second sub-channel C (SC1_C). For example, each sub-channel may use the common clock signal.
The first sub-channel C (SC0_C) may include a clock divider 126, and the second sub-channel C (SC1_C) may include a clock divider 128. The clock dividers 126 and 128 may generate one or more divided clock signals divided from a clock signal common to sub-channels. Each divided clock signal may have a frequency required by each sub-channel. For example, the first sub-channel C (SC0_C) and the second sub-channel C (SC1_C) may receive a common clock signal from the second clock interface circuit CKIC_B, but may operate independently with different operating speeds by converting a frequency of the common clock signal into the frequency required by each sub-channel and using the converted frequency, through the clock dividers 126 and 128.
For example, when a relatively high-performance operation is required in the first sub-channel and a low-power operation is required in the second sub-channel, the first clock divider 126 may operate at the external CK input speed rather than dividing the common clock signal, and the second clock divider 128 may divide the common clock signal into a low frequency compared to the frequency required in the first sub-channel.
The plurality of memory cell arrays 120 may be accessed by each sub-channel (for example, the first sub-channel or the second sub-channel).
The control logic circuit 122 may include control logic to control an internal operation of the memory device 104. For example, the control logic circuit 122 may generate an internal operation to decode and execute a command transmitted by the memory controller 114. The control logic circuit 122 may determine which mode is selected, based on programmed setting or default setting represented by the registers 124, and may execute an operation depending on the mode.
The register 124 may be a storage device providing a configuration or setting for the memory device 104. The register 124 may be provided in singular or plural. For example, the registers 124 may include one or more mode registers. The mode register may set an operating mode of the memory device 104. According to example embodiments, the mode register may control the first sub-channel C (SC0_C) and the second sub-channel C (SC1_C) through a mode register write signal.
According to the above-described embodiments, the memory system 100 may have a structure, in which an input/output interface circuit included in the memory device 104 may distribute a clock signal, common to each sub-channel, to a sub-channel, and a structure in which a clock signal common to each sub-channel may be independently divided. Therefore, each sub-channel may operate with an independent frequency and operating speed even in a structure in which a clock signal is common.
Referring to
The pair of sub-channels SC0 and SC1 may be connected to the common receiving driver CRD. According to example embodiments, the pair of sub-channels SC0 and SC1 may each be configured to receive a first clock signal CK1 and chip select signals CS0 and CS1, output a second clock signal from a logical operation of the first clock signal CK1 and the chip select signals CS0 and CS1, and output a single clock signal, among a second clock signal and one or more divided clock signals divided from the second clock signal. The pair of sub-channels SC0 and SC1 may sample command address signals CA0 and CA1 based on the output single clock signal.
Except for the first clock signal CK1, each signal may be defined for each sub-channel. For example, the first chip select signal CS0, a 2-1-th clock signal CK2-1, and the first command address signal CA0 may be defined for the first sub-channel SC0, and the second chip select signal CS1, a 2-2-th clock signal CK2-2, and the second command address signal CA1 may be defined for the second sub-channel SC1.
According to example embodiments, the sub-channel SC0 may include a plurality of sub-channel drivers, a logic circuit 202, a clock divider 204, a multiplexer 206, a plurality of buffers 208 and 210, and a flip-flop FF1-1. A buffer may be implemented using logic gates. The sub-channel SC1 may include a plurality of sub-channel drivers, a logic circuit 212, a clock divider 214, a multiplexer 216, a plurality of buffers 218 and 220, and a flip-flop FF1-2. The plurality of sub-channel drivers may include first sub-channel drivers SD1-1 and SD1-2, respectively receiving chip select signals CS0 and CS1, and second sub-channel drivers SD2-1 and SD2-2, respectively receiving command address signals CA0 and CA1. An input terminal of each sub-channel driver may be connected to a signal line of
The logic circuits 202 and 212 may be connected to an output terminal of the common receiving driver CRD and output terminals of a plurality of sub-channel drivers. The logic circuit 202 and 212 may perform a logical operation on the first clock signal CK1 and the chip select signals CS0 and CS1. The logical operation may be defined as an operation of sampling the first clock signal CK1 depending on whether the chip select signals CS0 and CS1 are activated (or logic high (or logic low)). For example, the logical operation may be an AND operation, in which each of the logic circuits 202 and 212 may be implemented as an AND gate. As described above, it will be understood that when the first clock signal CK1 may be sampled based on the chip select signals CS0 and CS1, each of the logic circuits 202 and 212 may also be implemented as a logic gate to perform operations (for example, an NAND operation, or the like) other than the AND operation. Hereinafter, a clock signal processed by the logical operation through the logic circuits 202 and 212 may be defined as a second clock signal. The second clock signal may be defined as the 2-1-th clock signal CK2-1 for the first sub-channel SC0 and as the 2-2-th clock signal CK2-2 for the second sub-channel SC1.
The multiplexers 206 and 216 may select a single clock signal from among a second clock signal and one or more divided clock signals, based on a control signal. The first multiplexer 206 may be provided for the first sub-channel SC0, and the second multiplexer 216 may be provided for the second sub-channel SC1. According to example embodiments, the control signal may be a mode register write signal. For example, the mode register write signal may be provided from the register described above in
The multiplexer 206 and 216 may select a clock signal corresponding to a frequency required by each sub-channel based on the control signal. The undivided second clock signal may be selected through the multiplexers 206 and 216 or a divided clock signal may be selected, depending on the operating mode. The clock dividers 204 and 214 and the multiplexers 206 and 216 are independently provided for each sub-channel, so that sub-channel may operate at different frequencies through the multiplexers 206 and 216, respectively. For example, when a high-performance operation is required for the first sub-channel SC0, the first multiplexers 206 and 216 may select a clock signal corresponding to a higher frequency. In addition, when a lower-power operation is required for the second sub-channel SC1, the second multiplexers 206 and 216 may select a clock signal corresponding to a lower frequency.
As a result, the multiplexers 206 and 216 may select a single clock signal from among a plurality of clock signals (a basic clock signal and divided clock signals) generated from the clock dividers 204 and 214, to adjust a division factor 2N through the control signal.
Each sub-channel may include first buffers 208 and 218, connected between the multiplexers 206 and 216 and the flip-flops FF1-1 and FF1-2, and second buffers 210 and 220 connected between the second sub-channel drivers SD2-1 and SD2-2 and the flip-flops FF1-1 and FF1-2. A 1-1-th buffer 208 and a 2-1-th buffer 210 may be provided for the first sub-channel SC0, and a 2-1-th buffer 218 and a 2-2-th buffer 220 may be provided for the second sub-channel SC1. The first buffers 208 and 218 may buffer a single clock signal selected from the multiplexers 206 and 216, and transmit the buffered clock signal to clock gates of the flip-flops FF1-1 and FF1-2. The second buffers 210 and 220 may buffer the command address signals CA0 and CA1, and transmit the buffered common address signals CA0 and CA1 to the flip-flops FF1-1 and FF1-2. According to example embodiments, the first buffers 208 and 218 and the second buffer 210 and 220 may each be additionally provided in plural, or may be omitted.
The flip-flops FF1-1 and FF1-2 may store the command address signals CA0 and CA1 based on a single clock signal. The flip-flops FF1-1 and FF1-2 may store and output the command address signals CA0 and CA1 in synchronization with the single clock signal selected from the multiplexers 206 and 216. Unlike what is illustrated, the flip-flops FF1-1 and FF1-2 may be replaced with other storage elements that may perform a storage operation (or a delay operation) based on a clock signal.
According to the above-described embodiments, the input/output interface circuit may have a structure in which each sub-channel receives common differential clock signals CK_T and CK_C, but may independently divide and select the first clock signal CK1 corresponding to the differential clock signals CK_T and CK_C. Therefore, each sub-channel may be independently driven even when the clock signal is merged.
Referring to
Each unit divider may divide the clock signal such that the divided clock signal has a lower frequency than a divided clock signal output from a unit divider disposed at a previous end. For example, the first unit divider 302 may receive a second clock signal CK2 and output a clock signal CK2/2 divided by 2, and a second unit divider 304 connected to a first unit divider 302 may output a clock signal CK2/4 divided by 4 from the clock signal CK2/2 divided by 2. An Nth unit divider 306, disposed at a last terminal, may output a clock signal CK2/2N divided by 2N. According to the above-described embodiments, when a plurality of unit dividers is provided, a clock divider may provide a wider range of frequencies.
Referring to
Referring to
In the first sub-channel SC0, the first chip selects signal CS0 and the first clock signal CK1 received through the first-1 sub-channel driver SD1-1 may be input to the first AND gate 402. The first AND gate 402 may output the 2-1-th clock signal CK2-1 through a logical AND operation. The 2-1-th clock signal CK2-1 may be input to the first clock divider 404.
The first clock divider 404 may include a plurality of first unit dividers 405 to 407. The plurality of first unit dividers 405 to 407 may be connected sequentially. As illustrated in the drawing, the plurality of first unit dividers 405 to 407 may be implemented as flip-flops (for example, D flip-flops). For example, each of the plurality of first unit dividers 405 to 407 may have a form in which an inverted output terminal QB is connected to an input terminal D. Accordingly, each unit divider may output a clock signal, divided by 2, of a clock signal applied to a clock gate to an output terminal Q.
For example, the 1-1-th unit divider 405 may receive a 2-1-th clock signal CK2-1 through a clock gate and output a clock signal CK2-1/2, divided by 2, of the 2-1-th clock signal CK2-1, the 1-2-th unit divider 406 may receive the clock signal CK2-1/2, divided by 2, through the clock gate and output a clock signal CK2-1/4 divided by 4, and the 1-N-th unit divider 407 may output a clock signal CK2-1/2N divided by N.
The first multiplexer 408 may receive a first divided clock signal output from each first unit divider and output a single clock signal based on a first control signal CON1. For example, the first control signal CON1 may be a mode register write signal. The single clock signal selected by the first multiplexer 408 may be applied to a clock gate of a 1-1-th flip-flop FF1-1 through a 1-1-th buffer 410. The 1-1-th flip-flop FF1-1 may sample the first command address signal CA0 transmitted through a 2-1-th sub-channel driver SD2-1 and a 2-1-th buffer 412.
The second sub-channel SC1 may have the same configuration as the first sub-channel SC0. For example, in the second sub-channel SC1, the second chip select signal CS1 and the first clock signal CK1 received through a 1-2-th sub-channel driver SD1-2 may be input to a second AND gate 422. The second AND gate 422 may output a 2-2-th clock signal CK2-2 through a logical AND operation.
The second clock divider 424 may include a plurality of second unit dividers 425 to 427. For example, a 2-1-th unit divider 425 may receive a 2-2-th clock signal CK2-2 through a clock gate and output a clock signal CK2-2/2, divided by 2, of the 2-2-th clock signal CK2-2, a 2-2-th unit divider 426 may receive the clock signal CK2-2/2, divided by 2, through the clock gate and output a clock signal CK2-2/4 divided by 4, and a 2-N-th unit divider 427 may output a clock signal CK2-2/2N divided by N.
The second multiplexer 428 may receive a second divided clock signal output from each second unit divider and output a single clock signal based on a second control signal CON2. The single clock signal selected by the second multiplexer 428 may be applied to a clock gate of a 1-2-th flip-flop FF1-2 through a 1-2-th buffer 430. The 1-2-th flip-flop FF1-2 may sample the second command address signal CA1 transmitted through a 2-2-th sub-channel driver SD2-2 and a 2-2-th buffer 432.
As the first chip select signal CS0 and the second chip select signal CS1 are logically ANDed with the first clock signal CK1, the clock divider may be turned on or off by a chip select signal. Therefore, the input/output interface circuit 400 may turn off a clock divider, which is not operating, through the chip select signal to reduce power consumption. In addition, the input/output interface circuit 400 may independently divide the common first clock signal CK1 into appropriate-frequency signals through a clock divider and a multiplexer provided for each sub-channel.
Referring to
A first sub-channel driver SD1 may receive a chip select signal CS, and a second sub-channel driver SD2 may receive a command address signal CA. An output terminal of the first sub-channel driver SD1 may be connected to the first logic circuit 502, and the first logic circuit 502 may sample a first clock signal CK1 depending on whether the chip select signal CS is activated (or logic high (or logic low)) through a logical operation. A second clock signal CK2 may be output from a logic circuit and applied to the clock divider 504.
The clock divider 504 may generate one or more divided clock signals from the second clock signal CK2. The multiplexer 506 may select a single clock signal from among the second clock signal CK2 and one or more divided clock signals, and apply the selected clock signal to clock gates of the first flip-flop FF1 and the second flip-flop FF2.
The second sub-channel driver SD2 may receive the command address signal CA. The second logic circuit 512 may be connected to an output terminal of the second sub-channel driver SD2. The second logic circuit 512 may sample the command address signal CA signal depending on whether the chip select signal CS is activated (or logic high (or logic low)), similarly to the first logic circuit 502. For example, the second logic circuit 512 may be implemented as an AND gate that performs a logical AND operation, similarly to the first logic circuit 502.
An output terminal of the second logic circuit 512 may be connected to the first flip-flop FF1, and the first flip-flop FF1 may store the command address signal CA based on a single clock signal.
An output terminal of the first sub-channel driver SD1 may be connected to the second flip-flop FF2. The single clock signal selected by the multiplexer 506A may be applied to a clock gate of the second flip-flop FF2, and the second flip-flop FF2 may store the chip select signal CS based on the single clock signal. According to example embodiments, a replica delay cell 522 may be connected between the output terminal of the first sub-channel driver SD1 and the second flip-flop FF2. The replica delay cell 522 may be configured to add a delay to the chip select signal CS based on operations of the first logic circuit 502 and the second logic circuit 512 included in another path. A delay cell may be implemented using, for example, inverters and capacitors.
According to example embodiments, the sub-channel 500 may further include first to third buffer 508, 514, and 524 for signal buffering. The third buffer 524 may be connected between the replica delay cell 522 and the second flip-flop FF2 to buffer the chip select signal CS.
According to example embodiments, the configuration of the sub-channel of
According to the above-described embodiments, a sub-channel may sample the chip select signal CS and command address signal CA at an independent frequency using a divided clock signal from a clock signal common to each sub-channel.
Referring to
The 2-1-th clock signal CK2-1 may be used as a synchronization signal of a flip-flop (for example, the 1-1-th flip-flop of
The first command address signal CA0 may be sampled at a rising edge and a falling edge of the 2-1-th clock signal CK2-1, so that the first to fourth commands CMD1 to CMD4 may be sampled from times t2 to t7.
As described above, the second command address signal CA1 is sampled at the rising edge and the falling edge of the 2-2-th clock signal CK2-2. Therefore, the second command address signal CA1 may represent first to fourth commands CMD1 to CMD4 sequentially from time t1. The second command address signal CA1 is sampled through a clock signal of frequency divided by 2 compared to the first command address signal CA0, so that the time length of a single command may be doubled.
Referring to
A first chip select signal CS0 is at a high level in some periods, while the second chip select signal CS1 is at a low level in all periods. Therefore, all paths of a second sub-channel, including not only the second chip select signal CS1 but also a command address signal logically AND-ed with the second chip select signal CS1, may be turned off.
For example, similarly to
However, the second chip select signal CS1 corresponding to the second sub-channel is at a low level in all periods, so that the 2-2 clock signal CK2-2 and the second command address signal CA1 cannot be sampled. Therefore, a toggling component of the second sub-channel is not provided, which may save power consumption for the memory system.
According to example embodiments, the first sub-channel may be turned off and the second sub-channel may be turned on, unlike what is illustrated. In addition, all sub-channels may be turned off.
Referring to
A 1-1-th logic circuit 602 may perform a logical operation a first chip select signal CS0 received through a 1-1-th sub-channel driver SD1-1 and a first clock signal CK1 output from the common receiving driver CRD and transmit a result of the logical operation to a 1-1-th flip-flop FF1-1. A 1-2-th logic circuit 612 may perform a logical operation on a second chip select signal CS1 received through a 1-2-th sub-channel driver SD1-2 and a first clock signal CK1 and transmit a result of the logical operation to a 1-2-th flip-flop FF1-2. For example, a chip select signal may be used to select each sub-channel.
The 1-1-th flip-flop FF1-1 may store a first command address signal CA0 based on a 2-1-th clock signal CK2-1 output from a 1-1-th logic circuit 602, and the 1-2-th flip-flop FF1-2 may store a second command address signal CA1 based on a 2-2-th clock signal CK2-2 output from a 1-2-th logic circuit 612. According to example embodiments, the plurality of buffers 604, 606, 614, and 616 described above may be included in a path between a clock gate and an input terminal of each flip-flop.
According to the above-described embodiments, in terms of sub-channel, the first clock signal CK1 may be divided for each sub-channel through a common receiving driver CRD common to a sub-channel, rather than providing an additional receiving driver to receive differential clock signals CK_T and CK_C. The input/output interface circuit 600 on a transmission side (for example, the first input/output interface circuit of
In addition, any one sub-channel may be turned off depending on a chip select signal (for example, when a chip select signal applied to a logic circuit is at logic low), so that power consumption of an unused sub-channel may be significantly reduced.
In addition, the common receiving driver CRD may be implemented to reduce package pads caused by the driver. As a result, a chip area may be decreased.
Referring to
In an example embodiment, the system 700 may include a main processor 710, memories 720a to 720b, and storage devices 730a and 730b, and may further include at least one of an image capturing device 741, a user input device 742, a sensor 743, a communication device 744, a display 745, a speaker 746, a power supply device 747, and a connection interface 748.
The main processor 710 may control the overall operation of the system 700, for example, operations of other components included in the system 700. The main processor 710 may be implemented as a general-purpose processor, a specific-purpose processor, or an application processor.
The main processor 710 may include one or more cores 711, and may further include a controller 712 to control the memories 720a to 720b and/or the storage devices 730a and 730b. In an example embodiment, the main processor 710 may further include an accelerator, a specific-purpose circuit for high-speed data processing such as artificial intelligence (AI) data processing.
The memories 720a to 720b may be used as a main memory device of the system 700 and may include nonvolatile memories such as a static random access memory (SRAM) and/or a dynamic random access memory (DRAM). The memories 720a to 720b may be implemented within the same package as the main processor 710. According to example embodiments, each of the memories 720a to 720b may include a first sub-channel SC0, a second sub-channel SC1, and a clock interface circuit CKIC according to the above-described embodiments (
Each of the storage devices 730a and 730b may function as a nonvolatile storage device storing data regardless of whether power is supplied, and may have relatively large storage capacity compared to the memory. The storage devices 730a and 730b may include storage controllers 731a and 731b and nonvolatile memories (NVMs) 732a and 732b storing data under the control of the storage controllers 731a and 731b, respectively. The NVMs 732a and 732b may include a flash memory having a two-dimensional (2D) structure or a three-dimensional vertical NAND (3D V-NAND) structure, but may include other types of nonvolatile memory such as a phase-change RAM (PRAM) and/or a resistive RAM (RRAM).
The storage devices 730a and 730b may be included in the system 700 while being physically separated from the main processor 710, or may be implemented in the same package as the main processor 710. In addition, each of the storage devices 730a and 730b may be in the form of a solid-state drive (SSD) or a memory card to be removably coupled to other components of the system 700 through an interface such as a connection interface 748 to be described later. Each of the storage devices 730a and 730b may be a device to which the standard protocol is applied, such as such as a universal flash storage (UFS), an embedded multimedia card (eMMC), or a nonvolatile memory express (NVMe), but example embodiments are not limited thereto.
The image capturing device 741 may capture still images or videos and may be a camera, a camcorder, and/or a webcam.
The user input device 742 may receive various types of data input from a user of the system 700, and may be a touchpad, a keypad, a keyboard, a mouse, and/or a microphone.
The sensor 743 may detect various types of physical quantities that may be obtained from the outside of the system 700, and may convert the detected physical quantities into electrical signals. The sensor 743 may include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.
The communication device 744 may transmit and receive signals between other devices outside the system 700 based on various communication protocols. The communication device 744 may be implemented to include an antenna, a transceiver, and/or a modem.
The display 745 and speaker 746 may function as output devices to output visual information and auditory information to the user of the system 700, respectively.
The power supply device 747 may appropriately convert power supplied from an internal battery, not illustrated, and/or external power, and may supply the converted power to each component of the system 700.
The connection interface 748 may provide a connection between the system 700 and an external device connected to the system 700 to exchange data with the system 700. The connection interface 748 may be implemented in various interface schemes such as an advanced technology attachment (ATA), a serial ATA (SATA), an external SATA (e-SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnect (PCI), a PCI express (PCIe), an NVMe, an IEEE 1394, a universal serial bus (USB), a secure digital (SD) card interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a universal flash storage (UFS) interface, an embedded UFS (eUFS) interface, or a compact flash (CF) card interface.
The system according to the above-described embodiments may operate at low power using the memories 720a to 720b that may independently divide the frequency of a common clock signal for each sub-channel.
As set forth above, according to example embodiments, an input/output interface circuit for dividing a common clock signal for each sub-channel and a memory system including the same may be provided.
While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0153033 | Nov 2023 | KR | national |
| 10-2024-0022952 | Feb 2024 | KR | national |
