Instruction Processing Method and Graphflow Apparatus

Abstract

A graphflow apparatus includes an information buffer (IB) and a load queue (LQ). The IB is configured to cache an instruction queue. The LQ is used to cache a read instruction queue. The IB includes a speculative bit and a speculative identity (ID) field. The speculative bit indicates whether a current instruction is a speculatively-executable instruction. The speculative ID field stores a speculative ID of one speculative operation on the current instruction.

Description

Claims

1. A method implemented by a graphflow apparatus wherein the method comprises: issuing, by an information buffer (IB) of one or more process engines(PEs) of the graphflow apparatus, a first instruction to a load queue (LQ) of a load store unit (LSU) of the graphflow apparatus, wherein the first instruction requests to read data and satisfies a first preset condition, wherein the first preset condition comprises a speculative bit of the first instruction in the IB being set to “yes”, and wherein the speculative bit indicates whether the first instruction is aspeculatively-executable instruction;determining, by the IB, a first speculative identity (ID) indicating a current speculative operation, andstoring, by the IB, the first speculative ID in a first speculative ID field of the first instruction.

2. The method of claim 1, wherein the LQ comprises the first speculative ID field, and wherein the method further comprises: after issuing the first instruction to the LQ: assigning, by the LQ, the first speculative ID to the first instruction;writing, by the LQ, the first speculative ID into a second speculative ID field of the first instruction in the LQ; andsending, by the LQ, the first speculative ID to the IB; and receiving, by the IB, the first speculative ID from the LQ.

3. The method of claim 2, wherein the first speculative ID is a one-hot code.

4. The method of claim 1, further comprising: searching, by the LQ based on the first instruction, a store buffer (SB) or a memory for the data, andobtaining, by the LQ, the data from the SB or the memory.

5. The method of claim 4, further comprising transmitting, by the LQ, the first speculative ID to a second speculative ID field of a second instruction in the IB, wherein the second instruction is based on the first instruction.

6. The method claim 1, wherein after issuing the first instruction, the method further comprises setting, by the IB, a speculative flag bit of the first instruction in the IB to “yes,” and wherein the speculative flag bit indicates whether the first instruction has been speculatively issued.

7. The method of claim 1, further comprising: obtaining, by the LQ, the data:issuing, by the IB after obtaining the data, a second instruction based on the first instruction; andsetting, by the IB after issuing the second instruction, a speculative flag bit of the second instruction in the IB to “yes,” wherein the speculative flag bit indicates whether the first instruction has been speculatively issued.

8. The method of claim 1, wherein the first preset condition further comprises: a dependence validity bit of the first instruction is set to “yes” wherein the dependence validity bit indicates whether the first instruction is executed after execution of a second instruction is completed; anda dependence presence bit in the IB is set to “no”, wherein the dependence presence bit indicates whether execution of the second instruction on which the first instruction is dependent is completed.

9. The method of claim 1, further comprising: issuing, by the IB after issuing the first instruction, a second instruction to a store buffer (SB) of the LSU, wherein the second instruction is a storage instruction, wherein the first instruction and the second instruction satisfy a second preset condition, wherein the second preset condition comprises that the first instruction follows the second instruction in an ideal execution sequence, wherein the first instruction comprises a memory dependence relationship with the second instruction, and wherein the memory dependence relationship indicates an existing sequential dependence relationship between access instructions due to operations on a same address; andsending, by the IB, a storage address of the second instruction to the LQ.

10. An apparatus comprising: one or more process engines (PEs), wherein each of the one or more PEs is configured to comprise: an information buffer (IB) configured to cache an instruction queue, wherein the IB comprise: a first speculative bit indicating whether a current instruction is a speculatively-executable instruction; anda first speculative identity (ID) field storing a first speculative ID of a speculative operation on the current instruction; anda load store unit (LSU) coupled to the IB and comprising a load queue (LQ) configured to cache a read instruction queue.

11. The apparatus of claim 10, wherein the speculative ID is a one-hot code.

12. The apparatus of claim 10, wherein the IB is configured to: issue, to the LQ, a first instruction requesting to read data, wherein the first instruction satisfies a first preset condition, and wherein the first preset condition comprises a second speculative bit of the first instruction in the IB is set to “yes”determine a second speculative ID indicating a curent speculative operation; andstore the first speculative ID in a second speculative ID field of the first instruction .

13. The apparatus of claim 12, wherein the LQ is further configured to: after issuing the first instruction to the LQ. assign the first speculative ID to the first instruction;write the first speculative ID into a second speculative ID field of the first instruction in the LQ; andsend the first speculative ID to the IB,whereing the IB is further configured to receive the first speculative ID from the LQ.

14. The apparatus of claim 12, wherein the LQ is further configured to: search, based on the first instruction, a store buffer (SB) or a memory for the data; andobtain the data from the SB or the memory.

15. The apparatus of claim 14, wherein the LQ is further configured to transmit the first speculative ID to a second speculative ID field of a second instruction in the IB, and wherein the second instruction is based on the first instruction.

16. The apparatus of claim 10, wherein the IB further comprises a first speculative flag bit indicating whether the current instruction has been speculatively issued.

17. The apparatus of claim 16, wherein after issuing a first instruction, the IB is further configured to set a second speculative flag bit of the first instruction to “yes”.

18. The apparatus of claim 12, wherein the IB is further configured to: issue, after obtaining the data, a second instruction that is based on the first instruction; andset, after issuing the second instruction, a third speculative flag bit of the second instruction to “yes”, wherein the third speculative flag bit indicates whether the first instruction has been speculatively issued.

19. A computer program product comprising computer-executable instructions that are stored on a non-transitory computer storage medium and that, when executed by one or more processors, cause an apparatus to: issue, using an information buffer (IB) of one or more process engines (PEs) of the apparatus, an instruction to a load queue (LQ) of a load store unit (LSU) of the apparatus, wherein the instruction requests to read data and satisfies a preset condition, wherein the preset condition comprises a speculative bit of first instruction in the IB being set to “yes”, and wherein the speculative bit indicates whether the first instruction is a speculatively-executable instruction;determine, using the IB, a speculative identity (ID) indicating a current speculative operation, andstoring, by, the IB, the speculative ID in a speculative ID field of the first instruction in the IB.

20. The computer program product of claim 19, wherein the speculative ID is a one-hot code.