Patent Application
20150277906
Arbitrary waveform generators (AWGs) are devices that produce analog waveforms by converting a stored digital representation of a waveform into an analog output through a digital-to-analog converter (DAC). This gives AWGs considerably more flexibility than function generators, which may produce a small number of pre-computed waveforms such as sine, sawtooth, triangle, and square waves. Nonetheless, practical considerations of transfer time and memory size still limit the duration and complexity of the output waveforms of an AWG. Consequently, engineers have added limited sequencing capabilities to AWGs to allow playback of more complex waveforms by stitching together smaller components. This allows for re-use of component waveforms many times such that the final output is of longer duration than what could be directly stored in the AWG memory. It also reduces transfer of redundant information.
Sequencing typically involves construction of a sequence table, which defines the order in which waveforms are played along with arbitrary control flow instructions. In existing AWGs, these control-flow instructions are limited to repeated waveforms (basic looping) and non-conditional goto statements to jump to other sections of the waveform table. Rudimentary conditional elements may be implemented with event triggers to conditionally jump to an address in the waveform table upon receipt of an external trigger. This capability enables branching into the sequence table. Memory may be re-used using the concept of subsequences which allow for jumping to sections of the waveform table and then returning to the jump point in a manner similar to a subroutine or function call in a programming language.
Existing AWGs are limited in several ways. First, previous implementations have not allowed arbitrary combinations of control-flow constructs. For instance, any control-flow instruction may be conditional, so that, for example, subsequence execution could depend on external inputs. Alternatively, recursive control-flow structures may be constructed, i.e. nested subsequences may be possible. Second, event triggers are not sufficiently expressive to choose between branches of more than two paths. With wider, multi-bit input interfaces, higher-order branches may be constructed, e.g., with a 2-bit input you could have four choices.
Some applications require a low-latency conditional response to external information. One such application is quantum error correction, where the control systems apply a correction operation (a pulse) upon receipt of an error signal. It is expected that future quantum information processors will spend the majority of their execution time correcting errors. Consequently, the latency of the error correction step directly translates into the effective clock speed of such devices. The testing of high-speed communications protocols also involves sequences (i.e. symbols) that are chosen depending on interactions between the sender and receiver.
Low-latency applications place additional demands on branching AWGs because jumping between distant addresses in dynamic random access memory (DRAM) is subject to significant latency.
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass available equivalents of those claims.
Test equipment applications involve signal stimuli varying from advanced communication signals to the playback of captured real-world analog signals. Signal source instruments generate the signal stimulus that is applied to a device under test (DUT). Consequently, signal sources comprise a class of test instruments.
Embodiments described herein satisfy the demands of long sequences and low-latency by adding a cache hierarchy into the AWG memory structure. Moreover, embodiments described herein provide a complete instruction set for arbitrary control flow, wherein the arbitrary control flow instruction set provides for loops, conditional execution, and subroutine structures. Consequently, arbitrary control flow may be provided that allows flexible sequence design.
Waveform sequences provide a mechanism to piece together specified or arbitrary waveforms in stages to create user-defined compound waveforms. Typically, a waveform library 102 provides the waveform data 110, 112, 114 used in the stages 140, 142, 144 of the waveform sequence. Waveform data 110, 112, 114 in the library 102 are reused and looped in a sequence to provide the flexibility to create long waveform sequences 150. The generation of the arbitrary waveforms will be described below.
The processed waveform data may be converted into an analog signal using a digital-to-analog converter (DAC) 220. The analog signal may be filtered by an analog output circuit 230, which may include an amplifier, an attenuator, a switch, a reconstruction filter, etc. The filtered analog signal may then be applied to a DUT 240.
An instruction set, and related system design involves segmenting AWG system memory 310 into two types, e.g., a waveform memory 312 and an instruction memory 314. In addition, an AWG according to an embodiment has four other resources available for managing the execution of the arbitrary control flow instruction set. Control registers 320 includes an instruction counter 322, a repeat counter 324 and a comparison register 326. A stack 330 is provided for returning to the current instruction and restoring state after calling a subroutine.
In
From Table 1, the available instructions includes CMP operator N, WAVEFORM address length, TA-WAVEFORM amplitude length, LOAD count, REPEAT address, GOTO address, CALL address, RETURN and PREFETCH address. GOTO, CALL and RETURN may have conditional versions which depend on the result of the most recent comparison (CMP) operator. CMP-Compares the value of the comparison register to N with any of these operators: =, ≠, >, <. So, (CMP≠0) would be true if the comparison register contains any value other than zero.
WAVEFORM address length indicates that the AWG should play back length N data points starting at the given waveform memory address. TA-WAVEFORM indicates that the AWG should play back length a constant waveform of N points with the specified amplitude.
The LOAD instruction loads the given value into the repeat counter. The REPEAT instruction decrements the repeat counters. If the resulting value is greater than zero, jumps are made to the given instruction address by updating the instruction counter. The GOTO instructions jumps to the given address by updating the instruction counter. The conditional version jumps if the prior CMP operator is true.
The CALL instruction pushes the current instruction counter onto the stack, and then jumps to the given address by updating the instruction counter. The conditional version jumps if the prior CMP operator is true. The RETURN instruction moves the top value on the stack to the instruction counter and jumps back to the instruction after the most recent CALL instruction. The conditional version jumps if the prior CMP operator is true. The PREFETCH instruction loads the sequence or waveform data at address into the cache.
These instructions easily facilitate two kinds of looping: iteration and while loops. The former is achieved through use of LOAD to set the value of the repeat counter, followed by the loop body, and terminated by REPEAT to jump back to the beginning of the loop. The latter is achieved by bookending the loop body with conditional GOTO statements that jump to the instruction following the loop.
Subroutines are implemented with the CALL and RETURN instructions. The address of a CALL instruction can indicate the first instruction in instruction memory of a subroutine. The subroutine may have multiple exit points, which may be marked by a RETURN instruction.
Conditional execution is directly supported by the conditional GOTO, CALL, and RETURN. Consequently, the stated instruction set may be used for arbitrary control flow.
PREFETCH helps to reduce latency from branching operations by loading data into a lower-latency domain at a predetermined time (rather than waiting for a cache miss). Instruction and waveform caching are described below.
According to an embodiment, an instruction set for AWGs provide more than a monolithic very wide instruction. Previous AWGs have only supported an instruction that tries to specify everything: waveform address and length, number of times to repeat the waveform, instruction address to jump to upon completion, and instruction address to jump to if a trigger event occurs. Limitations of existing hardware suggest that implementations of subroutines are really a software feature, and that subsequences are inlined, i.e., copied, in the AWG instruction memory.
Low-latency applications place additional demands on branching AWGs because jumping between distant addresses in dynamic random access memory (DRAM) is subject to significant latency. According to an embodiment, an AWG with multi-level memory caching, is provided to reduce memory latency by caching data in a higher speed memory before accessing a large DRAM. The System Memory is segmented into high and low latency domains.
As data, both instruction and waveform data are written into the system 400 by the cache controller 450 according to memory requests 460. The data type is indicated by the memory address. It is also possible to flag data to be pre-copied to the instruction memory 442 or waveform memory 444 of the low-latency domain 440 to ensure it is available immediately in the low latency domain 440, e.g., waveforms used for the inner loop of an arbitrary control flow structure.
After a write, a small number of instructions and waveform data points are read from the high latency domain 410 into their respective low-latency caches, e.g., instruction cache 442 and waveform cache 444. Memory reads 450 are serviced by the low-latency cache 440 when the requested address is stored in the cache, otherwise the cache is updated from the high latency domain 410.
According to an embodiment, the instruction cache 442 may include mechanisms that predict which instructions or waveforms may be accessed next in order to decrease the likelihood of a cache miss. An example mechanism may predict that 1) the subsequent instruction after the current one is the most likely to be requested next, and that 2) jumps in sequence memory are likely to be short, so that the distance between requested entries is likely to be small (this is often the case for loops). A cache structure that may facilitate both of these heuristics is a circular buffer centered on the current address of the instruction counter. In this structure, the addresses in the instruction cache may range from instructionCounter−cacheSize/2 to instructionCounter+cacheSize/2. When the instruction counter increments, the cache controller will read in one new instruction at instructionCounter+cacheSize/2 from the high latency domain 410. The high-latency read of the instruction will not impact program flow provided that the execution time of the current instruction, e.g., waveform playback, is longer than the read latency from the high latency domain 410. In the event of an instruction counter jump, forward or back, instructions are read from the high latency instruction memory 412 into the instruction cache 442 to re-center the buffer.
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments that may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements in addition to those shown or described. However, also contemplated are examples that include the elements shown or described. Moreover, also contemplated are examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
Publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) are supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to suggest a numerical order for their objects.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with others. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is to allow the reader to quickly ascertain the nature of the technical disclosure, for example, to comply with 37 C.F.R. §1.72(b) in the United States of America. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. However, the claims may not set forth features disclosed herein because embodiments may include a subset of said features. Further, embodiments may include fewer features than those disclosed in a particular example. Thus, the following claims are hereby incorporated into the Detailed Description, with a claim standing on its own as a separate embodiment. The scope of the embodiments disclosed herein is to be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
This case is a subject invention under government Contract No. C12J11269. The government has certain rights in this invention.
