Patent Application
20080059764
An Integral Parallel Machine (IPM) incorporates data parallelism, time parallelism and speculative parallelism but separates or segregates each. In particular, data parallelism and time parallelism are separated with speculative parallelism in each. The mixture of the different kinds of parallelism is useful in cases that require multiple kinds of parallelism for efficient processing.
An example of an application for which the different kinds of parallelism are required but are preferably separated is a sequential function. Some functions are pure sequential functions such as f(h(x)). The important aspect of a pure sequential function is that it is impossible to compute f before computing h since f is reliant on h. For such functions, time parallelism can be used to enhance efficiency which becomes very crucial. By understanding that it is possible to turn a sequential pipe into a parallel processor, a pipeline of sequential machines can be used to compute sequential functions very efficiently.
For example, two machines in sequence are used to compute f(h(x)). The machines include a first machine computing h is coupled to a second machine computing f. A stream of operands, x1, x2, . . . xn, is processed such that h(x1) is processed by the first machine while the second machine computing f performs no operation in the first clock cycle. Then, in the second clock cycle, h(x2) is processed by the first machine, and f(h(x1)) is processed by the second machine. In the third clock cycle, h(x3) is processed while f(h(x2)) is processed. The process continues until f(h(xn)) is computed. Thus, aside from a small latency required to fill the pipeline (a latency of two in the above example), the pipeline is able to perform computations in parallel for a sequential function and produce a result in each clock cycle, thereafter.
For a set of sequential machines to work properly as a parallel machine, the set preferably functions without interruption. Therefore, when confronted with a situation such as:
c=c[0]?c+(a+b):c+(a−b),
not only is time parallelism important but speculative parallelism is as well. The code above is interpreted to mean that if a Least Significant Bit (LSB) of c is 1, then set c equal to c+(a+b), but if the LSB of c is 0, then set c equal to c+ (a−b). Typically, the value of c is determined first to find out if it is a 0 or 1, and then depending on the value of c, b would either be added to a, or b would be subtracted from a. However, by performing the functions in such an order would cause an interruption in the process as there would be a delay waiting to determine the value of c to determine which branch to take. This is not an efficient to parallel system. If clock cycles are wasted waiting for a result, the system is no longer functioning in parallel at that point. The solution to this problem is referred to as speculative parallelism. Both a+b and a−b are calculated by a machine in the set of machines, and then the value of c is used to select the proper result after they are both computed. Thus, there is no time spent waiting, and the sequence continues to be processed in parallel.
To implement a sequential pipeline to perform computations in parallel, each processing element in a sequential pipeline is able to take data from any of the previous processing elements. Therefore, going back to the example of using c[0] to determine a+b or a−b, in a sequence of processing elements, a first processing element stores the data of c[0]. A second processing element computes c+(a+b). A third processing element computes c+(a−b). A fourth processing element takes the proper value from either the second or third processing element depending on the value of c[0]. Thus, the second and third processing elements are able to utilize the information received from the first processing element to perform their computations. Furthermore, the fourth processing element is able to utilize information from the second and third processing elements to make its computation or selection.
To select previous processing elements, preferably a selector/multiplexer is used, although in some embodiments, other mechanisms are implemented. In an alternative embodiment, a file register is used. Preferably, it is possible to choose from 8 previous processing elements, although fewer or more processing elements are possible.
The following is a description of the components of the IPM. A memory is used to store data and programs and to organize interface buffers between all sub-systems. Preferably, a portion of the memory is on chip, and a portion of it is on external RAM. An input-output system includes general purpose interfaces and, if desired, application specific interfaces. A host is one or more general purpose controllers used to control the interaction with the external world or to run sequential operations that are neither data intensive nor time intensive. A data parallel system is an array of processing elements interconnected by a simple network. A time parallel system with speculative capabilities is a dynamically reconfigurable pipe of processing elements. In each clock cycle, new data is inserted into the pipe of processing elements. In a pipe with n blocks, it is possible to do n computations in parallel. As described above there is an initial latency, but with a large amount of data, the latency is negligible. After the latency period, each clock cycle produces a single result.
The IPM is a “data-centric” design. This is in contrast with most general purpose high-performance sequential machines, which tend to be “program-centric.” The IPM is organized around the memory in order to have maximum flexibility in partitioning the overall computation into tasks performed by different complementary resources. P
The data parallel system 104 is an array of processing elements interconnected by a simple network. The data parallel system 104 issues, in each clock cycle, an instruction. The instruction is broadcast into the array for performing a function. The data parallel system 104 is described further in U.S. Pat. No. 7,107,478, entitled DATA PROCESSING SYSTEM HAVING A CARTESIAN CONTROLLER, and U.S. Patent Publ. No. 2004/0123071, entitled CELLULAR ENGINE FOR A DATA PROCESSING SYSTEM, which are hereby incorporated by reference in their entirety.
The time parallel system 106 is a dynamically reconfigurable pipe of processing elements. Each processing element in the data parallel system 104 and the time parallel system 106 is individually programmable.
The memory 114 is used to store data and programs and to organize interface buffers between all of the sub-systems. The I/O system 112 includes general purpose interfaces and, if desired, application specific interfaces. The host 110 is one or more general purpose controllers used to control the interaction with the external world or to run sequential operations that are neither data intensive nor time intensive.
As described above, each processing element 300 is able to be configured to perform a specified function. Information, such as a stream of data, enters the time parallel system 106 at the first processing element, PE1, and is processed in a first clock cycle. In a second clock cycle, the result of PE1 is sent to PE2, and PE2 performs a function on the result while PE1 receives new data and performs a function on the new data. The process continues until the data is processed by each processing element. Final results are obtained after the data is processed by PEn.
Within the data parallel system several design elements are preferred. Strong data locality of the algorithms allows processing elements to be coupled in a compact linear array with nearest neighbor connections. The number of 16-bit processing elements is preferably between 256 and 1024. Each processing element contains a 16-bit ALU, an 8-word register file, a 256-word data memory and a boolean machine with an associated 8-bit state register. Since cycle operations are add and subtract on 16-bit integers, a small number of additional single-clock instructions support efficient (multi-cycle) multiplication. The I/O is a 2-D network of shift registers with one register per processing element. Two or more independent (stack-based) instruction sequencers including one or more 32-bit instruction sequencers that sequence arithmetic and logic instructions into the array of processing elements and a 32/128-bit stack-based I/O controller (or “Smart-DMA”) are used to transfer data between an I/O plan and the rest of the system which results in a Single Instruction Multiple Data (SIMD)-like machine for one instruction sequencer or a Multiple Instruction Multiple Data (MIMD) of SIMD machine for more than one instruction register. A Smart-DMA and the instruction sequencer communicate with each other using interrupts. Data exchange between the array of the processing elements and the I/O is executed in one clock cycle and is synchronized using a sequence of interrupts specific to each kind of transfer. An instruction sequencer instruction is conditionally executed in each processing element depending on a boolean test of the appropriate bit in the state register.
The time parallel system includes a dynamically reconfigurable pipeline of n processing elements. The value of n preferably falls within the range of 8 and 63, and the pipeline can reshape dynamically into a logical “cross” configuration as described above.
To utilize the present invention, an integral parallel machine includes a data parallel system and a time parallel system which both are capable of implementing speculative parallelism. The time parallel system receives data input from a memory and performs processing in a pipeline where each processing element performs a function after receiving a result from one of the previous processing elements. The time parallel system then sends the computed results to the data parallel system for further computation. The time parallel system can send data to the data parallel system as well.
In operation, the present invention is able to be used independently or as an accelerator for a standard computing device. By separating data parallelism and time parallelism, processing data with certain conditions is improved. Specifically, large quantities of data such as video processing benefit from the present invention.
Although single pipelines have been illustrated and described above, multiple pipelines are possible. For multiple bitwise data, multiple stacks of these columns or pipelines of processing elements are used. For example, for 16 bitwise data, 16 columns of processing elements are used.
Additionally, although it is described that each processing element produces a result in one clock cycle, it is possible for each processing element to produce a result in any number of clock cycles such as 4 or 8.
There are many uses for the present invention, in particular where large amounts of data is processed. The present invention is very efficient when processing long streams of data such as in graphics and video processing, for example HDTV and HD-DVD.
The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be readily apparent to one skilled in the art that other various modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the invention as defined by the claims.
This Patent Application claims priority under 35 U.S.C. §119(e) of the co-pending, co-owned U.S. Provisional Patent Application No. 60/841,888, filed Sep. 1, 2006, and entitled “INTEGRAL PARALLEL COMPUTATION” which is also hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 60841888 | Sep 2006 | US |
