This application is related to and incorporates herein by reference pending U.S. application Ser. No. 09/525,184 titled “STANDARD BLOCK Architecture For Integrated Circuit Design,” filed Mar. 14, 2000, which is assigned to the assignee of the present application.
Number | Name | Date | Kind |
---|---|---|---|
4964057 | Yabe | Oct 1990 | A |
5047949 | Yamaguchi et al. | Sep 1991 | A |
5206815 | Purcell | Apr 1993 | A |
5227665 | Nakamura et al. | Jul 1993 | A |
5369596 | Tomkumaru | Nov 1994 | A |
5459673 | Carmean et al. | Oct 1995 | A |
5471398 | Stephens | Nov 1995 | A |
5495419 | Rostoker et al. | Feb 1996 | A |
5581475 | Majors | Dec 1996 | A |
5636129 | Her | Jun 1997 | A |
5696693 | Aubel et al. | Dec 1997 | A |
5723883 | Gheewalla | Mar 1998 | A |
5757656 | Hershberger et al. | May 1998 | A |
5847969 | Miller et al. | Dec 1998 | A |
5872718 | Scepanovic et al. | Feb 1999 | A |
5892688 | Scepanovic et al. | Apr 1999 | A |
5898597 | Scepanovic et al. | Apr 1999 | A |
5905655 | Deeley | May 1999 | A |
5923059 | Gheewala | Jul 1999 | A |
5923060 | Gheewala | Jul 1999 | A |
5984510 | Guruswamy et al. | Nov 1999 | A |
5987086 | Raman et al. | Nov 1999 | A |
6006024 | Guruswamy et al. | Dec 1999 | A |
6067409 | Scepanovic et al. | May 2000 | A |
6110221 | Pai et al. | Aug 2000 | A |
6223329 | Ling et al. | Apr 2001 | B1 |
6230304 | Groeneveld et al. | May 2001 | B1 |
6230308 | Granzelmi et al. | May 2001 | B1 |
6269466 | Crafts | Jul 2001 | B1 |
6298468 | Zhen | Oct 2001 | B1 |
6308309 | Gan et al. | Oct 2001 | B1 |
Number | Date | Country |
---|---|---|
0599469 | Jun 1994 | EP |
08258993 | Sep 1996 | EP |
0848342 | Jun 1998 | EP |
10107614 | Apr 1998 | JP |
WO9952049 | Oct 1999 | WO |
Entry |
---|
Synopsis, Design Compiler Family Reference Manual, Version 3.3a, Mar. 1995, Table of Contents. |
Semiconductor Industry Association, SIA Technology Programs, ASIC/SOC Presentation, Sep. 17, 1999 by Dr. Juri Matisoo |
Synopsis, Experiences Using Behavioral Synthesis on an ATM Traffic & Queue Management ASIC, www.synopsys.com/products/beh_syn/bc_nortel_wp.html. |
Synopsis, Behavioral and RTL Synthesis, 1998, www.synopsys.com/products/beh_syn/what_is.gif. |
Avant!, Single Pass RTL Design, 1999, ftp.interhdl.com/Avant!/SolutionsProducts/SinglePassRTLDesign/Index/. |
Synopsis, Synopsis Delivers Industry's First Register-Transfer-Level Optimization for Power Synthesis, Nov. 3, 1997, www.synopsys.com/news/announce/press/rtl_power_pr.html. |
ASIC Design, asic.heltech.com/asdcnts.htm. |
EDA Direct, XHDL, www.edadirect.com/XHDL.htm. |
IEEE 1076.6 VHDL Synthesis Standard Passes Balloting, 1999, www/vhdl.org/vhdltimes/73-ieee.html. |
Modeling Layout Tools to Derive Forward Estimates of Area and Delay at the RTL Level, by Donald S. Gelosh, www.acm.org/todaes/V6N2/L146/abstract.html. |
Avant!, IC Packaging and System Products, 1999, www.interhdl.com/Avant!/SolutionsProducts/Category/Item/1,1299,6,00.html. |
Synopsys, Desktop Verilog, www.synopsys.com/services/education/desk_verilog_tr.html. |
Cadence Design Tools Tutorial, vlsi.wpi.edu/courses/ee390x/flow.html. |