Integrated circuit device and electronic instrument

Abstract

A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1A, 1B, and IC are illustrative of a comparative example of one embodiment of the invention.

FIGS. 2A and 2B are illustrative of mounting of an integrated circuit device.

FIG. 3 is a configuration example of an integrated circuit device according to one embodiment of the invention.

FIG. 4 is an example of various types of display drivers and circuit blocks provided in the display drivers.

FIGS. 5A and 5B are planar layout examples of the integrated circuit device according to one embodiment of the invention.

FIGS. 6A and 6B are examples of cross-sectional views of the integrated circuit device.

FIG. 7 is a circuit configuration example of the integrated circuit device.

FIGS. 8A, 8B, and 8C are illustrative of configuration examples of a data driver and a scan driver.

FIGS. 9A and 9B are configuration examples of a power supply circuit and a grayscale voltage generation circuit.

FIGS. 10A, 10B, and 10C are configuration examples of a D/A conversion circuit and an output circuit.

FIG. 11 is a view showing a pad and an electrostatic discharge protection element which protects the pad.

FIG. 12 is a view showing a macrocell of pads, a memory, and a data driver.

FIG. 13 is a view showing a planar layout of output pads of a data driver and electrostatic discharge protection elements formed in a lower layer of the output pads.

FIG. 14 is a schematic view showing connection of the pads and the electrostatic discharge protection elements shown in FIG. 13.

FIG. 15 is a cross-sectional view along the line XV-XV in FIG. 13.

FIG. 16 is a cross-sectional view along the line XVI-XVI in FIG. 13.

FIGS. 17A and 17B are views illustrative of detection of bit output data.

FIG. 18 is a view illustrative of a bitline shield layer in a RAM region.

FIG. 19 is a view showing a planar layout of output pads of a scan driver and electrostatic discharge protection elements formed in a lower layer of the output pads.

FIG. 20 is a schematic view showing connection of the pads and the electrostatic discharge protection elements shown in FIG. 19.

FIG. 21 is a cross-sectional view along the line XXI-XXI in FIG. 19.

FIGS. 22A and 22B are configuration examples of an electronic instrument.

Claims

1. A semiconductor integrated circuit comprising: N (N is an integer equal to or larger than two) pad rows disposed at intervals in a first direction, a plurality of pads being arranged in each of the N pad rows at intervals in a second direction perpendicular to the first direction; anda plurality of electrostatic discharge protection elements disposed in a lower layer of the N pad rows and respectively connected with one of the pads in the N pad rows;wherein at least N electrostatic discharge protection elements are connected with N pads each of which is a different and adjacent pad belonging in each of the N pad rows, and the at least N electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.

2. The semiconductor integrated circuit as defined in claim 1, wherein each of the at least N electrostatic discharge protection elements includes a first electrostatic discharge protection element connected between a first power supply line and one pad among the pads, and a second electrostatic discharge protection element connected between a second power supply line having a potential lower than a potential of the first power supply line and the one pad;wherein each of the pads is formed in an approximately rectangular shape having a long side along the first direction and a short side along the second direction; andwherein an impurity layer of each of the first and second electrostatic discharge protection elements has a shape in which a dimension in the second direction is greater than a dimension in the first direction.

3. The semiconductor integrated circuit as defined in claim 2, wherein one of the first and second electrostatic discharge protection elements connected with the pad in the first row is formed in a region positioned in a lower layer of the pad in the first row;wherein the other of the first and second electrostatic discharge protection elements connected with the pad in the Nth row is formed in a region positioned in a lower layer of the pad in the Nth row;wherein the N first electrostatic discharge protection elements are adjacently disposed in the first direction; andwherein the N second electrostatic discharge protection elements are adjacently disposed in the first direction.

4. The semiconductor integrated circuit as defined in claim 3, wherein a first well in which the N first electrostatic discharge protection elements are formed is formed along the second direction, and a second well in which the N second electrostatic discharge protection elements are formed is formed along the second direction; andwherein the first and second wells are separated in the first direction.

5. The semiconductor integrated circuit as defined in claim 3, wherein each of the second electrostatic discharge protection elements is disposed in a triple well.

6. The semiconductor integrated circuit as defined in claim 2, wherein the impurity layer of the first electrostatic discharge protection element connected with the pad is formed in a shape of a ring in plan view.

7. The semiconductor integrated circuit as defined in claim 2, comprising: a power supply protection element between the first and second power supply lines.

8. The semiconductor integrated circuit as defined in claim 7, comprising: a RAM which stores data displayed on a display panel, and a data driver which drives a data line of the display panel based on output from the RAM;wherein the pad is connected with an output line of the data driver; andwherein the RAM includes a bitline protection interconnect layer which protects a bitline, and the bitline protection interconnect layer is connected with the second power supply line and the power supply protection element.

9. The semiconductor integrated circuit as defined in claim 1, wherein each of the N pad rows includes M (M is an integer equal to or larger than two) pads, and (N×M) electrostatic discharge protection elements connected with the (N×M) pads are provided in a lower layer of regions at least partially including each of the (N×M) pads.

10. The semiconductor integrated circuit as defined in claim 9, wherein each of the (N×M) electrostatic discharge protection elements includes a first electrostatic discharge protection element connected between a first power supply line and one pad of the (N×M) pads, and a second electrostatic discharge protection element connected between a second power supply line having a potential lower than a potential of the first power supply line and the one pad of the (N×M) pads;wherein each of the (N×M) pads is formed in an approximately rectangular shape having a long side along the first direction and a short side along the second direction; andwherein an impurity layer of each of the first and second electrostatic discharge protection elements has a dimension in the second direction greater than a pad pitch in the second direction.

11. The semiconductor integrated circuit as defined in claim 10, wherein, when the first and second electrostatic discharge protection elements adjacently disposed in the first direction make a pair, two pairs of the first and second electrostatic discharge protection elements are mirror-image disposed with respect to an axis parallel to the second direction in the lower layer of each of the N pad rows.

12. The semiconductor integrated circuit as defined in claim 11, wherein outermost pads of the (N×M) pads in the second direction are connected with the first and second electrostatic discharge protection elements positioned in a lower layer of the outermost pads.

13. The semiconductor integrated circuit as defined in claim 9, comprising: a scan driver which drives a scan line of a display panel;wherein the pad is connected with an output line of the scan driver.

14. The semiconductor integrated circuit as defined in claim 1, wherein the pads are arranged at an equal pitch along the second direction in each of the N pad rows; andwherein two rows of the pads adjacent in the first direction are shifted in the second direction by a half pitch of the equal pitch.

15. An electronic instrument comprising the semiconductor integrated circuit as defined in claim 1.