Integrated circuit dielectric formation

Abstract

An integrated circuit and its method of formation are disclosed. The circuit utilizes a spin-on glass as an interlevel dielectric. Above and below the spin-on glass is located a phosphorous doped dielectric. The doped dielectric prevents sodium from becoming mobile under the influence of subsequently applied electric fields.

Description

TECHNICAL FIELD

This invention relates to integrated circuits and methods for their manufacture. More particularly, it relates to dielectrics employed in integrated circuits to provide isolation between electrical conductors.

BACKGROUND OF THE INVENTION

The use of spin-on glasses, including polysiloxanes, polysilicates and silsesquioxanes, is becoming increasingly prevalent in integrated circuit manufacture. Spin-on glasses are easily applied, and may be conveniently planarized with an optimized etch chemistry. Further, spin-on glasses fill small gaps better than many other dielectrics. However, the use of spin-on glass presents a variety of problems in integrated circuit manufacture.

SUMMARY OF THE INVENTION

Applicants have discovered that dielectrics which include spin-on glass that is partially etched back are vulnerable to mobile alkaline ion contamination. Consequently, applicants' process or semiconductor integrated circuit fabrication includes forming a first dielectric layer over a substrate; forming a second layer from the group consisting of spin-on glass and ozone TEOS; performing a process step which tends to introduce mobile ion contamination; and forming a third dielectric layer over the etched second layer. Both the first and third dielectric layers have phosphorous doping. The doped first and third layers help prevent mobile alkaline ion contamination of the underlying substrate. Illustratively, the process which tends to introduce mobile ion contamination may be an etching back of the second layer.

BRIEF DESCRITPION OF THE DRAWING

The FIGURE is a cross-sectional view of a partially fabricated integrated circuit which is helpful in understanding the present invention.

DETAILED DESCRIPTION

In the FIGURE, reference numeral 11 designates a substrate which may be silicon or silicon dioxide. In general, the term substrate refers to any material having 30 a surface upon which subsequent materials, layers, or structures may be formed. Reference numeral 11 may also represent a field oxide, a thinox region, or alternating field oxide and thinox regions (although not explicitly illustrated as such). Reference numerals 13, 15, and 17 designate topographical features upon substrate 11. Reference numerals 13, 15, and 17 may, for example, be MOS transistor gates or runners. Reference numeral 19 designates a dielectric which surrounds and covers features 13, 15, and 17. Reference numerals 21 and 23 designate topographical features such as conductive runners which may, typically, be made from aluminum, an aluminum alloy, or polysilicon or another conductive material.

Reference numerals 25, 27, and 29, taken together, designate a triple-layer dielectric which serves to encapsulate runners 21 and 23.

Reference numeral 25 is, illustratively, a silicon-dioxide-type dielectric having between 2% and 6% phosphorous by weight. Illustratively, dielectric 25 may be made from TEOS, or silane precursors. Trimethylphosphite (TMP) or phosphine (PH.sub.3) may be used as phosphorous dopant sources in the formation of dielectric 25. Dielectric 25 may also be a low temperature oxide. Typically, the thickness of dielectric 25 is 4000-7000 .ANG..

Dielectric 27 is a spin-on glass material, either a polysiloxane, polysilicate, or a silsesquioxane or ozone TEOS. Dielectric 27 may be applied by conventional techniques and then etched back to form a relatively planar upper surface 28. Upper surface 28 is frequently approximately level or even with the upper surface 26 of layer 25. An etchback step is necessary not only for planarization purposes, but also to remove the spin-on glass from the vicinity of dielectric surfaces such as 26 through which vias may be later opened. (If vias are opened through spin-on glass, moisture may subsequently enter the via and degrade the spin-on glass.) During the plasma etchback, sodium contamination of the upper surfaces 28 of dielectric 27 and upper surface 26 of dielectric 25 frequently occurs. In conventional processing, sodium contamination from plasma etching is frequently removed from the upper oxide surfaces by performing a short wet cleaning procedure in solutions such as 8:1 ethylene glycol:buffered hydrofluoric acid, or 100:1 water and hydrofluoric acid. However, typical wet cleaning procedures (which may be quite suitable for silane or TEOS-based dielectrics) tend to rapidly attack spin-on glass and thus tend to destroy the already-achieved planarization.

Consequently, after spin-on glass 27 is applied and etched back, the wet clean process mentioned above is preferably not performed. Instead, dielectric layer 29 is immediately formed on top of spin-on glass 27. Dielectric 29 may be similar to dielectric 25. That is, dielectric 25 contains between 2% and 6% phosphorous by weight and may be made from TEOS, silane, or may be a low temperature oxide.

Typically, the thickness of dielectric 29 is 4000-7000 .ANG..

Illustratively, dielectrics 29 and 25 may be formed in an Applied Materials Precision 5000 CVD system. A process chemistry utilizing TEOS, oxygen, and TMP as a phosphorous source may be employed. Wafer temperature is maintained at 390.degree. C., well below the critical temperature of 410-420.degree. C. for aluminum metalization. The plasma CVD reactor is operated at 2.0 to 9.0 Torr, with 200-1000 watts of RF power at 13.56 MHz.

Applicants have found that doping either the top or the bottom layer (i.e., layer 29 or 25) alone is not effective in preventing alkaline ion motion under the influence of electric fields. Both layers 29 and 25 are preferably doped. The phosphorous in layers 29 and 25, it is hypothesized, ties up or getters the mobile alkaline ions, thus preventing degradation of the ultimately formed integrated circuits.

Claims

1. A method of integrated circuit fabrication, comprising:

forming a first dielectric over runners which overlie a substrate, said first dielectric containing more than four percent and up to six percent phosphorous by weight;

forming a second dielectric layer;

etching back said second dielectric layer to expose at least one portion of said first dielectric layer; said runners remaining covered; and

forming a third dielectric layer over said second dielectric layer containing more than four percent and up to six percent phosphorous by weight.

2. A method as recited in claim 1, wherein said first and said third dielectric layers are silicon-dioxide.

3. A method as recited in claim 1, wherein said second dielectric layer is spin-on-glass.

4. A method as recited in claim 2, wherein said first and third dielectric layers have a thickness in the range of 4000-7000 .ANG..