Claims
- 1. A method manufacturing a semiconductor device, comprising the sequential steps of:forming first and second transistors on a main surface of a semiconductor substrate with a space between each other; forming first metal silicide at a surface of a source/drain of said second transistor with a source/drain of said first transistor being covered by an insulating film; forming an interlayer insulating film covering said first and second transistors; forming in said interlayer insulating film a first contact hole reaching one of said source/drain of said first transistor; forming a plug electrode in said first contact hole; forming in said interlayer insulating film a second contact hole reaching one of said source/drain of said second transistor; forming second metal silicide on said plug electrode; forming a bit line on said second metal silicide and an interconnection in said second contact hole.
Priority Claims (1)
Number |
Date |
Country |
Kind |
10-017232 |
Jan 1998 |
JP |
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Parent Case Info
This application is a divisional of U.S. patent application Ser. 09/452,099, filed Dec. 2, 1999, now abandoned, which is a divisional of U.S. patent application Ser. No. 09/119,053, filed Jul. 20, 1998, now U.S. Pat. No. 6,066,881.
US Referenced Citations (26)
Foreign Referenced Citations (3)
Number |
Date |
Country |
54-058386 |
May 1979 |
JP |
04-134859 |
May 1992 |
JP |
04-345065 |
Dec 1992 |
JP |