The present disclosure relates generally to systems and methods for controlling the temperature of a device, such as a semiconductor electronic device under test.
Systems for testing and handling electronic devices, such as packaged integrated circuit chips and unpackaged, bare “chips” or other devices under test (DUT), conventionally may include a temperature control system to maintain the temperature of the electronic device near a constant set point temperature while the device is being tested. Any type of circuitry can be integrated into the DUTs, such as digital logic circuitry or memory circuitry or analog circuitry. Also, the circuitry in the DUT can be comprised of any type of transistors, such as field effect transistors or bi-polar transistors.
It is desirable to keep the temperature of a device constant while it is tested. For example, it is common to test various integrated circuits for failure at certain temperatures. Further, a common practice in the chip industry is to mass produce a particular type of chip, and then speed sort them and sell the faster operating chips at a higher price. CMOS memory chips and CMOS microprocessor chips are processed in this fashion. However, because the speed with which the chip operates may be temperature dependent, the temperature of each chip must be kept nearly constant while the speed test is performed in order to determine the speed of such chips properly.
One challenge in keeping the temperature of a chip or collection of chips constant during testing is minimizing a temperature gradient across the one or more chips being tested. For example, a block (e.g., plate, holder, nest, etc.) may be placed in thermal contact with one or more chips, while the temperature of the block is controlled to attempt to keep the temperature of the one or more chips constant during testing. However, particularly for relatively large blocks, the temperature at one area of the block may become different than at another area of the block. In such a case, the resulting temperature gradient across the block may result in uneven temperatures across the one or more chips being tested, potentially compromising test results. Accordingly, systems and methods for minimizing temperature gradients across one or more chips during testing are needed.
One implementation of the present disclosure is a system comprising a plurality of thermally-coupled zones. Each of a plurality of thermal control devices is controllable to control the temperature of one of the plurality of thermally-coupled zones. The system also includes a plurality of temperature sensors. Each of the plurality of temperature sensors configured to measure temperature of one of the plurality of thermally-coupled zones. The system also includes a control circuit configured to receive, from the plurality of temperature sensors, a temperature measurement for each of the plurality of thermally-coupled zones, collect the temperature measurements in a temperature vector in a real coordinate system, and transform the temperature vector to a normal coordinate system. The normal coordinate system provides a plurality of uncoupled equations. The control circuit is also configured to determine, based on the plurality of uncoupled equations and a desired temperature gradient across the plurality of thermally-coupled zones, a desired power vector in the normal coordinate system. The control circuit is also configured to transform the desired power vector in the normal coordinate system to the real coordinate system to generate a power vector and control the plurality of heaters in accordance with the power vector to substantially achieve the desired temperature gradient across the plurality of thermally-coupled zones.
Referring generally to the drawings, systems and methods for providing temperature control of a thermal system with multiple thermally-coupled zones are shown, according to exemplary embodiments. The systems and methods described herein may be implemented in a variety of testing and handling system for devices, such as integrated circuit devices (e.g., devices under test or DUTs). In such systems, it may be advantageous to substantially maintain the DUTs at a desired temperature during testing. One approach is to place the DUTs in thermal contact with a block or other structure and control the temperature of the block. The DUTs might also be arranged in multiple sockets. In the exemplary systems contemplated herein, the DUTs are positioned relative to each other such that a significant temperature gradient may exist across the DUTs, e.g., a temperature at a first point on the block and a temperature at a second point on the block may be sufficiently different to compromise test results.
The present disclosure introduces the concept that the DUTS are positioned in multiple thermally-coupled zones, where each zone may have a different temperature. As described in detail herein, each zone may be provided with an independently-controllable thermal control device to facilitate better management of the temperature gradient across the block. The thermal control device may include, for example, a heater, although other thermal control devices may be used to heat or cool the one of multiple zones. Because the zones are thermally coupled to one another, the operation of each heater affects the temperature of all of the zones, and, therefore, the amount of heat required from each of the other heaters. In some cases, a fan is provided at each zone to facilitate removal of heat from the zone. Systems and methods for controlling the heaters and/or fans that account for thermal coupling between zones, as described in detail below, may therefore be advantageous in maintaining the block at a desired temperature across multiple zones and/or providing some other desired temperature gradient across the multiple zones.
Referring now to
As shown in
The thermal system 100 is further shown to include multiple heaters (e.g., four heaters), multiple temperature sensors (e.g., four temperature sensors), and multiple fans (e.g., four fans). Each zone may be aligned with one heater, one temperature sensor, and one fan. In the example shown, zone A 104 includes temperature sensor A 114, heater A 124, and fan A 134; zone B 106 includes temperature sensor B 116, heater B 126, and fan B 136; zone C 108 includes temperature sensor C 118, heater C 128, and fan C 138; and zone D 110 includes temperature sensor D 120, heater D 130, and fan D 140.
Each temperature sensor 114-120 is configured to measure the temperature of the block 102 at the corresponding zone. That is, temperature sensor A 114 measures the temperature at zone A 104 (“TA”), temperature sensor B 116 measures the temperature at zone B 106 (“TB”), temperature sensor C 118 measures the temperature at zone C 108 (“TC”), and temperature sensor D 120 measures the temperature at zone D 110 (“TD”). In some embodiments, the temperature sensors 114-120 include resistance thermal detectors (RTDs). The temperature sensors 114-120 may provide analog and/or digital indications of temperature to a control circuit 200, shown in
Each heater 124-130 is configured to provide heat to the block 102 at the corresponding zone. For example, heater A 124 provides heat to the block 102 at zone A 104. Each heater 124-130 may be operable at variable power to provide a variable amount or rate of heat to the block 102. As described in detail below, the heaters 124-130 are independently controllable, such that each heater A 124 may operate at a different power than heater B 126, heater B 126 may operate at a different power than heater C 128, and so on. The heaters 124-130 may convert electricity into heat through electrical resistance and/or generate heat in some other manner.
Each fan 134-140 is configured to blow air across the block 102 at the corresponding zone to facilitate the transfer of heat out of the block 102 via the heat exchanger 112, for example to draw the temperature of the block 102 towards the ambient air temperature. The fans 134-140 may be independently controllable to operate at various powers (e.g., fan blade speeds, airflow levels, etc.).
Referring now to
The control circuit 200 is configured to control the heaters 124-130 and/or the fans 134-140 based on the temperature measurements TA, TB, TC, TD. In the example shown, the control circuit 200 controls heater A 124 to operate at power PA, heater B 126 to operate at power PB, heater C 128 to operate a power PC, and heater D 130 to operate at power PD. In the example shown, the control circuit 200 may also control fan A 134 to operate at power PFanA, fan B 136 to operate at power PFan B, fan C 138 to operate at power PFanC, and fan D 140 to operate at power PFanD. The control circuit 200 may thereby control the amount of heat added and/or removed to each of the thermally-coupled zones 104-110. To determine the values of P={PA, PB, PC, PD, PFanA, PFan B, PFanC, PFanD}, the control circuit 200 may follow process 300 shown in
The control circuit 200 is configured to generate the power controls Pi based on the temperature measurements Ti to control the temperature and temperature gradient across the thermally-coupled zones to achieve a desired temperature gradient (e.g., zero gradient). In other words, in the formulation contemplated by the present disclosure, the control circuit 200 is configured to manage a dynamically-coupled thermal system that may be approximated by a multi-degree-of-freedom discrete system of order n defined by the system equation C{dot over (T)}+KT=P. In this formulation, C is the thermal capacity (or thermal mass) matrix with units of J/° C. K is the thermal conductivity matrix with units of W/° C. P is the power vector with units of W (e.g., a vector of PA through PD). T is the temperature vector (e.g., a vector of TA through TD). {dot over (T)} is the time-derivative of the temperature vector T (i.e., {dot over (T)}=δT/δt, where t is time) with units of ° C./s. Under a static analysis (i.e., {dot over (T)}=0), the power vector can be calculated based on a given temperature vector as KT=P. Inversely, in the static case the temperature can be calculated based on a given power vector as T=K−1 P.
In this formulation, the vectors (indicated by a single underline) are of length n and the matrices are n-by-n square. The parameter n may be any integer and may equal a count of the number of thermally-coupled zones and/or the number of controllable devices (i.e., heaters and/or fans). For example, in the example thermal system 100 of
In the dynamic, thermally-coupled system managed by the control circuit 200, the thermal coupling between various zones prevents conventional control approaches from being directly applied to the system equation provided above. Accordingly, as described in detail with reference to
To address the system equation C{dot over (T)}+KT=P, the homogenous equation C{dot over (T)}+KT=0 may be solved using an eigenvalue approach. Assume T=a e−λt, which implies {dot over (T)}=λT and [K−λC] T=0. Non-trivial solutions (i.e., T≠0) require det |K−λC|=0. There are n solutions, namely eigenvalues λi, i=1, . . . , n. Each eigenvalue λi has a corresponding eigenvector Ei that is scaled such that {tilde over (E)}lCEi=1, where {tilde over (E)}l is the transpose of the vector Ei. Orthogonality properties provide that
In a particular case, various methods may be used to find the numerical values of the eigenvalues λi and eigenvectors Ei for a physical thermal system. Using the eigenvectors Ei, a modal matrix V may be defined V=[E1, E2, . . . , En]. VT denotes the transpose of V. A vector θ may then be defined as T=Vθ, where θ is an n-length vector of elements θi. θ may be characterized as a representation of the temperature vector T in a normal coordinate system (whereas T defines temperature values in a real coordinate system). Given these definitions, the system equation C{dot over (T)}+KT=P can be rewritten as VT CV{dot over (θ)}+VT KVθ=VT P=F, where F is a vector of elements Fi that may be characterized as a representation of the power vector P in the normal coordinate system (whereas P defines power values in a real coordinate system).
The orthogonality principles above imply that VT CV=I, where I is the identity matrix, and VT KV=∧, where ∧ is a diagonal matrix containing the eigenvalues λi. Accordingly, the system equation VT CV{dot over (θ)}+VT KVθ=F can be reduced to {dot over (θ)}+∧θ=F, or, equivalently, n uncoupled equations of the form {dot over (θ)}i+λiθi=EiT P=Fi. The approach outlined in the preceding paragraphs thereby transforms a coupled system of equations that describes the dynamically-coupled thermal system in a real coordinate system to a collection of uncoupled equations in a normal coordinate system.
In online control, the control circuit 200 may calculate the values of θi from measured (real-coordinate) temperature values Ti based on: T=Vθ⇒θ=V−1T=[VT C]T. One or more of a variety of known control approaches may then be applied using the values of θi to generate values of Fi in the normal coordinate system based on the uncoupled equations {dot over (θ)}i+λiθi=Fi. The control circuit 200 may then convert Fi back to the real coordinate system to determine values of Pi following: F=VT P⇒P=(VT)−1F=[CV]F, which can then be directly used to control the heaters 124-130 and/or fans 134-140.
Referring now to
At step 302, the control circuit 200 identifies the matrices C and V to be used in converting between the real coordinate system and the normal coordinate system. More particularly, as θ=[VT C]T and P=[CV]F, the control circuit 200 may identify numerical values for each element of [VT C] and [CV] at step 302. In some cases, the values may be automatically derived by the control circuit 200. In other cases, the values may be derived be an engineer and pre-programmed on the control circuit 200.
For example, the values of the elements of matrices C and V may derived analytically based on a circuit-style diagram, for example diagram 400 of
From the diagram 400, the thermal capacity and conductivity matrix can be defined as
In the example of
where Cp is the specific heat [J/kg] of the material of the block 102 and m is the mass of the block 102.
Furthermore, from the diagram 400 of
In the example of
where l is the length of the block 102, Area is the cross-sectional area of the block 102, and k is the thermal conductivity of the block material.
From those definitions based on the diagram 400 of
From this statement of the system equation, eigenvalues and eigenvectors can be found for use in building the matrix V for step 302 of
These eigenvectors are plotted on graph 500 of
In such an example, the increased thermal capacity of zone B 104 creates an asymmetry reflected in the matrix V (and visible on the graph 600), but which may not otherwise affect the analysis presented herein.
Still referring to
with [CV] equal to the transpose of [VT C].
Still referring to
At step 306, a vector T of the real temperature measurements (in the real coordinate system) is converted to the normal coordinate system to determine the feedback θi. That is, θ is calculated as θ=[VT C]T, with θ made up of entries θi. This conversion allows the real temperature measurements from the temperature sensors 114-120 to be used as feedback in the normal coordinate system. At step 308, the values θi in the normal coordinate system are applied to uncoupled equations {dot over (θ)}i+λiθi=Fi to form scalar, first-order differential equations.
At step 310, the uncoupled are equations are used to determine desired values of Fi, which may be described as desired power in the normal coordinate system. Various optimizations, control approaches, etc. may be applied in various situations. For example, desired values of Fi may be determined based on a temperature setpoint for the block 102, to minimize a temperature gradient across the block 102 (e.g., to minimize the difference in the temperature measurements TA, TB, TC, TD), and/or to optimize an economic cost of operating the heaters 114-120. The values Fi are collected in the vector F.
At step 312, the power vector F in the normal coordinate system is converted to the real coordinate system to determine a real-coordinate power vector P. That is, the control circuit 200 calculates P as P=[CV] F. The control circuit 200 thereby calculates P, which is made up of the real-coordinate powers PA through PD in the example shown in
In some alternative embodiments, an eight-channel control system may be used to provide for control of the four heaters 124-130 as well as the four fans 134-140. In some embodiments, the control of the four fans 134-140 may be assumed to be uncoupled with the feedback for each fan being the heater power, which, in this example, may be measured and provided to the control circuit 200. In such an example, an error signal may be defined as: Er=
where Tspi is a temperature setpoint and Pspi is a heater power setpoint with (i=A, B, C, D) and the bottom four rows correspond to the control of the fans 134-140. As derived above, converting to the normal coordinate system requires multiplication by [VT C] to get θ=[VT C]Er. The matrix [VT C] reflects the fact that the bottom four rows are uncoupled. Using the example values calculated in the example above, the eight-channel version of [VT C] may be defined as
so that the uncoupled (bottom four) elements of Er (corresponding to the fans 134-140) are unaffected by the coordinate transformation. Note that [CV] has a similar form, such that the uncoupled elements are also unaffected by the coordinate transformation back to real coordinates under P=[CV] F. This is true even where the rows/elements such that the uncoupled degrees of freedom are interspersed among the coupled degrees of freedom (e.g., placed in positions 1, 3, 5, and 7 in Er).
In other embodiments, the control circuit 200 may use the output of some channels as the input into other channels. For example, in some cases the estimated heater power from one of the channels may be used as feedback for a cooling source such as a fan (e.g., one of fans 134-140), which may allow for minimization of heater output by controlling fan rotation. In such a case, using the Er vector defined above, heater outputs from the first four rows may be used as inputs to changes 5, 6, 7, and 8, respectively. The normal coordinates can then be defined as
In other cases, the matrix B may be used to provide a fixed output (e.g., fixed PWM). In such a case, in the example above the matrix B may be defined such that
It should be understood that many such variations and formulations are contemplated by the present disclosure to account for various features of the thermal system managed by the control circuit 200 and/or to facilitate optimization of various desired parameters.
Although the figures show a specific order of method steps, the order of the steps may differ from what is depicted. Also two or more steps can be performed concurrently or with partial concurrence. Such variation will depend on the software and hardware systems chosen and on designer choice. All such variations are within the scope of the disclosure. Likewise, software implementations could be accomplished with standard programming techniques with rule based logic and other logic to accomplish the various connection steps, calculation steps, processing steps, comparison steps, and decision steps.
The construction and arrangement of the systems and methods as shown in the various exemplary embodiments are illustrative only. Although only a few embodiments have been described in detail in this disclosure, many modifications are possible (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, values of parameters, mounting arrangements, use of materials, colors, orientations, etc.). For example, the position of elements can be reversed or otherwise varied and the nature or number of discrete elements or positions can be altered or varied. Accordingly, all such modifications are intended to be included within the scope of the present disclosure. The order or sequence of any process or method steps can be varied or re-sequenced according to alternative embodiments. Other substitutions, modifications, changes, and omissions can be made in the design, operating conditions and arrangement of the exemplary embodiments without departing from the scope of the present disclosure.
As used herein, the term “control circuit” may include hardware structured to execute the functions described herein. In some embodiments, the “control circuit” may include machine-readable media for configuring the hardware to execute the functions described herein. The control circuit may be embodied as one or more circuitry components including, but not limited to, processing circuitry, network interfaces, peripheral devices, input devices, output devices, sensors, etc. In some embodiments, the control circuit may take the form of one or more analog circuits, electronic circuits (e.g., integrated circuits (IC), discrete circuits, system on a chip (SOCs) circuits, etc.), telecommunication circuits, hybrid circuits, and any other type of “circuit.” In this regard, the “control circuit” may include any type of component for accomplishing or facilitating achievement of the operations described herein. For example, a control circuit as described herein may include one or more transistors, logic gates (e.g., NAND, AND, NOR, OR, XOR, NOT, XNOR, etc.), resistors, multiplexers, registers, capacitors, inductors, diodes, wiring, and so on).
The “control circuit” may also include one or more processors communicably coupled to one or more memory or memory devices. In this regard, the one or more processors may execute instructions stored in the memory or may execute instructions otherwise accessible to the one or more processors. In some embodiments, the one or more processors may be embodied in various ways. The one or more processors may be constructed in a manner sufficient to perform at least the operations described herein. In some embodiments, the one or more processors may be shared by multiple circuits (e.g., circuit A and circuit B may comprise or otherwise share the same processor which, in some example embodiments, may execute instructions stored, or otherwise accessed, via different areas of memory). Alternatively or additionally, the one or more processors may be structured to perform or otherwise execute certain operations independent of one or more co-processors. In other example embodiments, two or more processors may be coupled via a bus to enable independent, parallel, pipelined, or multi-threaded instruction execution. Each processor may be implemented as one or more general-purpose processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), or other suitable electronic data processing components structured to execute instructions provided by memory. The one or more processors may take the form of a single core processor, multi-core processor (e.g., a dual core processor, triple core processor, quad core processor, etc.), microprocessor, etc. In some embodiments, the one or more processors may be external to the apparatus, for example the one or more processors may be a remote processor (e.g., a cloud based processor). Alternatively or additionally, the one or more processors may be internal and/or local to the apparatus. In this regard, a given circuit (control circuit) or components thereof may be disposed locally (e.g., as part of a local server, a local computing system, etc.) or remotely (e.g., as part of a remote server such as a cloud based server). To that end, a “control circuit” as described herein may include components that are distributed across one or more locations. The present disclosure contemplates methods, systems and program products on any machine-readable media for accomplishing various operations. The embodiments of the present disclosure can be implemented using existing computer processors, or by a special purpose computer processor for an appropriate system, incorporated for this or another purpose, or by a hardwired system. Embodiments within the scope of the present disclosure include program products comprising machine-readable media for carrying or having machine-executable instructions or data structures stored thereon. Such machine-readable media can be any available media that can be accessed by a general purpose or special purpose computer or other machine with a processor. By way of example, such machine-readable media can comprise RAM, ROM, EPROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to carry or store desired program code in the form of machine-executable instructions or data structures and which can be accessed by a general purpose or special purpose computer or other machine with a processor. Combinations of the above are also included within the scope of machine-readable media. Machine-executable instructions include, for example, instructions and data which cause a general purpose computer, special purpose computer, or special purpose processing machines to perform a certain function or group of functions.
This application claims the benefit of and priority to U.S. Provisional Appl. 63/132,708, filed Dec. 31, 2020, the entire disclosure of which is incorporated by reference herein.
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20220206060 A1 | Jun 2022 | US |
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63132708 | Dec 2020 | US |