Claims
- 1. An integrated circuit, comprising:
electrical conductor tracks adjacently disposed parallel to one another and running substantially in a first direction, said electrical conductor tracks respectively having electrical connection points configured to be severed by application of energy, said connection points disposed offset with respect to one another both in said first direction and in a second direction at right angles to said first direction, said conductor tracks having an offset facing away from a respective adjacent one of said conductor tracks at a level of one of said connection points of said respective adjacent one of said conductor tracks to form a smaller spacing between two adjacent ones of said conductor tracks in said second direction in each case where adjacent ones of said conductor tracks do not have a connection point than where adjacent ones of said conductor tracks has a connection point.
- 2. The integrated circuit according to claim 1, wherein:
said connection points include a central electrical connection point and two outer electrical connection points; said central connection point is disposed between said two outer connection points both in said first direction and in said second direction; said conductor tracks include a central conductor track and two outer conductor tracks; said central conductor track and said two outer conductor tracks are disposed parallel to one another and run substantially in said first direction; each of said central connection point and said two outer connection points are respectively a constituent part of one of said central and said two outer conductor tracks; each of said two outer conductor tracks has an offset facing away from said central connection point at a level of said central connection point, and an offset facing said central connection point at a level of a respective one of said two outer connection points of each of said two outer conductor tracks; and said central conductor track has a respective offset facing away from said central conductor track at a level of said two outer connection points.
- 3. The integrated circuit according to claim 2, wherein:
said connection points include multiples of said central and two outer electrical connection points; and said multiples are disposed adjacent to one another in said second direction.
- 4. The integrated circuit according to claim 2, including a first metallization plane and a second metallization plane, said central and said two outer conductor tracks being a constituent part of said first metallization plane in a region of a respective one of said central and said two outer connection points, and said central and said two outer conductor tracks being a constituent part of said second metallization plane in a region of others of said connection points.
- 5. The integrated circuit according to claim 3, including a first metallization plane and a second metallization plane, said central and said two outer conductor tracks being a constituent part of said first metallization plane in a region of a respective one of said central and said two outer connection points, and said central and said two outer conductor tracks being a constituent part of said second metallization plane in a region of others of said connection points.
Priority Claims (1)
Number |
Date |
Country |
Kind |
198 35 263.8 |
Aug 1998 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of International Application No. PCT/DE99/02398, filed Aug. 2, 1999, which designated the United States.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/DE99/02398 |
Aug 1999 |
US |
Child |
09776954 |
Feb 2001 |
US |