Claims
- 1. A computer system comprising:
a first integrated circuit including a memory; and a second integrated circuit coupled to the first integrated circuit, the second integrated circuit including a support of semiconductor material with opposed sides, said support including a spatial light modulator mounted on one side of said support and a microprocessor, mounted on the opposed side of said support, said microprocessor being coupled by an electrical conductor to said modulator through said support.
- 2. The system of claim 1 wherein said spatial light modulator of said second integrated circuit is formed using liquid crystal on silicon technology.
- 3. The system of claim 1 wherein said second integrated circuit includes a plurality of conductors formed as dielectric insulated vias which extend from one opposed side to the other opposed side of said support.
- 4. The system of claim 1 wherein said second integrated circuit includes a plurality of conductive vias which extend through said support, a plurality of mirror pads in said modulator and a plurality of conductive pads in said processor, each of said vias contacting a mirror pad in said modulator on one side of said support, and a metal pad on the other side of said support.
- 5. The system of claim 1 wherein said support includes a transparent conductive layer and a liquid crystal layer, an electrical contact being formed through said spatial light modulator to said conductive layer.
- 6. The system of claim 1 wherein said support includes a hole formed completely through said support forming a tubular wall, a dielectric layer formed on said wall and a conductive layer formed within said hole such that said dielectric layer is sandwiched between said conductive layer and said support, a mirror pad being formed in electrical contact with said conductive layer, said mirror pad forming part of said spatial light modulator
- 7. The system of claim 1 including an interface coupled to said second integrated circuit.
- 8. The system of claim 7 including a bus coupled to said interface.
Parent Case Info
[0001] This is a continuation-in-part of U.S. patent application Ser. No. 09/430,284 filed Oct. 29, 1999.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09430284 |
Oct 1999 |
US |
Child |
10035643 |
Nov 2001 |
US |