Integrated circuit

Abstract

An integrated circuit wherein a gate circuit is provided on a bus line mounted on a semiconductor substrate. The gate circuit is used to separate an unused circuit block from other circuit blocks which are connected to a bus line through an input-output circuit for high speed data transmission, thereby reducing a parasitic capacity which might be imparted to the bus line by the separated circuit block. The input-output circuit is formed of a clocked inverter. The gate circuit is formed of a C.multidot.MOS transmission gate. The input-output circuit and gate circuit are so connected that where the gate of the inverter is opened, then the C.multidot.MOS transmission gate is closed; and where the gate of the inverter is closed, then the C.multidot.MOS transmission gate is opened.

Description

BACKGROUND OF THE INVENTION

This invention relates to an integrated circuit for processing signals at high speed by decreasing a parasitic capacity in a common bus line.

A bus line system is generally adopted for a highly integrated circuit to effectively reduce an area occupied by wiring. With the bus line system, the peripheral circuits are grouped into blocks. These circuit blocks are connected to a given number of common bus lines through the corresponding input-output circuits (hereinafter referred to as "I/O circuits"). Data are transmitted between the respective peripheral circuits through the common bus lines. Therefore, as compared with a system using independent lines for the respective circuit blocks, the bus line system can noticeably decrease the number of lines, thereby simplifying arrangement of lines and preventing an increase in their number.

With the above-mentioned bus line system, the bus lines and diffused regions constituting I/O circuits are connected by diffused lines. Consequently, a difficulty arises in that the junction capacity possessed by the diffused regions tends to be parasitically accumulated in the bus line.

FIG. 1 illustrates the manner in which a parasitic capacity is accumulated in a bus line used with a conventional bus line system. FIG. 1 shows in enlargement part of a junction of a diffused line and bus line used in the prior art integrated circuit provided with four common bus lines. The common bus lines 10.sub.1 to 10.sub.4 are formed of aluminum and are arranged in parallel at a prescribed interval. The common bus lines 10.sub.1 to 10.sub.4 are set on diffused lines 12.sub.1 to 12.sub.4 at right angles. Reference numerals 13.sub.1 to 13.sub.4 denote the regions in which the diffused lines 12.sub.1 to 12.sub.4 and bus lines 10.sub.1 to 10.sub.4 contact each other. As a result, the capacities of the diffused lines 12.sub.1 to 12.sub.4 and the capacities 14.sub.1 to 14.sub.4 of diffused I/O regions (not shown) become parasitic on the common bus lines 10.sub.1 to 10.sub.4.

Where an integrated circuit is enlarged in scale and consequently circuit blocks increase in number, then I/O circuits connected to common bus lines also have a large number. Therefore, a parasitic capacity in the common bus line increases. The increased parasitic capacity causes the common bus line to have a large time constant (.tau.=CR). Accordingly, transmission of a signal through such common bus line is prominently delayed. This event presents difficulties in processing data at high speed by a one chip LSI circuit.

For resolution of the above-mentioned drawback, a method has been proposed which is intended to elevate the conductivity of diffused I/O lines. However, this method results in an increase in a total area of diffused lines, and consequently a decline in an integration density per unit area. Therefore, said method has proved practically unsuitable for high integration.

SUMMARY OF THE INVENTION

It is accordingly an object of this invention to provide an integrated circuit which minimizes a parasitic capacity in a common bus line.

Another object of the invention is to provide an integrated circuit which can accelerate data transmission.

Still another object of the invention is to provide an integrated circuit which enables an unused circuit block to be easily removed.

To attain the above-mentioned objects, the invention provides an integrated circuit which comprises:

a plurality of circuit blocks formed on a semiconductor substrate; I/O circuits which are formed on the semiconductor substrate in connection to the circuit blocks to carry out data transmission between the circuit blocks; bus lines which are connected to the I/O circuits for data transmission between the circuit blocks; and a gate circuit which is connected to the bus lines to separate a circuit block unrelated to data transmission from other circuit blocks carrying out high speed data transmission.

With an integrated circuit embodying this invention which is arranged as described above, a circuit block unrelated to data transmission is separated from other circuit blocks carrying out high speed data transmission, thereby decreasing parasitic capacity to an extent corresponding to the separation of said unrelated circuit block, and effecting high speed data transmission between circuit blocks.

With the integrated circuit of the invention, an I/O circuit is formed of a clocked inverter, and a gate circuit is formed of a C.multidot.MOS transmission gate circuit. Where the gate of the clocked inverter is opened, then the C.multidot.MOS transmission gate circuit is closed by mutually complementary control signals. Conversely where the C.multidot.MOS transmission gate circuit is opened, then the clocked inverter is closed by said mutually complementary control signals. Therefore, an unused circuit block can be easily separated from a bus line.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects of the invention will be seen by reference to the description taken in connection with the accompanying drawings, in which:

FIG. 1 is a partial enlarged view of a prior art integrated circuit, showing connection between diffused lines and bus lines;

FIG. 2 shows an arrangement of an integrated circuit embodying this invention which is provided with 4-bit bus lines;

FIG. 3 schematically indicates an arrangement of a circuit block whose memory circuit is formed of a random access memory (RAM);

FIG. 4 sets forth with respect to 1-bit data an arrangement of an I/O circuit included in the integrated circuit of FIG. 2 and a gate circuit; and

FIG. 5 shows with respect to 4-bit data an arrangement of an I/O circuit included in the integrated circuit of FIG. 2 and a gate circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This invention is applicable to an integrated circuit provided with bus lines of more than 1 bit. Description is now given with respect to FIGS. 2 to 5 of an integrated circuit embodying the invention which is provided with 4-bit bus lines. FIG. 2 is a schematic block diagram showing an arrangement of the above-mentioned 4-bit bus line type integrated circuit. Each of circuit blocks 16.sub.1 to 16.sub.4 formed on a semiconductor substrate constitutes, for example, a memory circuit shown in FIG. 3. The circuit blocks 16.sub.1 to 16.sub.4 may constitute arithmetic operation circuits or any other logic circuits or a combustion thereof.

Referring to FIG. 2, I/O circuits 18.sub.1 to 18.sub.4 are connected to the circuit block 16.sub.1 ; I/O circuits 18.sub.5 to 18.sub.8 to the circuit block 16.sub.2 ; I/O circuits 18.sub.9 to 18.sub.12 to the circuit block 16.sub.3 ; and I/O circuits 18.sub.13 to 18.sub.16 to the circuit block 16.sub.4. These I/O circuits 18.sub.1 to 18.sub.16 carry out data supply to the block circuits 16.sub.1 to 16.sub.4 and data withdrawal therefrom.

Four bus lines 20.sub.1 to 20.sub.4 are connected to the I/O circuits 18.sub.1 to 18.sub.16, and used in common as passages of data transmission between the circuit blocks 16.sub.1 to 16.sub.4.

A gate circuit 22 is provided for the bus lines 20.sub.1 to 20.sub.4. When opened, the gate circuit 22 separates circuit blocks 16.sub.3, 16.sub.4 from a unit 24 which is formed of the circuit blocks 16.sub.1, 16.sub.2 and I/O circuits 18.sub.1 to 18.sub.8, thereby ensuring high speed data transmission. When closed, the gate circuit 22 connects said unit 24 to the other blocks 16.sub.3, 16.sub.4.

Either or both of the circuit blocks 16.sub.3, 16.sub.4 when carrying out data transmission with respect to the unit 24 have a large parasitic capacity. It is therefore preferred in the unit 24 to position the circuit blocks 16.sub.1, 16.sub.2 undertaking high speed data transmission facing each other as closely as possible (as shown in FIG. 2) with the bus lines 20.sub.1 to 20.sub.4 interposed therebetween.

FIG. 3 shows a schematic arrangement of the circuit block 16.sub.1 constituting a RAM unit. The I/O circuit 18.sub.1 is connected through I/O lines 28.sub.1, 28.sub.2 to a group of RAM cells 26.sub.1 to 26.sub.3 connected in parallel with respect to said I/O lines 28.sub.1, 28.sub.2. The I/O circuit 18.sub.2 is connected through I/O lines 28.sub.3, 28.sub.4 to a group of RAM cells 26.sub.4 to 26.sub.6 connected in parallel with respect to said I/O lines 28.sub.3, 28.sub.4. The I/O circuit 18.sub.3 is connected through I/O lines 28.sub.5, 28.sub.6 to a group of RAM cells 26.sub.7 to 26.sub.9 connected in parallel with respect to said I/O lines 28.sub.5, 28.sub.6. The I/O circuit 18.sub.4 is connected through I/O lines 28.sub.7, 28.sub.8 to a group of RAM cells 26.sub.10 to 26.sub.12 connected in parallel with respect to said I/O lines 28.sub.7, 28.sub.8. Data is supplied to and withdrawn from the RAM cells 26.sub.1 to 26.sub.12 through the I/O lines 28.sub.1 to 28.sub.8. The RAM cells 26.sub.1 to 26.sub.12 are connected to address lines 30.sub.1 to 30.sub.12. Four RAM cells constituting any of three groups (26.sub.1 -26.sub.4 -26.sub.7 -26.sub.10), (26.sub.2 -26.sub.5 -26.sub.8 -26.sub.11), (26.sub.3 -26.sub.6 -26.sub.9 -26.sub.12) are selected by address signals supplied through the corresponding group of address lines chosen from among address lines 30.sub.1 to 30.sub.12 (for example, through the address lines 30.sub.1, 30.sub.2, 30.sub.3, 30.sub.4 for the group of RAM cells 26.sub.1 -26.sub.4 -26.sub.7 -26.sub.10). Data stored in the selected RAM cells are sent forth to any of the common bus lines 20.sub.1 to 20.sub.4 and/or data conducted through any of said common bus lines 20.sub.1 to 20.sub.4 are stored in the selected RAM cells.

Diffused lines 32.sub.1 to 32.sub.4 are formed as indicated in broken lines in FIG. 3 for connection between the I/O circuits 18.sub.1 to 18.sub.4 and bus lines 20.sub.1 to 20.sub.4. Therefore, junction capacities possessed by the diffused lines 32.sub.1 to 32.sub.4 and diffused regions constituting I/O circuits 18.sub.1 to 18.sub.4 are parasitically accumulated in the bus lines 20.sub.1 to 20.sub.4. The circuit blocks 16.sub.1 to 16.sub.4 impart a parasitic capacity, large or small, to the common bus lines 20.sub.1 to 20.sub.4, and consequently may be regarded as capacitive loads. These loads enlarge the time constant (.tau.=CR) of the respective bus lines 20.sub.1 to 20.sub.4, and slow down the speed of data transmission therethrough. Actually, a circuit block having an exceedingly large parasitic capacity is sometimes connected to a bus line. This event undesirably gives rise to a decline in the designed high speed of data transmission carried out by the circuit block.

With an integrated circuit embodying this invention, a gate circuit is provided, as described later, for a bus line. This arrangement enables a circuit block imparting a particularly large parasitic capacity to a bus line to be separated from other circuit blocks when they carry out high speed data transmission, thereby ensuring accelerated data transmission between said circuit blocks.

FIG. 4 shows the connection between the I/O circuit 18.sub.8 of FIG. 2 and the gate circuit 22 with respect to a 1-bit bus line 20.sub.4. The I/O circuit 18.sub.8 is formed between the circuit blocks 16.sub.2 and bus line 20.sub.4. The gate circuit 22 is provided for the bus lines 20.sub.1 to 20.sub.4 set between the unit 24 and the circuit blocks 16.sub.3, 16.sub.4 (not shown in FIG. 4).

The output section of the I/O circuit 18.sub.8 is formed of a clocked inverter 34.sub.1. This inverter 34.sub.1 is formed by arranging between a first power source V.sub.DD and a second power source V.sub.SS first and second P channel transistors 36.sub.1, 36.sub.2 and third and fourth N channel transistors 38.sub.1, 38.sub.2 in such a manner that the sources and drains of the respective transistors are sequentially connected in series. A data signal sent forth from the circuit block 16.sub.2 is supplied to the first and fourth transistors 36.sub.1, 38.sub.2. The source of the second transistor 36.sub.2 and the drain of the third transistor 38.sub.1 is connected to the bus line 20.sub.4. An inverted data signal is issued from the junction to the bus line 20.sub.4. A DATA OUT signal is supplied to the gate of the third transistor 38.sub.1. The output terminal of an inverter 40 is connected to the gate of the second transistor 36.sub.2 to supply a DATA OUT signal to the gate of said second transistor 36.sub.2.

The clocked inverter 35.sub.1 constituting an input section of the I/O circuit 18.sub.8 has the same arrangement as the clocked inverter 34.sub.1.

The gate circuit 22 is formed of C.multidot.MOS transmission gates 42.sub.1 to 42.sub.4 having the same arrangement. Therefore, description is only given of a C.multidot.MOS transmission gate 42.sub.1. This C.multidot.MOS transmission gate 42.sub.1 is formed by mutually connecting the sources of an N channel transmission gate 44.sub.1 and P channel transmission gate 44.sub.2 and also mutually connecting their drains. The source terminal of the C.multidot.MOS transmission gate 42.sub.1 is connected to that portion a common bus line 20.sub.4 which is connected to the unit 24. The drain terminal of said C.multidot.MOS transmission gate 42.sub.1 is connected to that portion of the common bus line 20.sub.4, which is connected to the circuit blocks 16.sub.3, 16.sub.4.

The gate of a second transistor 36.sub.2 included in the clocked inverter 34.sub.1 is connected to the gate of an N channel transistor 44.sub.1 included in the C.multidot.MOS transmission gate 42.sub.1. The gate of a third transistor 38.sub.1 included in the clocked inverter 34.sub.1 is connected to the gate of a P channel transistor 44.sub.2 included in the C.multidot.MOS transmission gate 42.sub.1.

Description is now given of the operation of an I/O circuit shown in FIG. 4. A DATA OUT clock signal having a logic level "1" is supplid from a control circuit (not shown) to the gate of the third transistor 38.sub.1 included in the clocked inverter 34.sub.1. A DATA OUT clock signal having a logic level "0" is delivered through an inverter 40 to the gate of a second transistor 36.sub.2 included in the inverter 34.sub.1. As a result, the gate voltages of the second and third transistors 36.sub.2, 38.sub.1 grow higher than the respective threshold voltages, thereby rendering said second and third transistors 36.sub.2, 38.sub.1 conducting. On the other hand, the gate voltages of the N and P channel transistors 44.sub.1, 44.sub.2 included in the C.multidot.MOS transmission gate 42.sub.1 fall below the respective threshold voltages, thereby rendering said N and P channel transistors 44.sub.1, 44.sub.2 nonconducting. Therefore, even though data is sent forth from the circuit block 16.sub.2 to the bus line 20.sub.4 through the clocked inverter 34.sub.1, data is not transmitted through said C.multidot.MOS transmission gate 42.sub.1.

Conversely, where the DATA OUT clock signal has a logic level "0" and the DATA OUT clock signal has a logic level "1", then the gate voltages of the second and third transistors 36.sub.2, 38.sub.1 become lower than the respective threshold voltages, rendering said transistors 36.sub.2, 38.sub.1 nonconducting. On the other hand, the gate voltages of the N and P channel transistors included in the C.multidot.MOS transmission gate 42.sub.1 grow higher than the respective threshold voltages, thereby rendering said N and P channel transistors 44.sub.1, 44.sub.2 conducting. In other words, where the clocked inverter 34.sub.1 is actuated, then the C.multidot.MOS transmission gate 42.sub.1 remains inoperative. Conversely, where the C.multidot.MOS transmission gate 42.sub.1 is actuated, the inverter 34.sub.1 is thrown out of operation. Therefore, data transmission from the circuit block 16.sub.2 to the circuit block 16.sub.1 can be accelerated by rendering the clocked inverter 34.sub.1 conducting and the transmission gate 42.sub.1 nonconducting. Moreover, the aforementioned circuit arrangement eliminates the necessity of producing any particular signal to actuate the C.multidot.MOS transmission gate 42.sub.1.

Therefore, the bus line 20.sub.4 can be easily shut off by the I/O circuit of FIG. 4 having a simple arrangement, thereby readily eliminating a parasitic capacity imparted to the bus line 20.sub.4 by the I/O circuits 18.sub.12, 18.sub.16. Consequently data transmission between the circuit blocks 16.sub.1, 16.sub.2 is saved from the harmful affect of the parasitic capacity 46.sub.1. Therefore, a circuit dimension can be reduced by taking into account only the adverse effect of the parasitic capacity 48.sub.1 imparted to the bus line 20.sub.4 by the I/O circuits 18.sub.4, 18.sub.8, thereby accelerating data transmission. In other words, this invention exerts a prominent effect, where it is necessary to separate that portion of, for example, a bus line 20.sub.4 where a particularly large parasitic capacity is accumulated.

FIG. 5 shows connection between the gate circuit 22 and the output terminals of the 4-bit I/O circuits 18.sub.5 to 18.sub.8 for controlling an input to and an output from the circuit block 16.sub.2 shown in FIG. 2. Description was given with reference to FIG. 4 of the operation of the clocked inverter 18.sub.8 and C.multidot.MOS transmission gate 42.sub.1 with respect to a 1-bit bus line 20.sub.4. The operation of said clocked inverter 18.sub.8 and C.multidot.MOS transmission gate 42.sub.1 is fundamentally the same as in FIG. 4 with respect to 4-bit bus lines 20.sub.1 to 20.sub.4, too. The respective elements of FIG. 5 are connected in the same way as in FIG. 4. Referring to FIG. 5, a single circle denotes a P channel transistor, and a double circle shown an N channel transistor.

Where the clocked inverters 34.sub.1 to 34.sub.4 are supplied with a DATA OUT clock signal having a logic level "1" and a DATA OUT clock signal having a logic level "0", then the gates of said clocked inverters 34.sub.1 to 34.sub.4 are opened. As a result, data is sent forth from the circuit block 16.sub.2 to the 4-bit bus lines 20.sub.1 to 20.sub.4 as indicated in arrows in FIG. 5. At this time, the C.multidot.MOS transmission gates 42.sub.1 to 42.sub.4 of the gate circuit 22 remain closed, thereby separating unused circuit blocks 16.sub.3, 16.sub.4. Therefore, data is not transmitted through the gates 42.sub.1 to 42.sub.4. The reason for this is that, as described with respect to FIG. 4, the clocked inverters 34.sub.1 to 34.sub.4 and C.multidot.MOS transmission gates 42.sub.1 to 42.sub.4 are connected together in complementary relationship; where, therefore, the inverters 34.sub.1 to 34.sub.4 are rendered conducting, then the transmission gates 42.sub.1 to 42.sub.4 are closed; and conversely where the inverters 34.sub.1 to 34.sub.4 are thrown out of operation, then the transmission gates 42.sub.1 to 42.sub.4 are opened.

Where, 4-bit data is supplied from the circuit block 16.sub.2 to the bus lines 20.sub.1 to 20.sub.4 through the clocked inverters 34.sub.1 to 34.sub.4, then it is possible to completely eliminate parasitic capacities 46.sub.1 to 46.sub.4 accumulated in the bus lines 20.sub.1 to 20.sub.4 separated by the C.multidot.MOS transmission gates 42.sub.1 to 42.sub.4. As a result, data transmission governed by a time constant .tau.=CR defined by the circuit constants of the bus lines 20.sub.1 to 20.sub.4 can be accelerated to an extent corresponding to the parasitic capacities 46.sub.1 to 46.sub.4 eliminated by the C.multidot.MOS transmission gates 42.sub.1 to 42.sub.4.

This invention is not limited to the abovementioned embodiment in which four bus lines were used. But the invention is obviously applicable to an integrated circuit provided with one or more bus lines. Further, with the foregoing embodiment, a single C.multidot.MOS transmission gate is set in one bus line. However, more than one C.multidot.MOS transmission gates may be provided in one bus line. Further with the foregoing embodiment, the conduction and nonconduction of the C.multidot.MOS transmission gates 42.sub.1 to 42.sub.4 constituting the gate circuit 22 were carried out by control signals supplied to the clocked inverters 34.sub.1 to 34.sub.4. However, it is possible to use control signals supplied to the clocked inverters of other circuit blocks, depending on the arrangement of output inverters formed on the semiconductor substrates of clocked inverters connected to the transmission gates 42.sub.1 to 42.sub.4. Obviously, this invention may be applied in various modifications without departing from the scope and object of the invention.

Claims

1. An integrated circuit which comprises:

first, second and third circuit blocks for storing data;

a bus line;

first, second and third input-output means with said first input-output means connected between said bus line and said first circuit block, said second input-output means connected between said bus line and said second circuit block, and said third input-output means connected between said bus line and said third input-output block, for supplying data received from said bus line to said respective circuit blocks and for withdrawing data from said respective circuit blocks to said bus line, the connections of said first and second input-output means to said bus line and the connection of said third input-output means to said bus line being spaced from each other along said bus line; and

gate circuit means coupled to said bus line between said connections of said first and second input-output means and the connection of said third input-output means to said bus line, for separating said first and second circuit blocks from said third circuit block upon transmission of data over said bus line between said first and second circuit blocks.

2. The integrated circuit according to claim 1 wherein said input-output means each comprises a clocked inverter having an N channel transistor and a P channel transistor.

3. The integrated circuit according to claim 2 wherein said gate circuit means comprises a C.multidot.MOS transmission gate circuit.

4. The integrated circuit according to claim 3 wherein said C.multidot.MOS transmission gate circuit comprises a P channel transmission gate and an N channel transmission gate connected in parallel to one another, source to source and drain to drain, with the control electrode of said P channel transmission gate connected to the control electrode of said N channel transistor included in said clocked inverter and the control electrode of said N channel transmission connected to the control electrode of said P channel transistor included in said clock inverter, and means for supplying mutually complementary control signals to said control electrodes of said P channel and N channel transmission gates, said two gates of said C.multidot.MOS transmission gate circuit being closed when said N and P channel transistors of said clock inverter are nonconducting and said two gates of said C.multidot.MOS transmission gate circuit being opened when said N and P channel transistors of said inverter are conducting.