The present disclosure generally relates to integrated circuits having improved contacts and to improved methods for fabricating integrated circuits having contacts, and more particularly relates to integrated circuits having self-aligned contacts formed over source/drain regions and methods for fabricating integrated circuits having self-aligned contacts formed over source/drain regions.
Self-aligned silicide technology has been widely implemented in existing CMOS technology with polysilicon gates by forming silicide on both the polysilicon gates and source/drain regions in a self-aligned manner, so that the source/drain resistance and polysilicon gate resistance are reduced (from resistance of doped silicon), leading to good device performance and yield. The self-aligned silicide process consists of depositing a layer of transition metal (e.g. Ti, Co, Ni, Al, etc.) over the partially fabricated integrated circuit followed by a rapid thermal anneal (RTA). As is well-known, chemical reaction occurs between silicon and metal to form silicide, while metal contacting silicon-oxide or other non-silicon materials remains non-reacted and does not form silicide. Edges of the silicide are aligned with the edge of the underlying silicon layer.
In advanced CMOS processing, high-k metal-gate technology is the standard practice and the self-aligned silicide technology is performed on source/drain regions after polysilicon gate/spacer formation and epitaxial layer growth on source/drain regions (in gate-first flow) or after replacement gate formation (in gate-last flow). Self-aligned silicide technology is also used for non-planar integrated circuits, such as with FinFET technology, and is performed on the source/drain regions after polysilicon gate/spacer formation (gate-first flow) or after replacement gate formation (gate-last flow).
Whether used with planar or non-planar structures, conventional processes using self-aligned silicide technology can lead to yield loss in integrated circuit fabrication. Specifically, conventional processing deposits a dielectric layer over the silicide contacts, and then etches through the dielectric layer to form holes that land on the silicide contacts. The holes are then filled with conductive material to form local interconnects. Alignment of the holes with the silicide contacts can be difficult to achieve during contact hole formation. Misalignment of the contact holes with the silicide contacts leads to “contact punch-through” wherein the local interconnect formed in the contact hole lands directly on the semiconductor substrate instead of onto a silicide contact. Contact punch-through results in high contact resistance.
When self-aligned silicide technology is used in conjunction with stress regions that selectively modify channel mobility, the process typically requires formation of silicon over the stress regions. Specifically, source/drain regions are typically etched to form cavities that are filled with stress material. Then, an upper portion of the stress material is etched and replaced with a layer of undoped silicon. The self-aligned silicide process reacts a metal with the layer of undoped silicon to form a silicide contact over the stress material and aligned with the semiconductor substrate. Due to the inclusion of the layer of silicon material/silicide contact in the cavities, the amount of force exerted from the cavity is less than optimal.
Accordingly, it is desirable to provide improved integrated circuits and improved methods for fabricating integrated circuits with self-aligned contacts. In addition, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that increase stress applied to channels for increased channel mobility. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
Integrated circuits having improved contacts and improved methods for fabricating integrated circuits having contacts are provided. In accordance with one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a source/drain region. The method deposits an interlayer dielectric material over the semiconductor substrate. Further, the method etches the interlayer dielectric material to form a hole defining an exposed portion of the source/drain region. The method includes forming a contact in the hole over the exposed portion of the source/drain region and forming an interconnect in the hole over the contact.
In another embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper substrate surface. The method includes etching a cavity into the semiconductor substrate. The method fills the cavity with a stress material that has an upper stress surface substantially coplanar with the upper substrate surface. The method includes depositing an interlayer dielectric over the upper stress surface and upper substrate surface. The method further includes etching the interlayer dielectric material to expose a portion of the upper stress surface and forming a contact over the exposed portion of the upper stress surface.
In accordance with another embodiment, an integrated circuit is provided. The integrated circuit includes a semiconductor substrate having a source/drain region. The integrated circuit includes a contact on the source/drain region that has a first contact edge and a second contact edge. The integrated circuit further includes an interconnect structure on the contact. The interconnect structure has a first interconnect edge aligned with the first contact edge and a second interconnect edge aligned with the second contact edge.
Embodiments of integrated circuits having improved contacts and improved methods for fabricating integrated circuits having contacts will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following detailed description is merely exemplary in nature and is not intended to limit the various embodiments of the integrated circuits or the methods for fabricating integrated circuits claimed herein. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or brief summary, or in the following detailed description.
Integrated circuits and methods for fabricating integrated circuits as described herein avoid issues faced in conventional processes. For example, exemplary integrated circuits and exemplary methods for fabricating integrated circuits avoid contact punch-through during contact hole formation. In an embodiment, an interlayer dielectric material is formed over areas to be contacted, such as source/drain regions or gate structures, before contacts or contact-forming layers are formed on the areas to be contacted. Then, the dielectric material is etched to form holes exposing the areas to be contacted. After exposing the areas to be contacted, a contact formation process is performed including, for example, deposition of a silicon material and a silicide-forming material followed by a thermal anneal process. As a result, the exemplary method forms contacts in the contact holes and contact hole punch-through is avoided. Also, exemplary integrated circuits and exemplary methods for fabricating integrated circuits provide for increased or maximized stress application to channel regions under selected gate structures by filling stress region cavities with stress material. The stress material is formed with an upper surface co-planar with the upper surface of the semiconductor substrate. The exemplary contact formation process deposits silicon material and silicide-forming material over the upper surface of the stress material and not in the stress region cavity. As a result, the stress exerted by the stress region cavity may be optimized.
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As shown, gate structures 16 and 17 are formed overlying the semiconductor substrate 12. Each gate structure 16 and 17 can be realized as a composite structure or stack that is formed from a plurality of different layers and materials. In this regard, the gate structures 16 and 17 can be formed by conformally depositing layers of material, using photolithographic techniques to pattern the deposited layers of material, and selectively etching the patterned layers to form the desired size and shape for the gate structures 16 and 17. For example, a relatively thin layer of dielectric material (commonly referred to as the gate insulator) can be initially deposited over the semiconductor substrate 12 using, for example, a sputtering, chemical vapor deposition (CVD) or atomic layer deposition (ALD) technique. Alternatively, this gate insulator layer could be formed by growing a dielectric material, such as silicon dioxide, on exposed silicon surfaces of the semiconductor substrate 12. In certain embodiments, a gate electrode material, such as a polycrystalline silicon material or a metal material (e.g., titanium nitride, tantalum nitride, tungsten nitride, or another metal nitride) is formed overlying the gate insulator layer. For advanced CMOS technology, gate processing is typically processed by first patterning a dummy polysilicon or amorphous silicon layer in the shape of the gate, acting as a placeholder until being further removed and replaced with a metal in a damascene way. This is referred to as the Replacement Metal Gate or RMG technique
Another insulating material may then be formed overlying the gate electrode material for use as a hard mask. This insulating material (such as silicon nitride) can be deposited using, for example, a sputtering or CVD technique. This insulating material can then be photolithographically patterned as desired to form a gate etch mask for etching of the gate structures 16 and 17. The underlying gate material is anisotropically etched into the desired topology that is defined by the gate etch mask. After patterning, the insulating material may remain on the gate structures 16 and 17 as gate caps. It should be appreciated that the particular composition of the gate structures 16 and 17 and the manner in which they are formed may vary from one embodiment to another, and that the brief description of the gate stack formation is not intended to be limiting or restrictive of the recited subject matter.
In the exemplary embodiment, spacers 18 are formed around the sides of gate structures 16 and 17. The spacers 18 can be fabricated using conventional process steps such as material deposition, photolithography, and etching. In this regard, formation of the spacers 18 may begin by conformally depositing a spacer material overlying the gate structures 16 and 17 and semiconductor substrate 12. The spacer material is an appropriate insulator, such as silicon nitride, and the spacer material can be deposited in a known manner by, for example, ALD, CVD, low pressure chemical vapor deposition (LPCVD), semi-atmospheric chemical vapor deposition (SACVD), or plasma enhanced chemical vapor deposition (PECVD). Thereafter, the spacer material is anisotropically and selectively etched to define the spacers 18. In practice, the spacer material can be etched by, for example, reactive ion etching (RIE) using a suitable etching chemistry.
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After the structure of the partially fabricated integrated circuit 10 in
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The fabrication method proceeds in
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The exemplary method continues with the formation of interconnect structures over the contacts 70 in
While the illustrated and described embodiments provide for formation of silicide contacts to gate structures formed from silicon material, the exemplary methods may be used during fabrication of integrated circuits with metal gates, such as replacement gates. For such embodiments, silicide contacts may be formed to the source/drain regions and not to the metal gates. Further, while embedded stress regions are formed around PFET gate structures in the illustrated embodiment, embedded stress regions may be formed around any selected gate structure, whether NFET or PFET, or may be absent from the integrated circuit.
As described herein, an embodiment of an improved integrated circuit fabrication process is implemented to form contacts to source/drain regions. Specifically, self-aligned contacts are formed on source/drain regions after deposition of interlayer dielectric material over the source/drain regions. As a result, contact punch-through is avoided. Specifically, methods described herein do not rely on landing the contact hole etch of the interlayer dielectric material on an already-formed source/drain contact. Rather, contact holes are etched into the interlayer dielectric material to expose the source/drain regions before the source/drain contacts are formed on the exposed source/drain regions. Further, both contacts and interconnects are formed in the contact holes and are bounded by the hole sidewalls. As a result, contact edges and interconnect edges are aligned.
Also, as described herein, an improved integrated circuit fabrication process is implemented to provide an increased or maximized amount of stress from embedded stress regions. Specifically, stress region cavities are formed in the semiconductor substrate and are filled with stress material. The upper surface of the stress material is formed to be co-planar with the upper surface of the semiconductor substrate. Additional silicon material supporting the formation of a silicide contact is deposited over the stress material and not in the stress region cavity. As a result, the amount of stress material in the stress region cavity is maximized.
To briefly summarize, exemplary fabrication methods described herein result in integrated circuits having source/drain contacts with reduced resistance and improved performance. Further, exemplary fabrication methods described herein result in integrated circuits having interconnect structures formed in alignment with source/drain contacts. Also, exemplary fabrication methods described herein result in integrated circuits having stress region cavities that are filled only with stress material before contacts are formed thereto.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.